View DSP56367_232297.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Revision 1.4 Published 01/02 DSP56367UM/D (Motorola Order Number)
DSP56367
24-Bit Digital Signal Processor User's Manual
Motorola, Incorporated Semiconductor Products Sector 6501 William Cannon Drive West Austin, TX 78735-8598
This document (and other documents) can be viewed on the World Wide Web at http://e-www.motorola.com/webapp/sps/prod_cat This manual is one of a set of three documents. You need the following manuals to have complete product information: Family Manual User's Manual Technical Data.
OnCE is a trademark of Motorola, Inc. MOTOROLA INC. 2001
Rev. 1.4; published 01/02 Order this document by DSP56367UM/D Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its product or products for the use intended. Motorola and b are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity /Affirmative Action Employer.
CONTENTS
Paragraph Number Section 1.1 1.2 1.3 1.4 1.4.1 1.4.1.1 1.4.1.2 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.4.9 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 Section 2.1 2.2 2.3 2.4 2.5 2.5.1 2.5.2 2.5.3 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 Title Page Number
1 DSP56367 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 DSP56300 Core Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 DSP56367 Audio Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 DSP56300 Core Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Data ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Data ALU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Multiplier-Accumulator (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Address Generation Unit (AGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Program Control Unit (PCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Direct Memory Access (DMA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 PLL-based Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 JTAG TAP and OnCE Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Off-Chip Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Host Interface (HDI08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Triple Timer (TEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Enhanced Serial Audio Interface (ESAI) . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Enhanced Serial Audio Interface 1 (ESAI_1) . . . . . . . . . . . . . . . . . . . . . . . 1-13 Serial Host Interface (SHI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Digital Audio Transmitter (DAX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 2 Signal/Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Signal Groupings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Clock and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 External Memory Expansion Port (Port A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 External Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 External Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 External Bus Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Parallel Host Interface (HDI08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Serial Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Enhanced Serial Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Enhanced Serial Audio Interface_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 SPDIF Transmitter Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 JTAG/OnCE Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
MOTOROLA
3
CONTENTS
Paragraph Number Section 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.10.1 3.10.2 3.10.3 3.11 3.12 3.13 3.13.1 3.14 3.15 3.16 3.17 3.18 Section 4.1 4.2 4.3 4.4 4.4.1 Title Page Number
3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6 External Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7 Phase Lock Loop (PLL) Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8 Reset, Stop, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . .3-8 External Memory Expansion Port (Port A) . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 SRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 DRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19 Arbitration Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-35 Parallel Host Interface (HDI08) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-36 Serial Host Interface SPI Protocol Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-45 Serial Host Interface (SHI) I2C Protocol Timing. . . . . . . . . . . . . . . . . . . . . . . .3-51 Programming the Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-53 Enhanced Serial Audio Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-55 Digital Audio Transmitter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-61 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-62 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-63 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-64 4 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Thermal Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Electrical Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 Power Consumption Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4 PLL Performance Issues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5 Input (EXTAL) Jitter Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
Section 5 Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 5.1 Data and Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 5.1.1 Reserved Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12 5.1.2 Program ROM Area Reserved for Motorola Use. . . . . . . . . . . . . . . . . . . . .5-12 5.1.3 Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12 5.1.4 Dynamic Memory Configuration Switching . . . . . . . . . . . . . . . . . . . . . . . .5-12 5.1.5 External Memory Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13 5.2 Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14 Section 6 Core Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 6.2 Operating Mode Register (OMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
4
MOTOROLA
CONTENTS
Paragraph Number 6.2.1 6.2.2 6.2.3 6.2.4 6.3 6.4 6.5 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.7 6.8 6.9 Title Page Number
Asynchronous Bus Arbitration Enable (ABE) - Bit 13. . . . . . . . . . . . . . . . . 6-2 Address Attribute Priority Disable (APD) - Bit 14. . . . . . . . . . . . . . . . . . . . 6-2 Address Tracing Enable (ATE) - Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Patch Enable (PEN) - Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 DMA Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 PLL Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 PLL Multiplication Factor (MF0-MF11) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 PLL Pre-Divider Factor (PD0-PD3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Crystal Range Bit (XTLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 XTAL Disable Bit (XTLD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Device Identification (ID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 JTAG Identification (ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 JTAG Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 7-1 7-1 7-1 7-1 7-2 7-2 7-2 7-2
Section 7 General Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Port B Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Port C Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 Port D Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.4 Port E Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.5 Timer/Event Counter Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Section 8.1 8.2 8.2.1 8.2.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.3.1 8.5.3.2 8.5.3.3 8.5.3.4 8.5.3.5 8.5.3.6 8.5.4
8 Host Interface (HDI08). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 HDI08 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Interface - DSP side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Interface - Host Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 HDI08 Host Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 HDI08 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 HDI08 - DSP-Side Programmer's Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Host Receive Data Register (HORX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Host Transmit Data Register (HOTX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Host Control Register (HCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 HCR Host Receive Interrupt Enable (HRIE) Bit 0 . . . . . . . . . . . . . . . . . 8-7 HCR Host Transmit Interrupt Enable (HTIE) Bit 1 . . . . . . . . . . . . . . . . 8-8 HCR Host Command Interrupt Enable (HCIE) Bit 2 . . . . . . . . . . . . . . . 8-8 HCR Host Flags 2,3 (HF2,HF3) Bits 3-4 . . . . . . . . . . . . . . . . . . . . . . . . 8-8 HCR Host DMA Mode Control Bits (HDM0, HDM1, HDM2) Bits 5-7 8-8 HCR Reserved Bits 8-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 Host Status Register (HSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
MOTOROLA
5
CONTENTS
Paragraph Number 8.5.4.1 8.5.4.2 8.5.4.3 8.5.4.4 8.5.4.5 8.5.4.6 8.5.5 8.5.5.1 8.5.5.2 8.5.6 8.5.6.1 8.5.6.2 8.5.6.3 8.5.6.4 8.5.6.5 8.5.6.6 8.5.6.7 8.5.6.8 8.5.6.9 8.5.6.10 8.5.6.11 8.5.6.12 8.5.6.13 8.5.6.14 8.5.6.15 8.5.6.16 8.5.7 8.5.8 8.5.9 8.5.10 8.6 8.6.1 8.6.1.1 8.6.1.2 8.6.1.3 8.6.1.4 8.6.1.5 8.6.1.6 8.6.1.7 8.6.1.8 8.6.2 8.6.2.1 8.6.2.2 Title Page Number
HSR Host Receive Data Full (HRDF) Bit 0. . . . . . . . . . . . . . . . . . . . . .8-10 HSR Host Transmit Data Empty (HTDE) Bit 1. . . . . . . . . . . . . . . . . . .8-11 HSR Host Command Pending (HCP) Bit 2 . . . . . . . . . . . . . . . . . . . . . .8-11 HSR Host Flags 0,1 (HF0,HF1) Bits 3-4 . . . . . . . . . . . . . . . . . . . . . . . .8-11 HSR Reserved Bits 5-6, 8-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-11 HSR DMA Status (DMA) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-11 Host Base Address Register (HBAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-12 HBAR Base Address (BA[10:3]) Bits 0-7 . . . . . . . . . . . . . . . . . . . . . . .8-12 HBAR Reserved Bits 8-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-12 Host Port Control Register (HPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-13 HPCR Host GPIO Port Enable (HGEN) Bit 0 . . . . . . . . . . . . . . . . . . . .8-13 HPCR Host Address Line 8 Enable (HA8EN) Bit 1 . . . . . . . . . . . . . . .8-13 HPCR Host Address Line 9 Enable (HA9EN) Bit 2 . . . . . . . . . . . . . . .8-13 HPCR Host Chip Select Enable (HCSEN) Bit 3 . . . . . . . . . . . . . . . . . .8-13 HPCR Host Request Enable (HREN) Bit 4 . . . . . . . . . . . . . . . . . . . . . .8-14 HPCR Host Acknowledge Enable (HAEN) Bit 5 . . . . . . . . . . . . . . . . .8-14 HPCR Host Enable (HEN) Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-14 HPCR Reserved Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-14 HPCR Host Request Open Drain (HROD) Bit 8 . . . . . . . . . . . . . . . . . .8-14 HPCR Host Data Strobe Polarity (HDSP) Bit 9. . . . . . . . . . . . . . . . . . .8-14 HPCR Host Address Strobe Polarity (HASP) Bit 10 . . . . . . . . . . . . . . .8-15 HPCR Host Multiplexed bus (HMUX) Bit 11 . . . . . . . . . . . . . . . . . . . .8-15 HPCR Host Dual Data Strobe (HDDS) Bit 12. . . . . . . . . . . . . . . . . . . .8-15 HPCR Host Chip Select Polarity (HCSP) Bit 13 . . . . . . . . . . . . . . . . . .8-16 HPCR Host Request Polarity (HRP) Bit 14 . . . . . . . . . . . . . . . . . . . . . .8-16 HPCR Host Acknowledge Polarity (HAP) Bit 15 . . . . . . . . . . . . . . . . .8-16 Data direction register (HDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-16 Host Data Register (HDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-17 DSP-Side Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-17 Host Interface DSP Core Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-18 HDI08 - External Host Programmer's Model . . . . . . . . . . . . . . . . . . . . . . . . . .8-19 Interface Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-21 ICR Receive Request Enable (RREQ) Bit 0 . . . . . . . . . . . . . . . . . . . . .8-21 ICR Transmit Request Enable (TREQ) Bit 1 . . . . . . . . . . . . . . . . . . . . .8-21 ICR Double Host Request (HDRQ) Bit 2 . . . . . . . . . . . . . . . . . . . . . . .8-22 ICR Host Flag 0 (HF0) Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22 ICR Host Flag 1 (HF1) Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-23 ICR Host Little Endian (HLEND) Bit 5. . . . . . . . . . . . . . . . . . . . . . . . .8-23 ICR Host Mode Control (HM1 and HM0 bits) Bits 5-6 . . . . . . . . . . . .8-23 ICR Initialize Bit (INIT) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-24 Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-25 CVR Host Vector (HV[6:0]) Bits 0-6 . . . . . . . . . . . . . . . . . . . . . . . . . .8-25 CVR Host Command Bit (HC) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . .8-25
6
MOTOROLA
CONTENTS
Paragraph Number 8.6.3 8.6.3.1 8.6.3.2 8.6.3.3 8.6.3.4 8.6.3.5 8.6.3.6 8.6.3.7 8.6.4 8.6.5 8.6.6 8.6.7 8.6.8 8.7 8.7.1 8.7.2 8.7.3 Section 9.1 9.2 9.3 9.4 9.5 9.5.1 9.5.2 9.5.3 9.5.4 9.5.4.1 9.5.4.2 9.5.5 9.5.5.1 9.5.5.2 9.5.5.3 9.5.5.4 9.5.5.5 9.5.6 9.5.6.1 9.5.6.2 9.5.6.3 9.5.6.4 9.5.6.5 9.5.6.6 Title Page Number 8-25 8-26 8-26 8-26 8-26 8-27 8-27 8-27 8-27 8-28 8-28 8-29 8-29 8-30 8-30 8-30 8-31
Interface Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR Receive Data Register Full (RXDF) Bit 0 . . . . . . . . . . . . . . . . . . . ISR Transmit Data Register Empty (TXDE) Bit 1 . . . . . . . . . . . . . . . . ISR Transmitter Ready (TRDY) Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . ISR Host Flag 2 (HF2) Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR Host Flag 3 (HF3) Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR Reserved Bits 5-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR Host Request (HREQ) Bit 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Byte Registers (RXH:RXM:RXL) . . . . . . . . . . . . . . . . . . . . . . . . Transmit Byte Registers (TXH:TXM:TXL) . . . . . . . . . . . . . . . . . . . . . . . . Host Side Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose INPUT/OUTPUT (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . Servicing The Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDI08 Host Processor Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Servicing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 Serial Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Serial Host Interface Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Characteristics Of The SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 SHI Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 Serial Host Interface Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 SHI Input/Output Shift Register (IOSR)--Host Side . . . . . . . . . . . . . . . . . . 9-7 SHI Host Transmit Data Register (HTX)--DSP Side . . . . . . . . . . . . . . . . . 9-8 SHI Host Receive Data FIFO (HRX)--DSP Side . . . . . . . . . . . . . . . . . . . . 9-8 SHI Slave Address Register (HSAR)--DSP Side . . . . . . . . . . . . . . . . . . . . 9-9 HSAR Reserved Bits--Bits 19, 17-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 HSAR I2C Slave Address (HA[6:3], HA1)--Bits 23-20,18 . . . . . . . . . 9-9 SHI Clock Control Register (HCKR)--DSP Side . . . . . . . . . . . . . . . . . . . . 9-9 Clock Phase and Polarity (CPHA and CPOL)--Bits 1-0. . . . . . . . . . . 9-10 HCKR Prescaler Rate Select (HRS)--Bit 2 . . . . . . . . . . . . . . . . . . . . . 9-11 HCKR Divider Modulus Select (HDM[7:0])--Bits 10-3 . . . . . . . . . . 9-11 HCKR Reserved Bits--Bits 23-14, 11. . . . . . . . . . . . . . . . . . . . . . . . . 9-12 HCKR Filter Mode (HFM[1:0]) -- Bits 13-12 . . . . . . . . . . . . . . . . . . 9-12 SHI Control/Status Register (HCSR)--DSP Side . . . . . . . . . . . . . . . . . . . 9-13 HCSR Host Enable (HEN)--Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 HCSR I2C/SPI Selection (HI2C)--Bit 1 . . . . . . . . . . . . . . . . . . . . . . . 9-13 HCSR Serial Host Interface Mode (HM[1:0])--Bits 3-2. . . . . . . . . . . 9-13 HCSR I2C Clock Freeze (HCKFR)--Bit 4 . . . . . . . . . . . . . . . . . . . . . 9-14 HCSR FIFO-Enable Control (HFIFO)--Bit 5 . . . . . . . . . . . . . . . . . . . 9-14 HCSR Master Mode (HMST)--Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
MOTOROLA
7
CONTENTS
Paragraph Number 9.5.6.7 9.5.6.8 9.5.6.9 9.5.6.10 9.5.6.11 9.5.6.12 9.5.6.13 9.5.6.14 9.5.6.15 9.5.6.16 9.5.6.17 9.5.6.18 9.5.6.19 9.6 9.6.1 9.6.2 9.7 9.7.1 9.7.2 9.7.3 9.7.3.1 9.7.3.2 9.7.4 9.7.4.1 9.7.4.2 9.7.5 Title Page Number
HCSR Host-Request Enable (HRQE[1:0])--Bits 8-7 . . . . . . . . . . . . . .9-15 HCSR Idle (HIDLE)--Bit 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-15 HCSR Bus-Error Interrupt Enable (HBIE)--Bit 10. . . . . . . . . . . . . . . .9-16 HCSR Transmit-Interrupt Enable (HTIE)--Bit 11 . . . . . . . . . . . . . . . .9-16 HCSR Receive Interrupt Enable (HRIE[1:0])--Bits 13-12 . . . . . . . . .9-16 HCSR Host Transmit Underrun Error (HTUE)--Bit 14 . . . . . . . . . . . .9-17 HCSR Host Transmit Data Empty (HTDE)--Bit 15 . . . . . . . . . . . . . . .9-17 HCSR Reserved Bits--Bits 23, 18 and 16 . . . . . . . . . . . . . . . . . . . . . . .9-17 Host Receive FIFO Not Empty (HRNE)--Bit 17 . . . . . . . . . . . . . . . . .9-18 Host Receive FIFO Full (HRFF)--Bit 19 . . . . . . . . . . . . . . . . . . . . . . .9-18 Host Receive Overrun Error (HROE)--Bit 20 . . . . . . . . . . . . . . . . . . .9-18 Host Bus Error (HBER)--Bit 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-18 HCSR Host Busy (HBUSY)--Bit 22. . . . . . . . . . . . . . . . . . . . . . . . . . .9-18 Characteristics Of The I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-19 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-19 I2C Data Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-21 SHI Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-22 SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-22 SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-23 I2C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-24 Receive Data in I2C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-25 Transmit Data In I2C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-26 2 I C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-27 Receive Data in I2C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-28 Transmit Data In I2C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-28 SHI Operation During DSP Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-29
Section 10 Enhanced Serial Audio Interface (ESAI). . . . . . . . . . . . . . . . . . . . . . . .10-1 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 10.2 ESAI Data and Control Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 10.2.1 Serial Transmit 0 Data Pin (SDO0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 10.2.2 Serial Transmit 1 Data Pin (SDO1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 10.2.3 Serial Transmit 2/Receive 3 Data Pin (SDO2/SDI3) . . . . . . . . . . . . . . . . . .10-3 10.2.4 Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2) . . . . . . . . . . . . . . . . . .10-4 10.2.5 Serial Transmit 4/Receive 1 Data Pin (SDO4/SDI1) . . . . . . . . . . . . . . . . . .10-4 10.2.6 Serial Transmit 5/Receive 0 Data Pin (SDO5/SDI0) . . . . . . . . . . . . . . . . . .10-5 10.2.7 Receiver Serial Clock (SCKR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5 10.2.8 Transmitter Serial Clock (SCKT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6 10.2.9 Frame Sync for Receiver (FSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-7 10.2.10 Frame Sync for Transmitter (FST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-8 10.2.11 High Frequency Clock for Transmitter (HCKT) . . . . . . . . . . . . . . . . . . . . .10-8 10.2.12 High Frequency Clock for Receiver (HCKR) . . . . . . . . . . . . . . . . . . . . . . .10-8 10.3 ESAI Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-9
8
MOTOROLA
CONTENTS
Paragraph Number 10.3.1 10.3.1.1 10.3.1.2 10.3.1.3 10.3.1.4 10.3.1.5 10.3.1.6 10.3.1.7 10.3.1.8 10.3.1.9 10.3.1.10 10.3.2 10.3.2.1 10.3.2.2 10.3.2.3 10.3.2.4 10.3.2.5 10.3.2.6 10.3.2.7 10.3.2.8 10.3.2.9 10.3.2.10 10.3.2.11 10.3.2.12 10.3.2.13 10.3.2.14 10.3.2.15 10.3.2.16 10.3.2.17 10.3.2.18 10.3.2.19 10.3.3 10.3.3.1 10.3.3.2 10.3.3.3 10.3.3.4 10.3.3.5 10.3.3.6 10.3.3.7 10.3.3.8 10.3.3.9 10.3.3.10 10.3.4 Title Page Number
ESAI Transmitter Clock Control Register (TCCR) . . . . . . . . . . . . . . . . . . 10-9 TCCR Transmit Prescale Modulus Select (TPM7-TPM0) - Bits 0-7 10-10 TCCR Transmit Prescaler Range (TPSR) - Bit 8 . . . . . . . . . . . . . . . . 10-12 TCCR Tx Frame Rate Divider Control (TDC4-TDC0) - Bits 9-13 . 10-12 TCCR Tx High Frequency Clock Divider (TFP3-TFP0) - Bits 14-17 10-13 TCCR Transmit Clock Polarity (TCKP) - Bit 18 . . . . . . . . . . . . . . . . 10-14 TCCR Transmit Frame Sync Polarity (TFSP) - Bit 19 . . . . . . . . . . . . 10-14 TCCR Transmit High Frequency Clock Polarity (THCKP) - Bit 20 . 10-14 TCCR Transmit Clock Source Direction (TCKD) - Bit 21 . . . . . . . . 10-14 TCCR Transmit Frame Sync Signal Direction (TFSD) - Bit 22. . . . . 10-15 TCCR Transmit High Frequency Clock Direction (THCKD) - Bit 23 10-15 ESAI Transmit Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 TCR ESAI Transmit 0 Enable (TE0) - Bit 0. . . . . . . . . . . . . . . . . . . . 10-15 TCR ESAI Transmit 1 Enable (TE1) - Bit 1. . . . . . . . . . . . . . . . . . . . 10-16 TCR ESAI Transmit 2 Enable (TE2) - Bit 2. . . . . . . . . . . . . . . . . . . . 10-16 TCR ESAI Transmit 3 Enable (TE3) - Bit 3. . . . . . . . . . . . . . . . . . . . 10-17 TCR ESAI Transmit 4 Enable (TE4) - Bit 4. . . . . . . . . . . . . . . . . . . . 10-17 TCR ESAI Transmit 5 Enable (TE5) - Bit 5. . . . . . . . . . . . . . . . . . . . 10-18 TCR Transmit Shift Direction (TSHFD) - Bit 6 . . . . . . . . . . . . . . . . . 10-18 TCR Transmit Word Alignment Control (TWA) - Bit 7 . . . . . . . . . . 10-18 TCR Transmit Network Mode Control (TMOD1-TMOD0) - Bits 8-910-19 TCR Tx Slot and Word Length Select (TSWS4-TSWS0) - Bits 10-1410-21 TCR Transmit Frame Sync Length (TFSL) - Bit 15. . . . . . . . . . . . . . 10-22 TCR Transmit Frame Sync Relative Timing (TFSR) - Bit 16 . . . . . . 10-24 TCR Transmit Zero Padding Control (PADC) - Bit 17 . . . . . . . . . . . 10-24 TCR Reserved Bit - Bits 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 TCR Transmit Section Personal Reset (TPR) - Bit 19 . . . . . . . . . . . . 10-24 TCR Transmit Exception Interrupt Enable (TEIE) - Bit 20 . . . . . . . . 10-25 TCR Transmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21. . . 10-25 TCR Transmit Interrupt Enable (TIE) - Bit 22 . . . . . . . . . . . . . . . . . . 10-25 TCR Transmit Last Slot Interrupt Enable (TLIE) - Bit 23 . . . . . . . . . 10-25 ESAI Receive Clock Control Register (RCCR) . . . . . . . . . . . . . . . . . . . . 10-26 RCCR Receiver Prescale Modulus Select (RPM7-RPM0) - Bits 7-0 10-26 RCCR Receiver Prescaler Range (RPSR) - Bit 8 . . . . . . . . . . . . . . . . 10-26 RCCR Rx Frame Rate Divider Control (RDC4-RDC0) - Bits 9-13 . 10-26 RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 14-1710-27 RCCR Receiver Clock Polarity (RCKP) - Bit 18 . . . . . . . . . . . . . . . . 10-27 RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19. . . . . . . . . . . . 10-27 RCCR Receiver High Frequency Clock Polarity (RHCKP) - Bit 20 . 10-28 RCCR Receiver Clock Source Direction (RCKD) - Bit 21 . . . . . . . . 10-28 RCCR Receiver Frame Sync Signal Direction (RFSD) - Bit 22 . . . . 10-28 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 2310-29 ESAI Receive Control Register (RCR). . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
MOTOROLA
9
CONTENTS
Paragraph Number 10.3.4.1 10.3.4.2 10.3.4.3 10.3.4.4 10.3.4.5 10.3.4.6 10.3.4.7 10.3.4.8 10.3.4.9 10.3.4.10 10.3.4.11 10.3.4.12 10.3.4.13 10.3.4.14 10.3.4.15 10.3.4.16 10.3.5 10.3.5.1 10.3.5.2 10.3.5.3 10.3.5.4 10.3.5.5 10.3.5.6 10.3.5.7 10.3.6 10.3.6.1 10.3.6.2 10.3.6.3 10.3.6.4 10.3.6.5 10.3.6.6 10.3.6.7 10.3.6.8 10.3.6.9 10.3.6.10 10.3.6.11 10.3.6.12 10.3.6.13 10.3.6.14 10.3.7 10.3.8 10.3.9 10.3.10 Title Page Number
RCR ESAI Receiver 0 Enable (RE0) - Bit 0 . . . . . . . . . . . . . . . . . . . .10-30 RCR ESAI Receiver 1 Enable (RE1) - Bit 1 . . . . . . . . . . . . . . . . . . . .10-30 RCR ESAI Receiver 2 Enable (RE2) - Bit 2 . . . . . . . . . . . . . . . . . . . .10-31 RCR ESAI Receiver 3 Enable (RE3) - Bit 3 . . . . . . . . . . . . . . . . . . . .10-31 RCR Reserved Bits - Bits 4-5, 17-18 . . . . . . . . . . . . . . . . . . . . . . . . . .10-31 RCR Receiver Shift Direction (RSHFD) - Bit 6 . . . . . . . . . . . . . . . . .10-31 RCR Receiver Word Alignment Control (RWA) - Bit 7 . . . . . . . . . . .10-31 RCR Receiver Network Mode Control (RMOD1-RMOD0) - Bits 8-910-31 RCR Receiver Slot and Word Select (RSWS4-RSWS0) - Bits 10-14 .10-32 RCR Receiver Frame Sync Length (RFSL) - Bit 15 . . . . . . . . . . . . . .10-33 RCR Receiver Frame Sync Relative Timing (RFSR) - Bit 16. . . . . . .10-33 RCR Receiver Section Personal Reset (RPR) - Bit 19. . . . . . . . . . . . .10-33 RCR Receive Exception Interrupt Enable (REIE) - Bit 20 . . . . . . . . .10-34 RCR Receive Even Slot Data Interrupt Enable (REDIE) - Bit 21 . . . .10-34 RCR Receive Interrupt Enable (RIE) - Bit 22 . . . . . . . . . . . . . . . . . . .10-34 RCR Receive Last Slot Interrupt Enable (RLIE) - Bit 23 . . . . . . . . . .10-34 ESAI Common Control Register (SAICR) . . . . . . . . . . . . . . . . . . . . . . . .10-35 SAICR Serial Output Flag 0 (OF0) - Bit 0. . . . . . . . . . . . . . . . . . . . . .10-35 SAICR Serial Output Flag 1 (OF1) - Bit 1. . . . . . . . . . . . . . . . . . . . . .10-35 SAICR Serial Output Flag 2 (OF2) - Bit 2. . . . . . . . . . . . . . . . . . . . . .10-35 SAICR Reserved Bits - Bits 3-5, 9-23 . . . . . . . . . . . . . . . . . . . . . . . . .10-36 SAICR Synchronous Mode Selection (SYN) - Bit 6 . . . . . . . . . . . . . .10-36 SAICR Transmit External Buffer Enable (TEBE) - Bit 7 . . . . . . . . . .10-36 SAICR Alignment Control (ALC) - Bit 8 . . . . . . . . . . . . . . . . . . . . . .10-36 ESAI Status Register (SAISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-38 SAISR Serial Input Flag 0 (IF0) - Bit 0 . . . . . . . . . . . . . . . . . . . . . . . .10-38 SAISR Serial Input Flag 1 (IF1) - Bit 1 . . . . . . . . . . . . . . . . . . . . . . . .10-38 SAISR Serial Input Flag 2 (IF2) - Bit 2 . . . . . . . . . . . . . . . . . . . . . . . .10-38 SAISR Reserved Bits - Bits 3-5, 11-12, 18-23. . . . . . . . . . . . . . . . . . .10-39 SAISR Receive Frame Sync Flag (RFS) - Bit 6. . . . . . . . . . . . . . . . . .10-39 SAISR Receiver Overrun Error Flag (ROE) - Bit 7. . . . . . . . . . . . . . .10-39 SAISR Receive Data Register Full (RDF) - Bit 8 . . . . . . . . . . . . . . . .10-39 SAISR Receive Even-Data Register Full (REDF) - Bit 9 . . . . . . . . . .10-39 SAISR Receive Odd-Data Register Full (RODF) - Bit 10. . . . . . . . . .10-39 SAISR Transmit Frame Sync Flag (TFS) - Bit 13 . . . . . . . . . . . . . . . .10-40 SAISR Transmit Underrun Error Flag (TUE) - Bit 14. . . . . . . . . . . . .10-40 SAISR Transmit Data Register Empty (TDE) - Bit 15 . . . . . . . . . . . .10-40 SAISR Transmit Even-Data Register Empty (TEDE) - Bit 16 . . . . . .10-40 SAISR Transmit Odd-Data Register Empty (TODE) - Bit 17 . . . . . . .10-41 ESAI Receive Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-44 ESAI Receive Data Registers (RX3, RX2, RX1, RX0) . . . . . . . . . . . . . . .10-44 ESAI Transmit Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-44 ESAI Transmit Data Registers (TX5, TX4, TX3, TX2,TX1,TX0) . . . . . .10-44
10
MOTOROLA
CONTENTS
Paragraph Number 10.3.11 10.3.12 10.3.13 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.4.1 10.4.4.2 10.4.4.3 10.4.4.4 10.4.5 10.5 10.5.1 10.5.2 10.5.3 10.6 10.6.1 10.6.2 10.6.3 Title Page Number 10-45 10-45 10-46 10-48 10-48 10-48 10-49 10-50 10-50 10-51 10-51 10-52 10-52 10-53 10-53 10-54 10-55 10-56 10-56 10-56 10-57
ESAI Time Slot Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Slot Mask Registers (TSMA, TSMB) . . . . . . . . . . . . . . . . . . . . Receive Slot Mask Registers (RSMA, RSMB). . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes - Normal, Network, and On-Demand . . . . . . . . . . . . . Normal/Network/On-Demand Mode Selection . . . . . . . . . . . . . . . . . Synchronous/Asynchronous Operating Modes. . . . . . . . . . . . . . . . . . Frame Sync Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shift Direction Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial I/O Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO - Pins and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Control Register (PCRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Direction Register (PRRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Data register (PDRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI Initialization Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initializing the ESAI Using Individual Reset . . . . . . . . . . . . . . . . . . . . . . Initializing Just the ESAI Transmitter Section . . . . . . . . . . . . . . . . . . . . . Initializing Just the ESAI Receiver Section . . . . . . . . . . . . . . . . . . . . . . .
Section 11 Enhanced Serial Audio Interface 1 (ESAI_1) . . . . . . . . . . . . . . . . . . . 11-1 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 ESAI_1 Data and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2.1 Serial Transmit 0 Data Pin (SDO0_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2.2 Serial Transmit 1 Data Pin (SDO1_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2.3 Serial Transmit 2/Receive 3 Data Pin (SDO2_1/SDI3_1) . . . . . . . . . . . . . 11-3 11.2.4 Serial Transmit 3/Receive 2 Data Pin (SDO3_1/SDI2_1) . . . . . . . . . . . . . 11-3 11.2.5 Serial Transmit 4/Receive 1 Data Pin (SDO4_1/SDI1_1) . . . . . . . . . . . . . 11-4 11.2.6 Serial Transmit 5/Receive 0 Data Pin (SDO5_1/SDI0_1) . . . . . . . . . . . . . 11-4 11.2.7 Receiver Serial Clock (SCKR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2.8 Transmitter Serial Clock (SCKT_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2.9 Frame Sync for Receiver (FSR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.10 Frame Sync for Transmitter (FST_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.3 ESAI_1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.3.1 ESAI_1 Multiplex Control Register (EMUXR) . . . . . . . . . . . . . . . . . . . . . 11-6 11.3.2 ESAI_1 Transmitter Clock Control Register (TCCR_1) . . . . . . . . . . . . . . 11-6 11.3.2.1 TCCR_1 Tx High Freq. Clock Divider (TFP3-TFP0) - Bits 14-17 . . . 11-7 11.3.2.2 TCCR_1 Tx High Freq. Clock Polarity (THCKP) - Bit 20 . . . . . . . . . 11-7 11.3.2.3 TCCR_1 Tx High Freq. Clock Direction (THCKD) - Bit 23 . . . . . . . . 11-7 11.3.3 ESAI_1 Transmit Control Register (TCR_1) . . . . . . . . . . . . . . . . . . . . . . 11-10 11.3.4 ESAI_1 Receive Clock Control Register (RCCR_1) . . . . . . . . . . . . . . . . 11-10
MOTOROLA
11
CONTENTS
Paragraph Number 11.3.4.1 11.3.4.2 11.3.4.3 11.3.5 11.3.6 11.3.7 11.3.8 11.3.9 11.3.10 11.3.11 11.3.12 11.3.13 11.3.14 11.4 11.4.1 11.5 11.5.1 11.5.2 11.5.3 Section 12.1 12.2 12.3 12.4 12.5 12.5.1 12.5.2 12.5.3 12.5.4 12.5.4.1 12.5.4.2 12.5.4.3 12.5.4.4 12.5.4.5 12.5.4.6 12.5.4.7 12.5.5 12.5.6 12.5.6.1 12.5.6.2 12.5.6.3 12.5.6.4 Title Page Number
RCCR_1 Rx High Freq. Clock Divider (RFP3-RFP0) - Bits 14-17 . .11-11 RCCR_1 Rx High Freq. Clock Polarity (RHCKP) - Bit 20 . . . . . . . . .11-11 RCCR_1 Rx High Freq. Clock Direction (RHCKD) - Bit 23 . . . . . . .11-11 ESAI_1 Receive Control Register (RCR_1) . . . . . . . . . . . . . . . . . . . . . . .11-11 ESAI_1 Common Control Register (SAICR_1) . . . . . . . . . . . . . . . . . . . .11-12 ESAI_1 Status Register (SAISR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12 ESAI_1 Receive Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-13 ESAI_1 Receive Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-13 ESAI_1 Transmit Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-13 ESAI_1 Transmit Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-13 ESAI_1 Time Slot Register (TSR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-14 Transmit Slot Mask Registers (TSMA_1, TSMB_1). . . . . . . . . . . . . . . . .11-14 Receive Slot Mask Registers (RSMA_1, RSMB_1) . . . . . . . . . . . . . . . . .11-15 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16 ESAI_1 After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16 GPIO - Pins and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16 Port E Control Register (PCRE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16 Port E Direction Register (PRRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-17 Port E Data register (PDRE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-18 12 Digital Audio Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1 DAX Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2 DAX Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-3 DAX Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-4 DAX Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5 DAX Audio Data Register (XADR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5 DAX Audio Data Buffers (XADBUFA / XADBUFB) . . . . . . . . . . . . . . . .12-6 DAX Audio Data Shift Register (XADSR) . . . . . . . . . . . . . . . . . . . . . . . . .12-6 DAX Non-Audio Data Register (XNADR) . . . . . . . . . . . . . . . . . . . . . . . . .12-6 DAX Channel A Validity (XVA)--Bit 10. . . . . . . . . . . . . . . . . . . . . . .12-6 DAX Channel A User Data (XUA)--Bit 11 . . . . . . . . . . . . . . . . . . . . .12-6 DAX Channel A Channel Status (XCA)--Bit 12 . . . . . . . . . . . . . . . . .12-7 DAX Channel B Validity (XVB)--Bit 13 . . . . . . . . . . . . . . . . . . . . . . .12-7 DAX Channel B User Data (XUB)--Bit 14 . . . . . . . . . . . . . . . . . . . . .12-7 DAX Channel B Channel Status (XCB)--Bit 15. . . . . . . . . . . . . . . . . .12-7 XNADR Reserved Bits--Bits 0-9, 16-23 . . . . . . . . . . . . . . . . . . . . . . .12-7 DAX Non-Audio Data Buffer (XNADBUF) . . . . . . . . . . . . . . . . . . . . . . . .12-7 DAX Control Register (XCTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-7 Audio Data Register Empty Interrupt Enable (XDIE)--Bit 0 . . . . . . . .12-8 Underrun Error Interrupt Enable (XUIE)--Bit 1 . . . . . . . . . . . . . . . . . .12-8 Block Transferred Interrupt Enable (XBIE)--Bit 2 . . . . . . . . . . . . . . . .12-8 DAX Clock Input Select (XCS[1:0])--Bits 3-4 . . . . . . . . . . . . . . . . . .12-8
12
MOTOROLA
CONTENTS
Paragraph Number 12.5.6.5 12.5.6.6 12.5.7 12.5.7.1 12.5.7.2 12.5.7.3 12.5.7.4 12.5.8 12.5.9 12.5.10 12.5.11 12.5.12 12.6 12.6.1 12.6.2 12.6.3 12.6.4 12.6.5 12.7 12.7.1 12.7.2 12.7.3 Title Page Number
DAX Start Block (XSB)--Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 XCTR Reserved Bits--Bits 6-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 DAX Status Register (XSTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 DAX Audio Data Register Empty (XADE)--Bit 0 . . . . . . . . . . . . . . . 12-9 DAX Transmit Underrun Error Flag (XAUR)--Bit 1 . . . . . . . . . . . . . 12-9 DAX Block Transfer Flag (XBLK)--Bit 2 . . . . . . . . . . . . . . . . . . . . . 12-9 XSTR Reserved Bits--Bits 3-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 DAX Parity Generator (PRTYG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 DAX Biphase Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 DAX Preamble Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 DAX Clock Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 DAX State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 DAX Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 Initiating A Transmit Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 Audio Data Register Empty Interrupt Handling . . . . . . . . . . . . . . . . . . . . 12-13 Block Transferred Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 DAX operation with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 DAX Operation During Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 GPIO (PORT D) - Pins and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 Port D Control Register (PCRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 Port D Direction Register (PRRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 Port D Data Register (PDRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 13-1 13-1 13-1 13-1 13-2 13-3 13-5 13-5 13-5 13-5 13-6 13-6 13-6 13-6 13-7 13-7 13-7 13-7 13-7 13-9
Section 13 Timer/ Event Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Timer/Event Counter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.1 Timer/Event Counter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.2 Individual Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 Timer/Event Counter Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.1 Prescaler Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2 Timer Prescaler Load Register (TPLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.1 TPLR Prescaler Preload Value PL[20:0] Bits 20-0 . . . . . . . . . . . . . . . 13.3.2.2 TPLR Prescaler Source PS[1:0] Bits 22-21 . . . . . . . . . . . . . . . . . . . . . 13.3.2.3 TPLR Reserved Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3 Timer Prescaler Count Register (TPCR). . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3.1 TPCR Prescaler Counter Value PC[20:0] Bits 20-0. . . . . . . . . . . . . . . 13.3.3.2 TPCR Reserved Bits 23-21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.4 Timer Control/Status Register (TCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.4.1 TCSR Timer Enable (TE) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.4.2 TCSR Timer Overflow Interrupt Enable (TOIE) Bit 1. . . . . . . . . . . . . 13.3.4.3 TCSR Timer Compare Interrupt Enable (TCIE) Bit 2 . . . . . . . . . . . . . 13.3.4.4 TCSR Timer Control (TC[3:0]) Bits 4-7 . . . . . . . . . . . . . . . . . . . . . . . 13.3.4.5 TCSR Inverter (INV) Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOTOROLA
13
CONTENTS
Paragraph Number Title Page Number
13.3.4.6 TCSR Timer Reload Mode (TRM) Bit 9 . . . . . . . . . . . . . . . . . . . . . . .13-10 13.3.4.7 TCSR Direction (DIR) Bit 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-10 13.3.4.8 TCSR Data Input (DI) Bit 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-11 13.3.4.9 TCSR Data Output (DO) Bit 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-11 13.3.4.10 TCSR Prescaler Clock Enable (PCE) Bit 15 . . . . . . . . . . . . . . . . . . . .13-11 13.3.4.11 TCSR Timer Overflow Flag (TOF) Bit 20. . . . . . . . . . . . . . . . . . . . . .13-11 13.3.4.12 TCSR Timer Compare Flag (TCF) Bit 21 . . . . . . . . . . . . . . . . . . . . . .13-12 13.3.4.13 TCSR Reserved Bits (Bits 3, 10, 14, 16-19, 22, 23) . . . . . . . . . . . . . .13-12 13.3.5 Timer Load Register (TLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-12 13.3.6 Timer Compare Register (TCPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-13 13.3.7 Timer Count Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-13 13.4 Timer Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-13 13.4.1 Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-14 13.4.1.1 Timer GPIO (Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-14 13.4.1.2 Timer Pulse (Mode 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-15 13.4.1.3 Timer Toggle (Mode 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-16 13.4.1.4 Timer Event Counter (Mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-17 13.4.2 Signal Measurement Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-17 13.4.2.1 Measurement Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-18 13.4.2.2 Measurement Input Width (Mode 4) . . . . . . . . . . . . . . . . . . . . . . . . . .13-18 13.4.2.3 Measurement Input Period (Mode 5) . . . . . . . . . . . . . . . . . . . . . . . . . .13-19 13.4.2.4 Measurement Capture (Mode 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-20 13.4.3 Pulse Width Modulation (PWM, Mode 7) . . . . . . . . . . . . . . . . . . . . . . . . .13-21 13.4.4 Watchdog Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-22 13.4.4.1 Watchdog Pulse (Mode 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-22 13.4.4.2 Watchdog Toggle (Mode 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-23 13.4.5 Reserved Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-24 13.4.6 Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-24 13.4.6.1 Timer Behavior during Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-24 13.4.6.2 Timer Behavior during Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-24 13.4.7 DMA Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-24 Section 14 Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1 14.1 Pin-out and Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1 14.1.1 LQFP Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1 14.1.2 LQFP Package Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-7 14.2 Ordering Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-10 Appendix A Bootstrap ROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1 DSP56367 Bootstrap Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
14
MOTOROLA
CONTENTS
Paragraph Number Appendix Appendix Title Page Number
B Equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 C JTAG BSDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
Appendix D Programmer's Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 D.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 D.1.1 Peripheral Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 D.1.2 Interrupt Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 D.1.3 Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 D.1.4 Host Interface Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 D.1.5 Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 D.2 Internal I/O Memory MAp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2 D.3 Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7 D.4 Interrupt Source Priorities (within an IPL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-10 D.5 Host Interface--Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-12 D.6 Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-15 Appendix Appendix E Power Consumption Benchmark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 F IBIS Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-1
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
MOTOROLA
15
CONTENTS
Paragraph Number Title Page Number
16
MOTOROLA
List of Figures
Figure Number 1-1 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 3-35 Title Page Number
DSP56367 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2 Signals Identified by Functional Group . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3 External Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7 Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11 External Fast Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12 External Interrupt Timing (Negative Edge-Triggered). . . . . . . . . . . . . . . .3-13 Operating Mode Select Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13 Recovery from Stop State Using IRQA Interrupt Service . . . . . . . . . . . . .3-13 Recovery from Stop State Using IRQA Interrupt Service . . . . . . . . . . . . .3-14 External Memory Access (DMA Source) Timing . . . . . . . . . . . . . . . . . . .3-14 SRAM Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17 SRAM Write Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18 DRAM Page Mode Wait States Selection Guide . . . . . . . . . . . . . . . . . . . .3-19 DRAM Page Mode Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23 DRAM Page Mode Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-24 DRAM Out-of-Page Wait States Selection Guide . . . . . . . . . . . . . . . . . . .3-25 DRAM Out-of-Page Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-32 DRAM Out-of-Page Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-33 DRAM Refresh Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-34 Asynchronous Bus Arbitration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . .3-35 Asynchronous Bus Arbitration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . .3-36 Host Interrupt Vector Register (IVR) Read Timing Diagram . . . . . . . . . .3-39 Read Timing Diagram, Non-Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . .3-40 Write Timing Diagram, Non-Multiplexed Bus. . . . . . . . . . . . . . . . . . . . . .3-41 Read Timing Diagram, Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . .3-42 Write Timing Diagram, Multiplexed Bus. . . . . . . . . . . . . . . . . . . . . . . . . .3-43 Host DMA Write Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-44 Host DMA Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-44 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-48 SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-49 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-50 SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-51 I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-54 ESAI Transmitter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-58 ESAI Receiver Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-59 ESAI HCKT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-60 ESAI HCKR Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-60
MOTOROLA
17
List of Figures
Figure Number 3-36 3-37 3-38 3-39 3-40 3-41 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 6-1 6-2 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 Page Number Digital Audio Transmitter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-61 TIO Timer Event Input Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-62 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-64 Test Clock Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-64 Boundary Scan (JTAG) Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . .3-65 Test Access Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-65 Memory Maps for MSW=(X,X), CE=0, MS=0, SC=0 . . . . . . . . . . . . . . . .5-4 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=0 . . . . . . . . . . . . . . . .5-4 Memory Maps for MSW=(0,0), CE=0 MS=1, SC=0 . . . . . . . . . . . . . . . . . .5-5 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=0 . . . . . . . . . . . . . . . . .5-5 Memory Maps for MSW=(1,0), CE=0, MS=1, SC=0 . . . . . . . . . . . . . . . . .5-6 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=0 . . . . . . . . . . . . . . . . .5-6 Memory Maps for MSW=(0,1), CE=1, MS=1, SC=0 . . . . . . . . . . . . . . . . .5-7 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=0 . . . . . . . . . . . . . . . . .5-7 Memory Maps for MSW=(X,X), CE=0, MS=0, SC=1 . . . . . . . . . . . . . . . .5-8 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=1 . . . . . . . . . . . . . . . .5-8 Memory Maps for MSW=(0,0), CE=0, MS=1, SC=1 . . . . . . . . . . . . . . . . .5-9 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=1 . . . . . . . . . . . . . . . . .5-9 Memory Maps for MSW=(1,0), CE=0, MS=1, SC=1 . . . . . . . . . . . . . . . .5-10 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=1 . . . . . . . . . . . . . . . .5-10 Memory Maps for MSW=(0,1), CE=1, MS=1, SC=1 . . . . . . . . . . . . . . . .5-11 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=1 . . . . . . . . . . . . . . . .5-11 Interrupt Priority Register P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8 Interrupt Priority Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8 HDI08 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5 Host Control Register (HCR) (X:$FFFFC2) . . . . . . . . . . . . . . . . . . . . . . . .8-7 Host Status Register (HSR) (X:FFFFC3) . . . . . . . . . . . . . . . . . . . . . . . . . .8-10 Host Base Address Register (HBAR) (X:$FFFFC5) . . . . . . . . . . . . . . . . .8-12 Self Chip Select logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-12 Host Port Control Register (HPCR) (X:$FFFFC4) . . . . . . . . . . . . . . . . . .8-13 Single strobe bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-15 Dual strobes bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-15 Host Data Direction Register (HDDR) (X:$FFFFC8) . . . . . . . . . . . . . . . .8-16 Host Data Register (HDR) (X:$FFFFC9). . . . . . . . . . . . . . . . . . . . . . . . . .8-17 HSR-HCR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-19 Interface Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-21 Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-25 Interface Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-26 Title
18
MOTOROLA
List of Figures
Figure Number 8-15 8-16 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 11-1 11-2 11-3 Title Page Number
Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-27 HDI08 Host Request Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-31 Serial Host Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3 SHI Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4 SHI Programming Model--Host Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5 SHI Programming Model--DSP Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6 SHI I/O Shift Register (IOSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8 SPI Data-To-Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10 I2C Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-19 I2C Start and Stop Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-20 Acknowledgment on the I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-20 I2C Bus Protocol For Host Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . .9-21 I2C Bus Protocol For Host Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . .9-22 ESAI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2 TCCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-10 ESAI Clock Generator Functional Block Diagram . . . . . . . . . . . . . . . . .10-11 ESAI Frame Sync Generator Functional Block Diagram. . . . . . . . . . . . .10-13 TCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-15 Normal and Network Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-20 Frame Length Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-23 RCCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-26 RCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-30 SAICR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-35 SAICR SYN Bit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-37 SAISR Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-38 ESAI Data Path Programming Model ([R/T]SHFD=0) . . . . . . . . . . . . . .10-42 ESAI Data Path Programming Model ([R/T]SHFD=1) . . . . . . . . . . . . . .10-43 TSMA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-45 TSMB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-45 RSMA Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-47 RSMB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-47 PCRC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-54 PRRC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-54 PDRC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-55 ESAI_1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2 EMUXR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-6 TCCR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-7
MOTOROLA
19
List of Figures
Figure Number 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 13-1 13-2 13-3 13-4 13-5 14-1 14-2 14-3 14-4 D-1 D-2 D-3 D-4 D-5 D-6 Page Number ESAI_1 Clock Generator Functional Block Diagram . . . . . . . . . . . . . . . .11-8 ESAI_1 Frame Sync Generator Functional Block Diagram. . . . . . . . . . . .11-9 TCR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-10 RCCR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-10 RCR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-11 SAICR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12 SAISR_1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12 TSMA_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-14 TSMB_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-14 RSMA_1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-15 RSMB_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-15 PCRE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-17 PRRE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-17 PDRE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-18 Digital Audio Transmitter (DAX) Block Diagram. . . . . . . . . . . . . . . . . . .12-2 DAX Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5 DAX Relative Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-10 Preamble sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-11 Clock Multiplexer Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-12 Examples of data organization in memory . . . . . . . . . . . . . . . . . . . . . . . .12-15 Port D Control Register (PCRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-16 Port D Direction Register (PRRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-16 Port D Data Register (PDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-18 Timer/Event Counter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-2 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3 Timer Module Programmer's Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-4 Timer Prescaler Load Register (TPLR) . . . . . . . . . . . . . . . . . . . . . . . . . . .13-5 Timer Prescaler Count Register (TPCR) . . . . . . . . . . . . . . . . . . . . . . . . . .13-6 144-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-2 DSP56367 144-pin LQFP Package (1 of 3) . . . . . . . . . . . . . . . . . . . . . . . .14-7 DSP56367 144-pin LQFP Package (2 of 3) . . . . . . . . . . . . . . . . . . . . . . . .14-8 DSP56367 144-pin LQFP Package (3 of 3) . . . . . . . . . . . . . . . . . . . . . . . .14-9 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-16 Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-17 Interrupt Priority Register-Core (IPR-C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-18 Interrupt Priority Register - Peripherals (IPR-P). . . . . . . . . . . . . . . . . . . . . . . . . D-19 Phase Lock Loop Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-20 Host Receive and Host Transmit Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . D-21 Title
20
MOTOROLA
List of Figures
Figure Number D-7 D-8 D-9 D-10 D-11 D-12 D-13 D-14 D-15 D-16 D-17 D-18 D-19 D-20 D-21 D-22 D-23 D-24 D-25 D-26 D-27 D-28 D-29 D-30 D-31 D-32 D-33 D-34 D-35 D-36 Title Page Number D-22 D-23 D-24 D-25 D-26 D-27 D-28 D-29 D-30 D-31 D-32 D-33 D-34 D-35 D-36 D-37 D-38 D-39 D-40 D-41 D-42 D-43 D-44 D-45 D-46 D-47 D-48 D-49 D-50 D-51
Host Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Base Address and Host Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Interrupt Control and Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Interrupt Vector and Command Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Receive and Transmit Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SHI Slave Address and Clock Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . SHI Transmit and Receive Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SHI Host Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI Transmit Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI Transmit Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI Receive Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI Receive Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI Common Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI_1 Multiplex Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI_1 Transmit Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI_1 Transmit Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI_1 Receive Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI_1 Receive Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI_1 Common Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESAI_1 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAX Non-Audio Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAX Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Prescaler Load and Prescaler Count Registers (TPLR, TPCR) . . . . . . . . . Timer Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Load, Compare and Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOTOROLA
21
List of Figures
Figure Number Title Page Number
22
MOTOROLA
List of Tables
Table Number 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 5-1 5-2 5-3 5-4 6-1 Title Page Number
DSP56367 Functional Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4 Grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4 Clock and PLL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 External Address Bus Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 External Data Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 External Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6 Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 Serial Host Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13 Enhanced Serial Audio Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . .2-15 Enhanced Serial Audio Interface_1 Signals . . . . . . . . . . . . . . . . . . . . . . .2-19 Digital Audio Interface (DAX) Signals . . . . . . . . . . . . . . . . . . . . . . . . . .2-20 Timer Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-21 JTAG/OnCE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-21 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 DC Electrical Characteristics5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6 Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7 PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8 Reset, Stop, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . . . . . . .3-8 SRAM Read and Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15 DRAM Page Mode Timings, Three Wait States . . . . . . . . . . . . . . . . . . .3-20 DRAM Page Mode Timings, Four Wait States1, 2, 3 . . . . . . . . . . . . . . . . . .3-21 DRAM Out-of-Page and Refresh Timings, Four Wait States . . . . . . . . .3-25 DRAM Out-of-Page and Refresh Timings, Eleven Wait States. . . . . . . .3-28 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 . . . . . .3-29 Asynchronous Bus Arbitration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .3-35 Host Interface (HDI08) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-36 Serial Host Interface SPI Protocol Timing . . . . . . . . . . . . . . . . . . . . . . . .3-45 SHI I2C Protocol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-51 SCL Serial Clock Cycle (TSCL) Generated as Master . . . . . . . . . . . . . . .3-53 Enhanced Serial Audio Interface Timing . . . . . . . . . . . . . . . . . . . . . . . .3-55 Digital Audio Transmitter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-61 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-62 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-63 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-64 Internal Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2 On-chip RAM Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2 On-chip ROM Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3 Internal I/O Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14 Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
MOTOROLA
23
List of Tables
Table Number 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 9-1 9-2 9-3 9-4 9-5 9-6 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 11-1 Title Page Number
DSP56367 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-5 DSP56367 Mode Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-6 Interrupt Priority Level Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7 Interrupt Sources Priorities Within an IPL . . . . . . . . . . . . . . . . . . . . . . . . .6-9 DSP56367 Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-10 DMA Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13 Identification Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-15 JTAG Identification Register Configuration . . . . . . . . . . . . . . . . . . . . . .6-15 DSP56367 BSR Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-15 HDI08 Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 Strobe Signals Support signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 Host request support signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 HDI08 IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8 HDM[2:0] Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-9 HDR and HDDR Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-17 DSP-Side Registers after Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-18 HDI08 Host Side Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-20 TREQ RREQ Interrupt Mode (HDM[2:0]=000 or HM[1:0]=00) . . . . . .8-22 TREQ RREQ DMA Mode (HM11/40 or HM01/40) . . . . . . . . . . . . . . . . . .8-22 HDRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22 Host Mode Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-23 INIT Command Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-24 Host Request Status (HREQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-27 Host Side Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-29 SHI Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7 SHI Internal Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7 SHI Noise Reduction Filter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-12 SHI Data Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-13 HREQ Function In SHI Slave Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . .9-15 HCSR Receive Interrupt Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-16 Receiver Clock Sources (asynchronous mode only) . . . . . . . . . . . . . . . .10-6 Transmitter Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-7 Transmitter High Frequency Clock Divider . . . . . . . . . . . . . . . . . . . . . .10-14 Transmit Network Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-19 ESAI Transmit Slot and Word Length Selection . . . . . . . . . . . . . . . . . .10-21 Receiver High Frequency Clock Divider . . . . . . . . . . . . . . . . . . . . . . . .10-27 SCKR Pin Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-28 FSR Pin Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-29 HCKR Pin Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-29 ESAI Receive Network Mode Selection . . . . . . . . . . . . . . . . . . . . . . . .10-32 ESAI Receive Slot and Word Length Selection . . . . . . . . . . . . . . . . . . .10-32 PCRC and PRRC Bits Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . .10-54 EMUXR ESAI/ESAI_1 Pin Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .11-6
24
MOTOROLA
List of Tables
Table Number 11-2 11-3 11-4 12-1 12-2 12-3 12-4 12-5 12-6 13-1 13-2 13-3 13-4 14-1 14-2 D-1 D-2 D-3 D-4 D-20 Title Page Number
Transmitter Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-7 Receiver Clock Sources (asynchronous mode only) . . . . . . . . . . . . . . .11-11 PCRE and PRRE Bits Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . .11-17 DAX Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-4 DAX Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-4 Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-8 Preamble Bit Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-11 Examples of DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-14 DAX Port GPIO Control Register Functionality . . . . . . . . . . . . . . . . . .12-17 Prescaler Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-6 Timer Control Bits for Timer 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8 Timer Control Bits for Timers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .13-9 Inverse Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-9 Signal Identification by Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-3 Signal Identification by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . .14-5 Internal I/O Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2 DSP56367 Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7 Interrupt Sources Priorities Within an IPL . . . . . . . . . . . . . . . . . . . . . . . D-10 HDI08 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-12 EMUXR ESAI/ESAI_1 Pin Selection . . . . . . . . . . . . . . . . . . . . . . . . . . D-36
MOTOROLA
25
List of Tables
Table Number Title Page Number
26
MOTOROLA
Preface
This manual describes the DSP56367 24-bit digital signal processor (DSP), its memory, operating modes, and peripheral modules. The DSP56367 is a member of the DSP56300 family of programmable CMOS DSPs. Changes in core functionality specific to the DSP56367 are also described in this manual. Note: This document contains information on a new product. Specifications and information herein are subject to change without notice.
The DSP56367 is targeted to applications that require digital audio compression and decompression, sound field processing, acoustic equalization, and other digital audio algorithms. This manual is intended to be used with the following publication: * The DSP56300 Family Manual (DSP56300FM/AD), which describes the CPU, core programming models, and instruction set details.
This document, as well as Motorola's DSP development tools, can be obtained through a local Motorola Semiconductor Sales Office or authorized distributor. To receive the latest information on this DSP, access the Motorola DSP home page at the address given on the front cover of this document. This manual contains the following sections and appendices.
SECTION 1--DSP56367 OVERVIEW
-
Provides a brief description of the DSP56367, including a features list and block diagram. Lists related documentation needed to use this chip and describes the organization of this manual. Describes the signals on the DSP56367 pins and how these signals are grouped into interfaces. Describes the DSP56367 maximum ratings, AC specifications, DC specifications, thermal specifications, clock operational specifications and timings.
SECTION 2--SIGNAL/CONNECTION DESCRIPTIONS
-
SECTION 3--SPECIFICATIONS
-
MOTOROLA
About This Guide
i
SECTION 4--DESIGN CONSIDERATIONS
-
Describes thermal, electrical, and power consumption issues, as wells PLL performance issues and input jitter requirements for the DSP56367. Describes data and program and memory maps for the DSP56367. Describes the registers used to configure the DSP56300 core when programming the DSP56367, in particular the interrupt vector locations and the operation of the interrupt priority registers. Explains the operating modes and how they affect the processor's program and data memories. Describes the DSP56367 GPIO capability and the programming model for the GPIO signals (operation, registers, and control). Describes the HDI08 parallel host interface. Describes the serial input/output interface providing a path for communication and program/coefficient data transfers between the DSP and an external host processor. The SHI can also communicate with other serial peripheral devices. Describes one of the full-duplex serial port for serial communication with a variety of serial devices. Describes the second full-duplex serial port for serial communication with a variety of serial devices. Describes the full-duplex serial port for serial communication with a variety of serial devices. Describes the internal timer/event counter in the DSP56367. Describes the available package for the DSP56367, including diagrams of the package pinouts and tables describing how the signals are allocated for the package. Lists the bootstrap code used for the DSP56367.
SECTION 5--MEMORY CONFIGURATION
- -
SECTION 6--CORE CONFIGURATION
SECTION 7--GENERAL PURPOSE INPUT/OUTPUT (GPIO)
-
SECTION 8-- HOST INTERFACE (HDI08)
- -
SECTION 9--SERIAL HOST INTERFACE (SHI)
SECTION 10--ENHANCED SERIAL AUDIO INTERFACE (ESAI)
-
SECTION 11--ENHANCED SERIAL AUDIO INTERFACE 1 (ESAI_1)
-
SECTION 12--DIGITAL AUDIO TRANSMITTER (DAX)
-
SECTION 13--TRIPLE TIMER MODULE (TEC)
- -
SECTION 14--PACKAGE DESCRIPTION
APPENDIX A--BOOTSTRAP PROGRAM
-
APPENDIX B--EQUATES
ii
About This Guide
MOTOROLA
- - -
Lists equates for the DSP56367. Provides the BSDL listing for the DSP56367. Lists peripheral addresses, interrupt addresses, and interrupt priorities for the DSP56367. Contains programming sheets listing the contents of the major DSP56367 registers for programmer reference. Describes the benchmark program that permits evaluation of DSP power usage in a test situation. Describes the IBIS model used for the DSP56367.
APPENDIX C--JTAG/BSDL LISTING
APPENDIX D--PROGRAMMING REFERENCE
APPENDIX E--POWER CONSUMPTION BENCHMARK
-
APPENDIX F--IBIS MODEL
-
Manual Conventions
The following conventions are used in this manual: * * Bits within registers are always listed from most significant bit (MSB) to least significant bit (LSB). When several related bits are discussed, they are referenced as AA[n:m], where n>m. For purposes of description, the bits are presented as if they are contiguous within a register. However, this is not always the case. Refer to the programming model diagrams or to the programmer's sheets to see the exact location of bits within a register. When a bit is described as "set", its value is 1. When a bit is described as "cleared", its value is 0. The word "assert" means that a high true (active high) signal is pulled high to VCC or that a low true (active low) signal is pulled low to ground. The word "deassert" means that a high true signal is pulled low to ground or that a low true signal is pulled high to VCC.
High True/Low True Signal Conventions
* *
Signal/Symbol PIN1 PIN PIN PIN
Logic State True False True False
Signal State Asserted Deasserted Asserted Deasserted
Voltage Ground2 VCC3 VCC Ground
MOTOROLA
About This Guide
iii
High True/Low True Signal Conventions
Signal/Symbol
Note: 1. 2. 3.
Logic State
Signal State
Voltage
PIN is a generic term for any pin on the chip. Ground is an acceptable low voltage level. See the appropriate data sheet for the range of acceptable low voltage levels (typically a TTL logic low). VCC is an acceptable high voltage level. See the appropriate data sheet for the range of acceptable high voltage levels (typically a TTL logic high).
*
Pins or signals that are asserted low (made active when pulled to ground) - - In text, have an overbar (e.g., RESET is asserted low). In code examples, have a tilde in front of their names. In example below, line 3 refers to the SS0 pin (shown as ~SS0).
* *
Sets of pins or signals are indicated by the first and last pins or signals in the set (e.g., HA1-HA8). Code examples are displayed in a monospaced font, as shown below:
Example Sample Code Listing
BFSET
#$0007,X:PCC; Configure: ; MISO0, MOSI0, SCK0 for SPI master
line 1 line 2 line 3
; ~SS0 as PC3 for GPIO
* *
Hex values are indicated with a dollar sign ($) preceding the hex value, as follows: $FFFFFF is the X memory address for the core interrupt priority register (IPR-C). The word "reset" is used in four different contexts in this manual: - - - - the reset signal, written as "RESET," the reset instruction, written as "RESET," the reset operating state, written as "Reset," and the reset function, written as "reset."
iv
About This Guide
MOTOROLA
SECTION
1
DSP56367 OVERVIEW
1.1 INTRODUCTION
This manual describes the DSP56367 24-bit digital signal processor (DSP), its memory, operating modes, and peripheral modules. The DSP56367 is a member of the DSP56300 family of programmable CMOS DSPs. The DSP56367 is targeted to applications that require digital audio compression/decompression, sound field processing, acoustic equalization and other digital audio algorithms. The DSP56367 offers 150 million instructions per second (MIPS) using an internal 150 MHz clock at 1.8 V and 100 million instructions per second (MIPS) using an internal 100 MHz clock at 1.5 V. Changes in core functionality specific to the DSP56367 are also described in this manual. See Figure 1-1 for the block diagram of the DSP56367.
MOTOROLA
DSP56367
1-1
1
2
16
8
4 6
5
MEMORY EXPANSION AREA
TRIPLE TIMER DAX (SPDIF Tx.) INTER-FA CE HOST INTERFACE ESAI INTERFACE ESAI_1 SHI INTERFACE PROGRAM RAM /INSTR. CACHE 3K x 24 PROGRAM ROM 40K x 24 Bootstrap X MEMORY RAM 13K X 24 ROM 32K x 24 Y MEMORY RAM 7K X 24 ROM 8K x 24
PIO_EB
PM_EB
PERIPHERAL EXPANSION AREA
ADDRESS GENERATION UNIT SIX CHANNELS DMA UNIT
YAB XAB PAB DAB
XM_EB
YM_EB
EXTERNAL ADDRESS BUS SWITCH DRAM & SRAM BUS INTERFACE & I - CACHE EXTERNAL DATA BUS SWITCH
18 ADDRESS
24-BIT DSP56300 Core
10 CONTROL
DDB YDB
INTERNAL DATA BUS
XDB PDB GDB
24 DATA
POWER MNGMNT PLL CLOCK GENERAT
PROGRAM INTERRUPT CONTROLLER PROGRAM DECODE CONTROLLE PROGRAM ADDRESS GENERATOR DATA ALU 24X24+56->56-BIT MAC TWO 56-BIT ACCUMULATORS BARREL SHIFTER JTAG OnCETM
4
EXTAL RESET PINIT/NMI
MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD
24 BITS BUS
Figure 1-1 DSP56367 Block Diagram
1.2
DSP56300 CORE DESCRIPTION
The DSP56367 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides up to twice the performance of Motorola's popular DSP56000 core family while retaining code compatibility with it. The DSP56300 core family offers a new level of performance in speed and power, provided by its rich instruction set and low power dissipation, thus enabling a new generation of wireless, telecommunications, and multimedia products. For a description of the DSP56300
MOTOROLA
DSP56367
1-2
DSP56367 Overview DSP56300 Core Description
core, see Section 1 DSP56300 Core Functional Blocks on page 1-5. Significant architectural enhancements to the DSP56300 core family include a barrel shifter, 24-bit addressing, an instruction cache, and direct memory access (DMA). The DSP56300 core family members contain the DSP56300 core and additional modules. The modules are chosen from a library of standard predesigned elements such as memories and peripherals. New modules may be added to the library to meet customer specifications. A standard interface between the DSP56300 core and the on-chip memory and peripherals supports a wide variety of memory and peripheral configurations. Refer to Section 5 Memory Configuration. Core features are described fully in the DSP56300 Family Manual. Pinout, memory, and peripheral features are described in this manual. * DSP56300 modular chassis - 150 Million Instructions Per Second (MIPS) with a 150 MHz clock at internal logic supply (QVCCL) of 1.8V. - - - - - -
100 Million Instructions Per Second (MIPS) with a 100 MHz clock at internal logic supply (QVCCL) of 1.5V.
Object Code Compatible with the 56K core. Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support. Program Control with position independent code support and instruction cache support. Six-channel DMA controller. PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors (1 to 16) and power saving clock divider (2i: i=0 to 7). Reduces clock noise.
- Internal address tracing support and OnCE for Hardware/Software debugging. - JTAG port. - Very low-power CMOS design, fully static design with operating frequencies down to DC. - * STOP and WAIT low-power standby modes.
On-chip Memory Configuration - 7Kx24 Bit Y-Data RAM and 8Kx24 Bit Y-Data ROM.
- 13Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM.
MOTOROLA
DSP56367
1-3
DSP56367 Overview DSP56367 Audio Processor Architecture
- - - *
40Kx24 Bit Program ROM. 3Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM. 1K of Program RAM may be used as Instruction Cache or for Program ROM patching. 2Kx24 Bit from Y Data RAM and 5Kx24 Bit from X Data RAM can be switched to Program RAM resulting in up to 10Kx24 Bit of Program RAM.
Off-chip memory expansion - - - - External Memory Expansion Port. Off-chip expansion up to two 16M x 24-bit word of Data memory. Off-chip expansion up to 16M x 24-bit word of Program memory. Simultaneous glueless interface to SRAM and DRAM.
*
Peripheral modules - - Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony, AC97, network and other programmable protocols. Serial Audio Interface I(ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony, AC97, network and other programmable protocols The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT support HCKR and HCKT (high frequency clocks) Serial Host Interface (SHI): SPI and I2C protocols, multi master capability, 10-word receive FIFO, support for 8, 16 and 24-bit words. Byte-wide parallel Host Interface (HDI08) with DMA support. Triple Timer module (TEC). Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF, IEC958, CP-340 and AES/EBU digital audio formats. Pins of unused peripherals (except SHI) may be programmed as GPIO lines.
- - - - - *
144-pin plastic LQFP package.
1.3
DSP56367 AUDIO PROCESSOR ARCHITECTURE
This section defines the DSP56367 audio processor architecture. The audio processor is composed of the following units: * The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program Controller, Instruction-Cache Controller, DMA Controller, PLL-based clock oscillator, Memory Module Interface, Peripheral Module Interface and the On-Chip
1-4
DSP56367
MOTOROLA
DSP56367 Overview DSP56300 Core Functional Blocks
Emulator (OnCE). The DSP56300 core is described in the document DSP56300 24-Bit Digital Signal Processor Family Manual, Motorola publication DSP56300FM/AD. * * Memory modules. Peripheral modules. The peripheral modules are defined in the following sections.
Memory sizes in the block diagram are defaults. Memory may be differently partitioned, according to the memory mode of the chip. See Section 1 On-Chip Memory on page 1-10 for more details about memory size.
1.4
DSP56300 CORE FUNCTIONAL BLOCKS
The DSP56300 core provides the following functional blocks: * * * * * * * * * * Data arithmetic logic unit (Data ALU) Address generation unit (AGU) Program control unit (PCU) Bus interface unit (BIU) DMA controller (with six channels) Instruction cache controller PLL-based clock oscillator OnCE module JTAG TAP Memory
In addition, the DSP56367 provides a set of on-chip peripherals, described in Section 1 Peripheral Overview on page 1-11.
1.4.1
DATA ALU
The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core. The components of the Data ALU are as follows: * * Fully pipelined 24-bit x 24-bit parallel multiplier-accumulator (MAC) Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing)
MOTOROLA
DSP56367
1-5
DSP56367 Overview DSP56300 Core Functional Blocks
* * * * *
Conditional ALU instructions 24-bit or 16-bit arithmetic support under software control Four 24-bit input general purpose registers: X1, X0, Y1, and Y0 Six Data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two general purpose, 56-bit accumulators (A and B), accumulator shifters Two data bus shifter/limiter circuits
1.4.1.1 Data ALU Registers The Data ALU registers can be read or written over the X memory data bus (XDB) and the Y memory data bus (YDB) as 24- or 48-bit operands (or as 16- or 32-bit operands in 16-bit arithmetic mode). The source operands for the Data ALU, which can be 24, 48, or 56 bits (16, 32, or 40 bits in 16-bit arithmetic mode), always originate from Data ALU registers. The results of all Data ALU operations are stored in an accumulator. All the Data ALU operations are performed in two clock cycles in pipeline fashion so that a new instruction can be initiated in every clock, yielding an effective execution rate of one instruction per clock cycle. The destination of every arithmetic operation can be used as a source operand for the immediately following arithmetic operation without a time penalty (i.e., without a pipeline stall). 1.4.1.2 Multiplier-Accumulator (MAC) The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and performs all of the calculations on data operands. In the case of arithmetic instructions, the unit accepts as many as three input operands and outputs one 56-bit result of the following form- Extension:Most Significant Product:Least Significant Product (EXT:MSP:LSP). The multiplier executes 24-bit x 24-bit, parallel, fractional multiplies, between two's-complement signed, unsigned, or mixed operands. The 48-bit product is right-justified and added to the 56-bit contents of either the A or B accumulator. A 56-bit result can be stored as a 24-bit operand. The LSP can either be truncated or rounded into the MSP. Rounding is performed if specified.
1.4.2
ADDRESS GENERATION UNIT (AGU)
The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers used to generate the addresses. It implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and reverse-carry. The AGU operates in parallel with other chip resources to minimize address-generation overhead.
1-6
DSP56367
MOTOROLA
DSP56367 Overview DSP56300 Core Functional Blocks
The AGU is divided into two halves, each with its own Address ALU. Each Address ALU has four sets of register triplets, and each register triplet is composed of an address register, an offset register, and a modifier register. The two Address ALUs are identical. Each contains a 24-bit full adder (called an offset adder). A second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register. A third full adder (called a reverse-carry adder) is also provided. The offset adder and the reverse-carry adder are in parallel and share common inputs. The only difference between them is that the carry propagates in opposite directions. Test logic determines which of the three summed results of the full adders is output. Each Address ALU can update one address register from its respective address register file during one instruction cycle. The contents of the associated modifier register specifies the type of arithmetic to be used in the address register update calculation. The modifier value is decoded in the Address ALU.
1.4.3
PROGRAM CONTROL UNIT (PCU)
The PCU performs instruction prefetch, instruction decoding, hardware DO loop control, and exception processing. The PCU implements a seven-stage pipeline and controls the different processing states of the DSP56300 core. The PCU consists of the following three hardware blocks: * * * Program decode controller (PDC) Program address generator (PAG) Program interrupt controller (PIC)
The PDC decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control. The PAG contains all the hardware needed for program address generation, system stack, and loop control. The PIC arbitrates among all interrupt requests (internal interrupts, as well as the five external requests: IRQA, IRQB, IRQC, IRQD, and NMI), and generates the appropriate interrupt vector address. PCU features include the following: * * * Position independent code support Addressing modes optimized for DSP applications (including immediate offsets) On-chip instruction cache controller
MOTOROLA
DSP56367
1-7
DSP56367 Overview DSP56300 Core Functional Blocks
* * *
On-chip memory-expandable hardware stack Nested hardware DO loops Fast auto-return interrupts
The PCU implements its functions using the following registers: * * * * * * * * * PC--program counter register SR--Status register LA--loop address register LC--loop counter register VBA--vector base address register SZ--stack size register SP--stack pointer OMR--operating mode register SC--stack counter register
The PCU also includes a hardware system stack (SS).
1.4.4
INTERNAL BUSES
To provide data exchange between blocks, the following buses are implemented: * * * * * * * * * * Peripheral input/output expansion bus (PIO_EB) to peripherals Program memory expansion bus (PM_EB) to program memory X memory expansion bus (XM_EB) to X memory Y memory expansion bus (YM_EB) to Y memory Global data bus (GDB) between registers in the DMA, AGU, OnCE, PLL, BIU, and PCU as well as the memory-mapped registers in the peripherals DMA data bus (DDB) for carrying DMA data between memories and/or peripherals DMA address bus (DAB) for carrying DMA addresses to memories and peripherals Program Data Bus (PDB) for carrying program data throughout the core X memory Data Bus (XDB) for carrying X data throughout the core Y memory Data Bus (YDB) for carrying Y data throughout the core
1-8
DSP56367
MOTOROLA
DSP56367 Overview DSP56300 Core Functional Blocks
* * *
Program address bus (PAB) for carrying program memory addresses throughout the core X memory address bus (XAB) for carrying X memory addresses throughout the core Y memory address bus (YAB) for carrying Y memory addresses throughout the core
All internal buses on the DSP56300 family members are 24-bit buses. See Figure 1-1.
1.4.5
DIRECT MEMORY ACCESS (DMA)
The DMA block has the following features: * * * * Six DMA channels supporting internal and external accesses One-, two-, and three-dimensional transfers (including circular buffering) End-of-block-transfer interrupts Triggering from interrupt lines and all peripherals
1.4.6
PLL-BASED CLOCK OSCILLATOR
The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which performs clock input division, frequency multiplication, and skew elimination; and the clock generator (CLKGEN), which performs low-power division and clock pulse generation. PLL-based clocking: * * * Allows change of low-power divide factor (DF) without loss of lock Provides output clock with skew elimination Provides a wide range of frequency multiplications (1 to 4096), predivider factors (1 to 16), and a power-saving clock divider (2i: i = 0 to 7) to reduce clock noise
The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock input. This feature offers two immediate benefits: * * A lower frequency clock input reduces the overall electromagnetic interference generated by a system. The ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system.
MOTOROLA
DSP56367
1-9
DSP56367 Overview DSP56300 Core Functional Blocks
1.4.7
JTAG TAP AND ONCE MODULE
The DSP56300 core provides a dedicated user-accessible TAP fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density circuit boards led to developing this standard under the sponsorship of the Test Technology Committee of IEEE and JTAG. The DSP56300 core implementation supports circuit-board test strategies based on this standard. The test logic includes a TAP consisting of four dedicated signals, a 16-state controller, and three test data registers. A boundary scan register links all device signals into a single shift register. The test logic, implemented utilizing static logic design, is independent of the device system logic. More information on the JTAG port is provided in DSP56300 Family Manual, JTAG Port. The OnCE module provides a nonintrusive means of interacting with the DSP56300 core and its peripherals so a user can examine registers, memory, or on-chip peripherals. This facilitates hardware and software development on the DSP56300 core processor. OnCE module functions are provided through the JTAG TAP signals. More information on the OnCE module is provided in DSP56300 Family Manual, On-Chip Emulation Module.
1.4.8
ON-CHIP MEMORY
The memory space of the DSP56300 core is partitioned into program memory space, X data memory space, and Y data memory space. The data memory space is divided into X and Y data memory in order to work with the two Address ALUs and to feed two operands simultaneously to the Data ALU. Memory space includes internal RAM and ROM and can be expanded off-chip under software control. There is an instruction cache, made using program RAM. The patch mode (which uses instruction cache space) is used to patch program ROM. The memory switch mode is used to increase the size of program RAM as needed (switch from X data RAM and/or Y data RAM). There are on-chip ROMs for program memory (40K x 24-bit), bootstrap memory (192 words x 24-bit), X ROM (32K x 24-bit), and Y ROM(8K x 24-bit). More information on the internal memory is provided in Section 5 Internal I/O Memory Map on page 5-14.
1-10
DSP56367
MOTOROLA
DSP56367 Overview Peripheral Overview
1.4.9
OFF-CHIP MEMORY EXPANSION
Memory can be expanded off-chip as follows: * * Data memory can be expanded to two 16 M x 24-bit word memory spaces in 24-bit address mode (64K in 16-bit address mode). Program memory can be expanded to one 16 M x 24-bit word memory space in 24-bit address mode (64K in 16-bit address mode).
Other features of external memory expansion include the following: * * * * External memory expansion port Chip-select logic glueless interface to static random access memory (SRAM) On-chip dynamic RAM (DRAM) controller for glueless interface to DRAM Eighteen external address lines
1.5
PERIPHERAL OVERVIEW
The DSP56367 is designed to perform a wide variety of fixed-point digital signal processing functions. In addition to the core features previously discussed, the DSP56367 provides the following peripherals: * * * * * * 8-bit parallel host interface (HDI08, with DMA support) to external hosts As many as 37 user-configurable general purpose input/output (GPIO) signals Timer/event counter (TEC) module, containing three independent timers Memory switch mode in on-chip memory Four external interrupt/mode control lines and one external non-maskable interrupt line Enhanced serial audio interface (ESAI) with up to four receivers and up to six transmitters, master or slave, using the I2S, Sony, AC97, network, and other programmable protocols A second enhanced serial audio interface (ESAI_1) with 6 dedicated pins. Serial host interface (SHI) using SPI and I2C protocols, with multi-master capability, 10-word receive FIFO, and support for 8-, 16-, and 24-bit words Digital audio transmitter (DAX): a serial transmitter capable of supporting the SPDIF, IEC958, CP-340, and AES/EBU digital audio formats
* * *
MOTOROLA
DSP56367
1-11
DSP56367 Overview Peripheral Overview
1.5.1
HOST INTERFACE (HDI08)
The host interface (HDI08) is a byte-wide, full-duplex, double-buffered, parallel port that can be connected directly to the data bus of a host processor. The HDI08 supports a variety of buses and provides glueless connection with a number of industry-standard DSPs, microcomputers, microprocessors, and DMA hardware. The DSP core treats the HDI08 as a memory-mapped peripheral, using either standard polled or interrupt programming techniques. Separate transmit and receive data registers are double-buffered to allow the DSP and host processor to efficiently transfer data at high speed. Memory mapping allows DSP core communication with the HDI08 registers to be accomplished using standard instructions and addressing modes. Since the host bus may operate asynchronously with the DSP core clock, the HDI08 registers are divided into 2 banks. The "host side" bank is accessible to the external host, and the "DSP side" bank is accessible to the DSP core. The HDI08 supports the following three classes of interfaces: * * * Host processor/MCU connection DMA controller GPIO port
Host port pins not in use may be configured as GPIO pins. The host interface provides up to 16 GPIO pins. These pins can be programmed to function as either GPIO or host interface. For more information on the HDI08, see Section 8 - Host Interface (HDI08).
1.5.2
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
The GPIO port consists of as many as 37 programmable signals, all of which are also used by the peripherals (HDI08, ESAI, ESAI_1, DAX, and TEC). There are no dedicated GPIO signals. The signals are configured as GPIO after hardware reset. Register programming techniques for all GPIO functionality among these interfaces are very similar.
1-12
DSP56367
MOTOROLA
DSP56367 Overview Peripheral Overview
1.5.3
TRIPLE TIMER (TEC)
This section describes a peripheral module composed of a common 21-bit prescaler and three independent and identical general purpose 24-bit timer/event counters, each one having its own register set. Each timer can use internal or external clocking and can interrupt the DSP after a specified number of events (clocks). Timer 0 can signal an external device after counting internal events. Each timer can also be used to trigger DMA transfers after a specified number of events (clocks) occurred. One timer (Timer 0) connects to the external world through one bidirectional pin TIO0. When TIO0 is configured as input, the timer functions as an external event counter or can measure external pulse width/signal period. When TIO0 is used as output the timer is functioning as either a timer, a watchdog or a Pulse Width Modulator. When the TIO0 pin is not used by the timer it can be used as a General Purpose Input/Output Pin. Refer to Section 13 - Timer/ Event Counter.
1.5.4
ENHANCED SERIAL AUDIO INTERFACE (ESAI)
The ESAI provides a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the Motorola SPI serial protocol. The ESAI consists of independent transmitter and receiver sections, each with its own clock generator. It is a superset of the DSP56300 family ESSI peripheral and of the DSP56000 family SAI peripheral. For more information on the ESAI, refer to Section 10 Enhanced Serial Audio Interface (ESAI) on page 10-1.
1.5.5
ENHANCED SERIAL AUDIO INTERFACE 1 (ESAI_1)
The ESAI_1 is a second ESAI interface with just 6 dedicated pins instead of the 12 pins of the full ESAI. Four data pins are shared with the ESAI, while the two high frequency clock pins are not available. Other than the available pins, ESAI_1 is functionally identical to ESAI. For more information on the ESAI_1, refer to Section 11 Enhanced Serial Audio Interface 1 (ESAI_1) on page 11-1.
MOTOROLA
DSP56367
1-13
DSP56367 Overview Peripheral Overview
1.5.6
SERIAL HOST INTERFACE (SHI)
The SHI is a serial input/output interface providing a path for communication and program/coefficient data transfers between the DSP and an external host processor. The SHI can also communicate with other serial peripheral devices. The SHI can interface directly to either of two well-known and widely used synchronous serial buses: the Motorola serial peripheral interface (SPI) bus and the Philips inter-integrated-circuit control (I2C) bus. The SHI supports either the SPI or I2C bus protocol, as required, from a slave or a single-master device. To minimize DSP overhead, the SHI supports single-, double-, and triple-byte data transfers. The SHI has a 10-word receive FIFO that permits receiving up to 30 bytes before generating a receive interrupt, reducing the overhead for data reception. For more information on the SHI, refer to Section 9 Serial Host Interface on page 9-1.
1.5.7
DIGITAL AUDIO TRANSMITTER (DAX)
The DAX is a serial audio interface module that outputs digital audio data in the AES/EBU, CP-340 and IEC958 formats. For more information on the DAX, refer to Section 12 Digital Audio Transmitter on page 12-1.
1-14
DSP56367
MOTOROLA
SECTION
2
SIGNAL/CONNECTION DESCRIPTIONS
2.1 SIGNAL GROUPINGS
The input and output signals of the DSP56367 are organized into functional groups, which are listed in Table 2-1 and illustrated in Figure 2-1. The DSP56367 is operated from a 1.8V supply; however, some of the inputs can tolerate 3.3V. A special notice for this feature is added to the signal descriptions of those inputs. Remember, the DSP56367 offers 150 million instructions per second (MIPS) using an internal 150 MHz clock at 1.8 V and 100 million instructions per second (MIPS) using an internal 100 MHz clock at 1.3.3V. Table 2-1 DSP56367 Functional Signal Groupings
Functional Group Number of Signals 20 18 3 18 Port A1 Data bus Bus control Interrupt and mode control HDI08 SHI ESAI ESAI_1 Digital audio transmitter (DAX) Timer Port C3 Port E5 Port D4 Port B2 24 10 5 16 5 12 6 2 1 Table 2-6 Table 2-7 Table 2-8 Table 2-9 Table 2-10 Table 2-11 Table 2-12 Table 2-13 Table 2-14 Detailed Description Table 2-2 Table 2-3 Table 2-4 Table 2-5
Power (VCC) Ground (GND) Clock and PLL Address bus
MOTOROLA
DSP56367
2-1
Signal/Connection Descriptions Signal Groupings
Table 2-1 DSP56367 Functional Signal Groupings (Continued)
Functional Group Number of Signals 4 Detailed Description Table 2-15
JTAG/OnCE Port
Note:
1. 2. 3. 4. 5.
Port A is the external memory interface port, including the external address bus, data bus, and control signals. Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals. Port C signals are the GPIO port signals which are multiplexed with the ESAI signals. Port D signals are the GPIO port signals which are multiplexed with the DAX signals. Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.
2-2
DSP56367
MOTOROLA
Signal/Connection Descriptions Signal Groupings
PORT A ADDRESS BUS
A0-A17 VCCA (3) GNDA (4)
DSP56367
OnCE ON-CHIP EMULATION/ JTAG PORT TDI
TCK TDO TMS
PORT A DATA BUS
D0-D23 VCCD (4) GNDD (4)
PARALLEL HOST PORT (HDI08) Port B
HAD(7:0) [PB0-PB7] HAS/HA0 [PB8] HA8/HA1 [PB9] HA9/HA2 [PB10] HRW/HRD [PB11] HDS/HWR [PB12] HCS/HA10 [PB13] HOREQ/HTRQ [PB14] HACK/HRRQ [PB15] VCCH GNDH
PORT A BUS CONTROL
AA0-AA2/RAS0-RAS2 CAS RD WR TA BR BG BB VCCC (2) GNDC (2)
SERIAL AUDIO INTERFACE (ESAI)
SCKT[PC3]
Port C
FST [PC4] HCKT [PC5] SCKR [PC0] FSR [PC1] HCKR [PC2] SDO0[PC11] / SDO0_1[PE11] SDO1[PC10] / SDO1_1[PE10] SDO2/SDI3[PC9] / SDO2_1/SDI3_1[PE9] SDO3/SDI2[PC8] / SDO3_1/SDI2_1[PE8] SDO4/SDI1 [PC7] SDO5/SDI0 [PC6]
INTERRUPT AND MODE CONTROL
MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET
PLL AND CLOCK
EXTAL PINIT/NMI PCAP VCCP GNDP
SERIAL AUDIO INTERFACE(ESAI_1)
SCKT_1[PE3]
Port E
FS T_1[PE4] SCKR_1[PE0] FSR_1[PE1] SDO4_1/SDI1_1[PE7] SDO5_1/SDI0_1[PE6] VCCS (2) GNDS (2)
QUIET POWER
VCCQH (3) VCCQL (4) GNDQ (4)
SPDIF TRANSMITTER (DAX)
ADO [PD1] ACI [PD0]
Port D
SERIAL HOST INTERFACE (SHI)
MOSI/HA0 SS/HA2 MISO/SDA SCK/SCL HREQ
TIMER 0
TIO0 [TIO0]
Figure 2-1 Signals Identified by Functional Group
MOTOROLA
DSP56367
2-3
Signal/Connection Descriptions Power
2.2
POWER
Table 2-2 Power Inputs
Power Name VCCP
Description PLL Power--VCCP is VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. There is one VCCP input. Quiet Core (Low) Power--VCCQL is an isolated power for the internal processing logic. This input must be tied externally to all other VCCQL power pins and the VCCP power pin only. Do not tie with other power pins. The user must provide adequate external decoupling capacitors. There are four VCCQL inputs. Quiet External (High) Power--VCCQH is a quiet power source for I/O lines. This input must be tied externally to all other chip power inputs.The user must provide adequate decoupling capacitors. There are three VCCQH inputs. Address Bus Power--VCCA is an isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are three VCCA inputs. Data Bus Power--VCCD is an isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCD inputs. Bus Control Power--VCCC is an isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are two VCCC inputs. Host Power--VCCH is an isolated power for the HDI08 I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There is one VCCH input. SHI, ESAI, ESAI_1, DAX and Timer Power --VCCS is an isolated power for the SHI, ESAI, ESAI_1, DAX and Timer. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are two VCCS inputs.
VCCQL (4)
VCCQH (3)
VCCA (3)
VCCD (4)
VCCC (2)
VCCH
VCCS (2)
2.3
GROUND
Table 2-3 Grounds
Ground Name GNDP
Description PLL Ground--GNDP is a ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 F capacitor located as close as possible to the chip package. There is one GNDP connection. Quiet Ground--GNDQ is an isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDQ connections.
GNDQ (4)
2-4
DSP56367
MOTOROLA
Signal/Connection Descriptions Clock and PLL
Table 2-3 Grounds
Ground Name GNDA (4) Description Address Bus Ground--GNDA is an isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDA connections. Data Bus Ground--GNDD is an isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDD connections. Bus Control Ground--GNDC is an isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GNDC connections. Host Ground--GNDh is an isolated ground for the HD08 I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There is one GNDH connection. SHI, ESAI, ESAI_1, DAX and Timer Ground--GNDS is an isolated ground for the SHI, ESAI, ESAI_1, DAX and Timer. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GNDS connections.
GNDD (4)
GNDC (2)
GNDH
GNDS (2)
2.4
CLOCK AND PLL
Table 2-4 Clock and PLL Signals
Signal Name
Type
State during Reset Input
Signal Description
EXTAL
Input
External Clock Input--An external clock source must be connected to EXTAL in order to supply the clock to the internal clock generator and PLL. PLL Capacitor--PCAP is an input connecting an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP may be tied to VCC, GND, or left floating. PLL Initial/Nonmaskable Interrupt--During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET de assertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized to internal system clock.
PCAP
Input
Input
PINIT/NMI
Input
Input
MOTOROLA
DSP56367
2-5
Signal/Connection Descriptions External Memory Expansion Port (Port A)
2.5
EXTERNAL MEMORY EXPANSION PORT (PORT A)
When the DSP56367 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant port A signals: A0-A17, D0-D23, AA0/RAS0-AA2/RAS2, RD, WR, BB, CAS.
2.5.1
EXTERNAL ADDRESS BUS
Table 2-5 External Address Bus Signals
Signal Name
Type
State during Reset Tri-stated
Signal Description
A0-A17
Output
Address Bus--When the DSP is the bus master, A0-A17 are active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A0-A17 do not change state when external memory spaces are not being accessed.
2.5.2
EXTERNAL DATA BUS
Table 2-6 External Data Bus Signals
Signal Name D0-D23
Type Input/Output
State during Reset Tri-stated
Signal Description Data Bus--When the DSP is the bus master, D0-D23 are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D0-D23 are tri-stated.
2.5.3
EXTERNAL BUS CONTROL
Table 2-7 External Bus Control Signals
Signal Name
Type
State during Reset Tri-stated
Signal Description
AA0-AA2/ RAS0-RAS 2
Output
Address Attribute or Row Address Strobe--When defined as AA, these signals can be used as chip selects or additional address lines. When defined as RAS, these signals can be used as RAS for DRAM interface. These signals are tri-statable outputs with programmable polarity.
2-6
DSP56367
MOTOROLA
Signal/Connection Descriptions External Memory Expansion Port (Port A)
Table 2-7 External Bus Control Signals (Continued)
Signal Name Type State during Reset Tri-stated Signal Description
CAS
Output
Column Address Strobe-- When the DSP is the bus master, CAS is an active-low output used by DRAM to strobe the column address. Otherwise, if the bus mastership enable (BME) bit in the DRAM control register is cleared, the signal is tri-stated. Read Enable--When the DSP is the bus master, RD is an active-low output that is asserted to read external memory on the data bus (D0-D23). Otherwise, RD is tri-stated. Write Enable--When the DSP is the bus master, WR is an active-low output that is asserted to write external memory on the data bus (D0-D23). Otherwise, WR is tri-stated. Transfer Acknowledge--If the DSP is the bus master and there is no external bus activity, or the DSP is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be added to the wait states inserted by the BCR by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to the internal system clock. The number of wait states is determined by the TA input or by the bus control register (BCR), whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles. In order to use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access cannot be extended by TA deassertion, otherwise improper operation may result. TA can operate synchronously or asynchronously, depending on the setting of the TAS bit in the operating mode register (OMR). TA functionality may not be used while performing DRAM type accesses, otherwise improper operation may result. Bus Request--BR is an active-low output, never tri-stated. BR is asserted when the DSP requests bus mastership. BR is deasserted when the DSP no longer needs the bus. BR may be asserted or deasserted independent of whether the DSP56367 is a bus master or a bus slave. Bus "parking" allows BR to be deasserted even though the DSP56367 is the bus master. (See the description of bus "parking" in the BB signal description.) The bus request hold (BRH) bit in the BCR allows BR to be asserted under software control even though the DSP does not need the bus. BR is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. BR is only affected by DSP requests for the external bus, never for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset to the bus slave state. Bus Grant--BG is an active-low input. BG is asserted by an external bus arbitration circuit when the DSP56367 becomes the next bus master. When BG is asserted, the DSP56367 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution. For proper BG operation, the asynchronous bus arbitration enable bit (ABE) in the OMR register must be set.
RD
Output
Tri-stated
WR
Output
Tri-stated
TA
Input
Ignored Input
BR
Output
Output (deasserted)
BG
Input
Ignored Input
MOTOROLA
DSP56367
2-7
Signal/Connection Descriptions Interrupt and Mode Control
Table 2-7 External Bus Control Signals (Continued)
Signal Name Type State during Reset Input Signal Description
BB
Input/ Output
Bus Busy--BB is a bidirectional active-low input/output. BB indicates that the bus is active. Only after BB is deasserted can the pending bus master become the bus master (and then assert the signal again). The bus master may keep BB asserted after ceasing bus activity regardless of whether BR is asserted or deasserted. This is called "bus parking" and allows the current bus master to reuse the bus without rearbitration until another device requires the bus. The deassertion of BB is done by an "active pull-up" method (i.e., BB is driven high and then released and held high by an external pull-up resistor). For proper BB operation, the asynchronous bus arbitration enable bit (ABE) in the OMR register must be set. BB requires an external pull-up resistor.
2.6
INTERRUPT AND MODE CONTROL
The interrupt and mode control signals select the chip's operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. Table 2-8 Interrupt and Mode Control
Signal Name Type State during Reset Input Signal Description
MODA/IRQA
Input
Mode Select A/External Interrupt Request A--MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. If the processor is in the stop standby state and the MODA/IRQA pin is pulled to GND, the processor will exit the stop state. This input is 3.3V tolerant. Mode Select B/External Interrupt Request B--MODB/IRQB is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. This input is 3.3V tolerant.
MODB/IRQB
Input
Input
2-8
DSP56367
MOTOROLA
Signal/Connection Descriptions Parallel Host Interface (HDI08)
Table 2-8 Interrupt and Mode Control (Continued)
Signal Name Type State during Reset Input Signal Description
MODC/IRQC
Input
Mode Select C/External Interrupt Request C--MODC/IRQC is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. This input is 3.3V tolerant. Mode Select D/External Interrupt Request D--MODD/IRQD is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. This input is 3.3V tolerant. Reset--RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET is being asserted. This input is 3.3V tolerant.
MODD/IRQD
Input
Input
RESET
Input
Input
2.7
PARALLEL HOST INTERFACE (HDI08)
The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The HDI08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware.
MOTOROLA
DSP56367
2-9
Signal/Connection Descriptions Parallel Host Interface (HDI08)
Table 2-9 Host Interface
Signal Name Type State during Reset Signal Description
H0-H7
Input/ output
Host Data--When HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, these signals are lines 0-7 of the bidirectional, tri-state data bus. Host Address/Data--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, these signals are lines 0-7 of the address/data bidirectional, multiplexed, tri-state bus. GPIO disconnected Port B 0-7--When the HDI08 is configured as GPIO, these signals are individually programmable as input, output, or internally disconnected. The default state after reset for these signals is GPIO disconnected. These inputs are 3.3V tolerant.
HAD0-HAD7
Input/ output
PB0-PB7
Input, output, or disconnected
HA0
Input
GPIO disconnected
Host Address Input 0--When the HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 0 of the host address input bus. Host Address Strobe--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is the host address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is programmable, but is configured active-low (HAS) following reset. Port B 8--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
HAS/HAS
Input
PB8
Input, output, or disconnected
HA1
Input
GPIO disconnected
Host Address Input 1--When the HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is line 1 of the host address (HA1) input bus. Host Address 8--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 8 of the host address (HA8) input bus.
HA8
Input
PB9
Input, output, or disconnected
Port B 9--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
2-10
DSP56367
MOTOROLA
Signal/Connection Descriptions Parallel Host Interface (HDI08)
Table 2-9 Host Interface (Continued)
Signal Name Type State during Reset GPIO disconnected Signal Description
HA2
Input
Host Address Input 2--When the HDI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line 2 of the host address (HA2) input bus. Host Address 9--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 9 of the host address (HA9) input bus. Port B 10--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
HA9
Input
PB10
Input, Output, or Disconnected
HRW
Input
GPIO disconnected
Host Read/Write--When HDI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the Host Read/Write (HRW) input. Host Read Data--When HDI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the host read data strobe (HRD) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HRD) after reset. Port B 11--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
HRD/ HRD
Input
PB11
Input, Output, or Disconnected
HDS/ HDS
Input
GPIO disconnected
Host Data Strobe--When HDI08 is programmed to interface a single-data-strobe host bus and the HI function is selected, this signal is the host data strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HDS) following reset. Host Write Data--When HDI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the host write data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HWR) following reset. Port B 12--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
HWR/ HWR
Input
PB12
Input, output, or disconnected
MOTOROLA
DSP56367
2-11
Signal/Connection Descriptions Parallel Host Interface (HDI08)
Table 2-9 Host Interface (Continued)
Signal Name Type State during Reset GPIO disconnected Signal Description
HCS
Input
Host Chip Select--When HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is the host chip select (HCS) input. The polarity of the chip select is programmable, but is configured active-low (HCS) after reset. Host Address 10--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 10 of the host address (HA10) input bus. Port B 13--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
HA10
Input
PB13
Input, output, or disconnected
HOREQ/HOREQ
Output
GPIO disconnected
Host Request--When HDI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host request (HOREQ) output. The polarity of the host request is programmable, but is configured as active-low (HOREQ) following reset. The host request may be programmed as a driven or open-drain output. Transmit Host Request--When HDI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the transmit host request (HTRQ) output. The polarity of the host request is programmable, but is configured as active-low (HTRQ) following reset. The host request may be programmed as a driven or open-drain output. Port B 14--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
HTRQ/ HTRQ
Output
PB14
Input, output, or disconnected
HACK/ HACK
Input
GPIO disconnected
Host Acknowledge--When HDI08 is programmed to interface a single host request host bus and the HI function is selected, this signal is the host acknowledge (HACK) Schmitt-trigger input. The polarity of the host acknowledge is programmable, but is configured as active-low (HACK) after reset. Receive Host Request--When HDI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the receive host request (HRRQ) output. The polarity of the host request is programmable, but is configured as active-low (HRRQ) after reset. The host request may be programmed as a driven or open-drain output. Port B 15--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected.
HRRQ/ HRRQ
Output
PB15
Input, output, or disconnected
The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
2-12
DSP56367
MOTOROLA
Signal/Connection Descriptions Serial Host Interface
2.8
SERIAL HOST INTERFACE
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode. Table 2-10 Serial Host Interface Signals
Signal Name Signal Type State during Reset Tri-stated Signal Description
SCK
Input or output
SPI Serial Clock--The SCK signal is an output when the SPI is configured as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol. I2C Serial Clock--SCL carries the clock for I2C bus transactions in the I2C mode. SCL is a Schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. SCL should be connected to VCC through a pull-up resistor. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 3.3V tolerant.
SCL
Input or output
MISO
Input or output
Tri-stated
SPI Master-In-Slave-Out--When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted. An external pull-up resistor is not required for SPI operation. I2C Data and Acknowledge--In I2C mode, SDA is a Schmitt-trigger input when receiving and an open-drain output when transmitting. SDA should be connected to VCC through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events. A high-to-low transition of the SDA line while SCL is high is a unique situation, and is defined as the start event. A low-to-high transition of SDA while SCL is high is a unique situation defined as the stop event. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 3.3V tolerant.
SDA
Input or open-drain output
MOTOROLA
DSP56367
2-13
Signal/Connection Descriptions Serial Host Interface
Table 2-10 Serial Host Interface Signals (Continued)
Signal Name Signal Type State during Reset Tri-stated Signal Description
MOSI
Input or output
SPI Master-Out-Slave-In--When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. I2C Slave Address 0--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for I2C slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when configured for the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 3.3V tolerant.
HA0
Input
SS
Input
Tri-stated
SPI Slave Select--This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI master mode, this signal should be kept deasserted (pulled high). If it is asserted while configured as SPI master, a bus error condition is flagged. If SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state. I2C Slave Address 2--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for the I2C Slave mode, the HA2 signal is used to form the slave device address. HA2 is ignored in the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 3.3V tolerant.
HA2
Input
HREQ
Input or Output
Tri-stated
Host Request--This signal is an active low Schmitt-trigger input when configured for the master mode but an active low output when configured for the slave mode. When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. When configured for the master mode, HREQ is an input. When asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer. This signal is tri-stated during hardware, software, personal reset, or when the HREQ1-HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in this state. This input is 3.3V tolerant.
2-14
DSP56367
MOTOROLA
Signal/Connection Descriptions Enhanced Serial Audio Interface
2.9
ENHANCED SERIAL AUDIO INTERFACE
Table 2-11 Enhanced Serial Audio Interface Signals
Signal Name HCKR
Signal Type Input or output
State during Reset GPIO disconnected
Signal Description High Frequency Clock for Receiver--When programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock. Port C 2--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
PC2
Input, output, or disconnected
HCKT
Input or output
GPIO disconnected
High Frequency Clock for Transmitter--When programmed as an input, this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock. Port C 5--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
PC5
Input, output, or disconnected
FSR
Input or output
GPIO disconnected
Frame Sync for Receiver--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode.
PC1
Input, output, or disconnected
Port C 1--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
MOTOROLA
DSP56367
2-15
Signal/Connection Descriptions Enhanced Serial Audio Interface
Table 2-11 Enhanced Serial Audio Interface Signals (Continued)
Signal Name FST Signal Type Input or output State during Reset GPIO disconnected Signal Description Frame Sync for Transmitter--This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). Port C 4--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. SCKR Input or output GPIO disconnected Receiver Serial Clock--SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. PC0 Input, output, or disconnected Port C 0--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. SCKT Input or output GPIO disconnected Transmitter Serial Clock--This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. Port C 3--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. SDO5 SDI0 PC6 Output Input Input, output, or disconnected GPIO disconnected Serial Data Output 5--When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0--When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register. Port C 6--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
PC4
Input, output, or disconnected
PC3
Input, output, or disconnected
2-16
DSP56367
MOTOROLA
Signal/Connection Descriptions Enhanced Serial Audio Interface
Table 2-11 Enhanced Serial Audio Interface Signals (Continued)
Signal Name SDO4 SDI1 PC7 Signal Type Output Input Input, output, or disconnected State during Reset GPIO disconnected Signal Description Serial Data Output 4--When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1--When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. Port C 7--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. SDO3/SD O3_1 SDI2/SDI 2_1 PC8/PE8 Output GPIO disconnected Serial Data Output 3--When programmed as a transmitter, SDO3 is used to transmit data from the TX3 serial transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 3. Serial Data Input 2--When programmed as a receiver, SDI2 is used to receive serial data into the RX2 serial receive shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input 2. Port C 8--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 8 signal. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. SDO2/SD O2_1 SDI3/SDI 3_1 PC9/PE9 Output GPIO disconnected Serial Data Output 2--When programmed as a transmitter, SDO2 is used to transmit data from the TX2 serial transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 2. Serial Data Input 3--When programmed as a receiver, SDI3 is used to receive serial data into the RX3 serial receive shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input 3. Port C 9--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 9 signal. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. SDO1/SD O1_1 PC10/PE1 0 Output GPIO disconnected Serial Data Output 1--SDO1 is used to transmit data from the TX1 serial transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 1. Port C 10--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 10 signal. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
Input
Input, output, or disconnected
Input
Input, output, or disconnected
Input, output, or disconnected
MOTOROLA
DSP56367
2-17
Signal/Connection Descriptions Enhanced Serial Audio Interface
Table 2-11 Enhanced Serial Audio Interface Signals (Continued)
Signal Name SDO0/SD O0_1 PC11/PE1 1 Signal Type Output State during Reset GPIO disconnected Signal Description Serial Data Output 0--SDO0 is used to transmit data from the TX0 serial transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 0. Port C 11--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 11 signal. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
Input, output, or disconnected
2-18
DSP56367
MOTOROLA
Signal/Connection Descriptions Enhanced Serial Audio Interface_1
2.10
ENHANCED SERIAL AUDIO INTERFACE_1
Table 2-12 Enhanced Serial Audio Interface_1 Signals
Signal Name FSR_1
Signal Type Input or output
State during Reset GPIO disconnected
Signal Description Frame Sync for Receiver_1--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode.
PE1
Input, output, or disconnected
Port E 1--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 3.3V.
FST_1
Input or output
GPIO disconnected
Frame Sync for Transmitter_1--This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). Port E 4--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 3.3V.
PE4
Input, output, or disconnected
SCKR_1
Input or output
GPIO disconnected
Receiver Serial Clock_1--SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode.
PE0
Input, output, or disconnected
Port E 0--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 3.3V.
MOTOROLA
DSP56367
2-19
Signal/Connection Descriptions SPDIF Transmitter Digital Audio Interface
Table 2-12 Enhanced Serial Audio Interface_1 Signals
Signal Name SCKT_1 Signal Type Input or output State during Reset GPIO disconnected Signal Description Transmitter Serial Clock_1--This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. Port E 3--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 3.3V. SDO5_1 SDI0_1 PE6 Output Input Input, output, or disconnected GPIO disconnected Serial Data Output 5_1--When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0_1--When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register. Port E 6--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 3.3V. SDO4_1 SDI1_1 PE7 Output Input Input, output, or disconnected GPIO disconnected Serial Data Output 4_1--When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1_1--When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. Port E 7--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
PE3
Input, output, or disconnected
2.11
SPDIF TRANSMITTER DIGITAL AUDIO INTERFACE
Table 2-13 Digital Audio Interface (DAX) Signals
Signal Name ACI
Type
State During Reset
Signal Description
Input
GPIO Disconnected Audio Clock Input--This is the DAX clock input. When programmed to use an external clock, this input supplies the DAX clock. The external clock frequency must be 256, 384, or 512 times the audio sampling frequency (256 x Fs, 384 x Fs or 512 x Fs, respectively). Port D 0--When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.
PD0
Input, output, or disconnected
The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
2-20
DSP56367
MOTOROLA
Signal/Connection Descriptions Timer
Table 2-13 Digital Audio Interface (DAX) Signals (Continued)
Signal Name ADO Type State During Reset Signal Description
Output
GPIO Disconnected Digital Audio Data Output--This signal is an audio and non-audio output in the form of AES/EBU, CP340 and IEC958 data in a biphase mark format. Port D 1--When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected.
PD1
Input, output, or disconnected
The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
2.12
TIMER
Table 2-14 Timer Signal
Signal Name
Type
State during Reset Input
Signal Description
TIO0
Input or Output
Timer 0 Schmitt-Trigger Input/Output--When timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 0 control/status register (TCSR0). If TIO0 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected to Vcc through a pull-up resistor in order to ensure a stable logic level at this input. This input is 3.3V tolerant.
2.13
JTAG/OnCE INTERFACE
Table 2-15 JTAG/OnCE Interface
Signal Name
Signal Type
State during Reset Input
Signal Description
TCK
Input
Test Clock--TCK is a test clock input signal used to synchronize the JTAG test logic. It has an internal pull-up resistor. This input is 3.3V tolerant.
MOTOROLA
DSP56367
2-21
Signal/Connection Descriptions JTAG/OnCE Interface
Table 2-15 JTAG/OnCE Interface (Continued)
Signal Name Signal Type State during Reset Input Signal Description
TDI
Input
Test Data Input--TDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 3.3V tolerant.
TDO
Output
Tri-stated
Test Data Output--TDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. Test Mode Select--TMS is an input signal used to sequence the test controller's state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 3.3V tolerant.
TMS
Input
Input
2-22
DSP56367
MOTOROLA
SECTION
3
SPECIFICATIONS
3.1 INTRODUCTION
The DSP56367 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs and outputs. Note: This document contains information on a new product. Specifications and information herein are subject to change without notice.
Finalized specifications may be published after further characterization and device qualifications are completed.
3.2
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either GND or VCC). The suggested value for a pullup or pulldown resistor is 10 k.
Note:
In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification
MOTOROLA
DSP56367
3-1
Specifications Maximum Ratings
is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 3-1 Maximum Ratings
Rating1 Supply Voltage Symbol VCCQL, VCCP VCCQH, VCCA, VCCD, VCCC, VCCH, VCCS, All "3.3V tolerant" input voltages Current drain per pin excluding VCC and GND Operating temperature range3 Storage temperature Note: 1. 2. 3. VIN I TJ TSTG Value1, 2 Unit V
-0.3 to + 2.0 -0.3 to + 4.0
GND - 0.3 to VCC + 0.7 10
V
V mA
-40 to + 95 -55 to +125
C C
GND = 0 V, VCCP, VCCQL = 1.8 V 5%, TJ = -40xC to +95xC, CL = 50 pF All other VCC = 3.3 V 5%, TJ = -40xC to +95xC, CL = 50 pF Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. Temperatures below -0C are qualified for consumer applications.
3-2
DSP56367
MOTOROLA
Specifications Thermal Characteristics
3.3
THERMAL CHARACTERISTICS
Table 3-2 Thermal Characteristics
Characteristic Symbol RJA or JA RJC or JC JT TQFP Value 45.0 10.0 3.0 Unit
Natural Convection, Junction-to-ambient thermal resistance1,2 Junction-to-case thermal resistance3 Natural Convection, Thermal characterization parameter4 Note: 1.
C/W C/W C/W
2. 3. 4.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
3.4
DC ELECTRICAL CHARACTERISTICS
Table 3-3 DC Electrical Characteristics5
Characteristics Symbol VCC Min 1.71 Typ 1.8 Max 1.89 Unit V
Supply voltages * Core (VCCQL) * PLL(VCCP) Supply voltages * VCCQH * VCCA * VCCD * VCCC * VCCH * VCCS Input high voltage * D(0:23), BG, BB, TA, ESAI_1 (except
SDO4_1)
VCC
3.14
3.3
3.46
V
V VIH VIHP 2.0 2.0 -- -- VCCQH VCCQH + 03 max for both VIHP VCCQH + 03 max for both VIHP 0.8 x VCCQH
*
MOD1/IRQ1, RESET, PINIT/NMI and all JTAG/ESAI_1/Timer/HDI08/DAX/(only SDO4_1)/SHI(SPI mode) SHI(I2C mode)
*
VIHP
1.5 0.8 x VCCQH
--
*
EXTAL
VIHX
--
MOTOROLA
DSP56367
3-3
Specifications AC Electrical Characteristics
Table 3-3 DC Electrical Characteristics5 (Continued)
Characteristics Input low voltage * D(0:23), BG, BB, TA, ESAI_1(except
SDO4_1)
Symbol
Min
Typ
Max
Unit V
VIL VILP
-0.3 -0.3
-- --
0.8 0.8
*
MOD1/IRQ1, RESET, PINIT/NMI and all JTAG/ESAI/Timer/HDI08/DAX/ESAI_1(on ly SDO4_1)/SHI(SPI mode) SHI(I2C mode) EXTAL
* *
VILP VILX IIN ITSI
-0.3 -0.3 -10 -10
-- -- -- --
0.3 x VCC 0.2 x VCCQH 10 10 A A
Input leakage current High impedance (off-state) input current (@ 2.4 V / 0.4 V) Output high voltage6
VOH Output low voltage6 VOL Internal supply current2 at internal clock of 150MHz ICCI * * * In Normal mode In Wait mode In Stop mode3 ICCW ICCS
2.4
--
--
V V
--
--
0.4
--
58.0
115
mA
-- -- --
7.3 2.0 1 --
20 4 2.5 10
mA mA mA pF
PLL supply current Input capacitance4 Note: 1. 2. CIN
--
3. 4. 5. 6.
Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC,and MODD/IRQD pins The Power Consumption Considerations section provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCCQL = 1.8V, VCC(other) = 3.3V at TJ = 25C. Maximum internal supply current is measured with VCCQL = 1.89V, VCC(other) = 3.46V at TJ = 95C. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float). Periodically sampled and not 100% tested VCCQL = 1.8 V 5%, TJ = -40C to +95C, CL = 50 pF All other VCC = 3.3 V 5%, TJ = -40C to +95C, CL = 50 pF This characteristic does not apply to PCAP.
3.5
AC ELECTRICAL CHARACTERISTICS
The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.4 V and a VIH minimum of 2.4 V for all pins except EXTAL. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal's transition. DSP56367 output levels
3-4
DSP56367
MOTOROLA
Specifications AC Electrical Characteristics
are measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively. Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15 MHz and rated speed.
MOTOROLA
DSP56367
3-5
Specifications Internal Clocks
3.6
INTERNAL CLOCKS
Table 3-4 Internal Clocks
Expression1, 2 Characteristics Symbol Min Typ (Ef x MF)/ (PDF x DF) Ef/2 Max -- --
Internal operation frequency with PLL enabled Internal operation frequency with PLL disabled Internal clock high period * * With PLL disabled With PLL enabled and MF 4 With PLL enabled and MF > 4
f f
-- --
TH
-- 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF
ETC --
-- 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF
*
--
Internal clock low period * * With PLL disabled With PLL enabled and MF 4 With PLL enabled and MF > 4 TC TC ICYC TL -- 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF -- ETC -- -- 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF --
*
-- ETC x PDF x DF/MF 2 x ETC TC
Internal clock cycle time with PLL enabled Internal clock cycle time with PLL disabled Instruction cycle time Note: 1.
-- --
-- --
2.
DF = Division Factor Ef = External frequency ETC = External clock cycle MF = Multiplication Factor PDF = Predivision Factor TC = internal clock cycle Refer to the DSP56300 Family
Manual for a detailed discussion of the PLL.
3-6
DSP56367
MOTOROLA
Specifications External Clock Operation
3.7
EXTERNAL CLOCK OPERATION
The DSP56367 system clock is an externally supplied square wave voltage source connected to EXTAL(Figure 3-1).
VIHC EXTAL VILC ETH ETL 4 Midpoint
2
3 ETC
Note:
The midpoint is 0.5 (VIHC + VILC).
Figure 3-1 External Clock Timing
Table 3-5 Clock Operation
No. 1 Characteristics Frequency of EXTAL (EXTAL Pin Frequency) The rise and fall time of this external clock should be 2 ns maximum. EXTAL input high1, 2 * With PLL disabled (46.7%-53.3% duty cycle4) * 3 With PLL enabled (42.5%-57.5% duty cycle4) ETL Symbol Ef Min 2.0 ns Max 150.0
2
ETH
3.11 ns 2.83 ns 3.11 ns 2.83 ns
157.0 s 157.0 s 273.1 s 8.53 s
EXTAL input low1, 2 * With PLL disabled (46.7%-53.3% duty cycle4) * With PLL enabled (42.5%-57.5% duty cycle4)
4
EXTAL cycle time2 * With PLL disabled * With PLL enabled TC3
ETC
6.7 ns 6.7 ns
7
Instruction cycle time = ICYC = * With PLL disabled * With PLL enabled
ICYC
13.33 ns 6.67 ns
Note:
1. 2. 3. 4.
Measured at 50% of the input transition The maximum value for PLL enabled is given for minimum VCO and maximum MF. The maximum value for PLL enabled is given for minimum VCO and maximum DF. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met.
MOTOROLA
DSP56367
3-7
Specifications Phase Lock Loop (PLL) Characteristics
3.8
PHASE LOCK LOOP (PLL) CHARACTERISTICS
Table 3-6 PLL Characteristics
Characteristics Min 30 Max 300 Unit MHz
VCO frequency when PLL enabled (MF x Ef x 2/PDF) PLL external capacitor (PCAP pin to VCCP) (CPCAP1) * * Note: @ MF 4 @ MF > 4 1.
(MF x 580) - 100 MF x 830
(MF x 780) - 140 MF x 1470
pF
CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for CPCAP can be computed from one of the following equations: (MF x 680)-120, for MF 4, or MF x 1100, for MF > 4.
3.9
RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing
No. 8 9
Characteristics Delay from RESET assertion to all pins at reset value3 Required RESET duration4 * Power on, external clock generator, PLL disabled * * * * * Power on, external clock generator, PLL enabled Power on, Internal oscillator During STOP, XTAL disabled During STOP, XTAL enabled During normal operation
Expression --
Min --
Max 26.0
Unit ns
50 x ETC 1000 x ETC 75000 x ETC 75000 x ETC 2.5 x TC 2.5 x TC
333.4
--
ns
6.7 500 500 16.7 16.7
-- -- -- -- --
s s s ns ns
10
Delay from asynchronous RESET deassertion to first external address output (internal reset deassertion)5 * * Minimum Maximum 3.25 x TC + 2.0 20.25 x TC + 10 23.7 -- -- 145.0 ns ns
11
Syn reset setup time from RESET * Maximum TC -- 6.7 ns
3-8
DSP56367
MOTOROLA
Specifications Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing
No. 12 Characteristics Syn reset deassert delay time * * 13 14 15 16 17 Minimum Maximum 3.25 x TC + 1.0 20.25 x TC + 5.0 22.7 -- 30.0 0.0 4.4 4.4 -- 140.0 -- -- -- -- ns ns ns ns ns ns Expression Min Max Unit
Mode select setup time Mode select hold time Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory access address out valid * Caused by first interrupt instruction fetch * Caused by first interrupt instruction execution
4.25 x TC + 2.0 7.25 x TC + 2.0 10 x TC + 5.0
30.3 50.3 71.7
-- -- --
ns ns ns
18
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts1,7,8
19
(WS + 3.75) x TC - 10.94
--
Note 8
ns
20
Delay from RD assertion to interrupt request deassertion for level sensitive fast interrupts1,7,8
(WS + 3.25) x TC - 10.94
--
Note 8
ns
21
Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts1, 7, 8 * DRAM for all WS (WS + 3.5) x TC - 10.94 -- Note 8
ns
* * * 22
SRAM WS = 1 SRAM WS = 2, 3 SRAM WS 4
N/A 1.75 x TC - 4.0 2.75 x TC - 4.0 0.6 x TC - 0.1
-- -- --
Note 8 Note 8 Note 8
Synchronous int setup time from IRQs NMI assertion to the CLKOUT trans. 3.9 -- ns
23
Synch. int delay time from the CLKOUT trans2 to the first external address out valid caused by first inst fetch * * Minimum Maximum 9.25 x TC + 1.0 24.75 x TC + 5.0 0.6 x TC - 0.1 62.7 -- 3.9 -- 170.0 -- ns ns ns
24
Duration for IRQA assertion to recover from Stop state
MOTOROLA
DSP56367
3-9
Specifications Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing
No. 25 Characteristics Delay from IRQA assertion to fetch of first instruction (when exiting Stop)2, 3 * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) PLC x ETC x PDF + (128 K - PLC/2) x TC PLC x ETC x PDF + (23.75 +/0.5) x TC Expression Min Max Unit
--
--
ms
--
--
ms
*
PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop Delay)
(8.25 0.5) x TC
51.7
58.3
ns
26
Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)2, 3 * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay) PLC x ETC x PDF + (128 K - PLC/2) x TC PLC x ETC x PDF + (20.5 +/0.5) x TC 5.5 x TC
--
--
ms
--
--
ms
*
36.7
--
ns
27
Interrupt Requests Rate * HDI08, ESAI, ESAI_1, SHI, DAX, Timer * * * DMA IRQ, NMI (edge trigger) IRQ (level trigger)
12TC 8TC 8TC 12TC
-- -- -- --
80.0 53.0 53.0 80.0
ns ns ns ns
28
DMA Requests Rate * Data read from HDI08, ESAI, ESAI_1, SHI, DAX * * * Data write to HDI08, ESAI, ESAI_1, SHI, DAX Timer IRQ, NMI (edge trigger)
6TC 7TC 2TC 3TC
--
40.0
ns
--
46.7 13.3
ns
--
20.0
ns
3-10
DSP56367
MOTOROLA
Specifications Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing
No. 29 Characteristics Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory (DMA source) access address out valid 1. Expression 4.25 x TC + 2.0 Min 30.3 Max -- Unit ns
Note:
When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. This timing depends on several settings: For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by the PCTL Bit 17 and OMR Bit 6 settings. For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs: the stop delay counter completes count or PLL lock procedure completion. PLC value for PLL disable is 0. The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 150 MHz it is 4096/150 MHz = 27.3 s). During the stabilization period, TC, TH, and TL will not be constant, and their width may vary, so timing may vary as well.
2.
3. 4.
Periodically sampled and not 100% tested RESET duration is measured during the time in which RESET is asserted, VCC is valid, and the EXTAL input is active and valid. When the VCC is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. If PLL does not lose lock VCCQH = 3.3 V 5%; VCC= 1.8V 5%; TJ = -40C to + 95C, CL = 50 pF WS = number of wait states (measured in clock cycles, number of TC). Use expression to compute maximum value.
5. 6. 7. 8.
VIH
RESET
9 8 All Pins Reset Value
10
A0-A17
First Fetch
AA0460
Figure 3-2 Reset Timing
MOTOROLA
DSP56367
3-11
Specifications Reset, Stop, Mode Select, and Interrupt Timing
A0-A17
First Interrupt Instruction Execution/Fetch
RD 20 WR
21 IRQA, IRQB, IRQC, IRQD, NMI 17 19
a) First Interrupt Instruction Execution
General Purpose I/O 18 IRQA, IRQB, IRQC, IRQD, NMI b) General Purpose I/O
Figure 3-3 External Fast Interrupt Timing
3-12
DSP56367
MOTOROLA
Specifications Reset, Stop, Mode Select, and Interrupt Timing
IRQA, IRQB, IRQC, IRQD, NMI 15 IRQA, IRQB, IRQC, IRQD, NMI
16
AA0463
Figure 3-4 External Interrupt Timing (Negative Edge-Triggered)
RESET
VIH 13 14
MODA, MODB, MODC, MODD, PINIT
VIH VIL
VIH VIL
IRQA, IRQB, IRQD, NMI
AA0465
Figure 3-5 Operating Mode Select Timing
24 IRQA
25 First Instruction Fetch
AA0466
A0-A17
Figure 3-6 Recovery from Stop State Using IRQA Interrupt Service
MOTOROLA
DSP56367
3-13
Specifications Reset, Stop, Mode Select, and Interrupt Timing
26 IRQA 25 A0-A17
First IRQA Interrupt Instruction Fetch AA0467
Figure 3-7 Recovery from Stop State Using IRQA Interrupt Service
A0-A17
DMA Source Address
RD
WR 29 IRQA, IRQB, IRQC, IRQD, NMI First Interrupt Instruction Execution
AA110
Figure 3-8 External Memory Access (DMA Source) Timing
3-14
DSP56367
MOTOROLA
Specifications External Memory Expansion Port (Port A)
3.10
EXTERNAL MEMORY EXPANSION PORT (PORT A)
3.10.1
SRAM TIMING
Table 3-8 SRAM Read and Write Accesses
150 MHz
No.
Characteristics
Symbol
Expression1 Min Max --
Unit
100
Address valid and AA assertion pulse width
tRC, tWC
(WS + 2) x TC - 4.0 [2 WS 7] (WS + 3) x TC - 4.0 [WS 8] 0.75 x TC - 2.0 [2 WS 3] 1.25 x TC - 2.0 [WS 4]
22.7
ns
69.3
--
ns
101
Address and AA valid to WR assertion
tAS
3.0
--
ns
6.3
--
ns
102
WR assertion pulse width
tWP
WS x TC - 4.0 [2 WS 3] (WS - 0.5) x TC - 4.0 [WS 4]
9.3
--
ns
19.3
--
ns
103
WR deassertion to address not valid
tWR
1.25 x TC - 4.0 [2 WS 7] 2.25 x TC - 4.0 [WS 8] (WS + 0.75) x TC - 5.0 [WS 2] (WS + 0.25) x TC - 5.0 [WS 2]
4.3
--
ns
11.0
--
ns
104
Address and AA valid to input data valid
tAA, tAC
--
13.3
ns
105
RD assertion to input data valid
tOE
--
10.0
ns
106 107
RD deassertion to data not valid (data hold time) Address valid to WR deassertion2
tOHZ tAW (WS + 0.75) x TC - 4.0 [WS 2] (WS - 0.25) x TC - 3.0 [WS 2]
0.0 14.3
-- --
ns ns
108
Data valid to WR deassertion (data setup time)
tDS (tDW)
8.7
--
ns
MOTOROLA
DSP56367
3-15
Specifications External Memory Expansion Port (Port A)
Table 3-8 SRAM Read and Write Accesses (Continued)
150 MHz No. Characteristics Symbol Expression1 Min 109 Data hold time from WR deassertion tDH 1.25 x TC - 2.0 [2 WS 7] 2.25 x TC - 2.0 [WS 8] 0.25 x TC - 3.7 [2 WS 3] -0.25 x TC - 3.7 [WS 4] 0.25 x TC + 0.2 [2 WS 3] 1.25 x TC + 0.2 [4 WS 7] 2.25 x TC + 0.2 [WS 8] 112 Previous RD deassertion to data active (write) -- 1.25 x TC - 4.0 [2 WS 3] 2.25 x TC - 4.0 [4 WS 7] 3.25 x TC - 4.0 [WS 8] 113 RD deassertion time 1.75 x TC - 4.0 [2 WS 7] 2.75 x TC - 4.0 [WS 8] 114 WR deassertion time 2.0 x TC - 4.0 [2 WS 3] 2.5 x TC - 4.0 [4 WS 7] 3.5 x TC - 4.0 [WS 8] 115 116 Address valid to RD assertion RD assertion pulse width 0.5 x TC - 2.0 (WS + 0.25) x TC -4.0 6.3 Max -- ns Unit
13.0
--
ns
110
WR assertion to data active
--
-2.0
--
ns
-5.4
--
ns
111
WR deassertion to data high impedance
--
--
1.9
ns
--
8.5
--
15.2
4.3
--
ns
11.0
--
17.7
--
7.7
--
ns
14.3
--
ns
9.3
--
ns
12.7
--
ns
19.3
--
ns
1.3 11.0
-- --
ns ns
3-16
DSP56367
MOTOROLA
Specifications External Memory Expansion Port (Port A)
Table 3-8 SRAM Read and Write Accesses (Continued)
150 MHz No. Characteristics Symbol Expression1 Min 117 RD deassertion to address not valid 1.25 x TC - 2.0 [2 WS 7] 2.25 x TC - 2.0 [WS 8] 118 119 Note: TA setup before RD or WR deassertion3 TA hold after RD or WR deassertion 1. 0.25 x TC + 2.0 6.3 Max -- ns Unit
13.0
--
ns
3.7 0.0
-- --
ns ns
2. 3.
WS is the number of wait states specified in the BCR. The value is given for the minimum for a given category. (For example, for a category of [2 WS 7] timing is specified for 2 wait states.) Two wait states is the minimum otherwise. Timings 100, 107 are guaranteed by design, not tested. In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active
100 A0-A17 AA0-AA2 113 RD 115 WR 104 119 TA D0-D23 Data In
AA0468
116
117
105
106
118
Figure 3-9 SRAM Read Access
MOTOROLA
DSP56367
3-17
Specifications External Memory Expansion Port (Port A)
100 A0-A17 AA0-AA2 107 101 WR 114 RD 119 TA 108 109 D0-D23 Data Out 118 102 103
Figure 3-10 SRAM Write Access
3-18
DSP56367
MOTOROLA
Specifications External Memory Expansion Port (Port A)
3.10.2
DRAM TIMING
The selection guides provided in Figure 3-11 and Figure 3-14 should be used for primary selection only. Final selection should be based on the timing provided in the following tables. As an example, the selection guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode DRAM. However, by using the information in the appropriate table, a designer may choose to evaluate whether fewer wait states might be used by determining which timing prevents operation at 100 MHz, running the chip at a slightly lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available), and control factors such as capacitive and resistive load to improve overall system performance.
DRAM Type (tRAC ns)
Note:
This figure should be use for primary selection. For exact and detailed timings see the following tables.
100
80
70
60
50 40 66 80 100 120
Chip Frequency (MHz)
1 Wait States 2 Wait States
3 Wait States 4 Wait States
AA047
Figure 3-11 DRAM Page Mode Wait States Selection Guide
MOTOROLA
DSP56367
3-19
Specifications External Memory Expansion Port (Port A)
Table 3-9 DRAM Page Mode Timings, Three Wait States
100 MHz No. Characteristics Symbol Expression Min 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses 132 133 134 135 136 137 138 CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS assertion5 * BRW[1:0] = 00, 01-- not applicable * * 139 140 141 142 143 144 145 146 147 148 149 150 BRW[1:0] = 10 BRW[1:0] = 11 tCP tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tCAC tAA tOFF tRSH tRHCP tCAS tCRP 2.5 x TC - 4.0 4.5 x TC - 4.0 2 x TC - 4.0 tPC 2 x TC 1.25 x TC 2 x TC - 7.0 3 x TC - 7.0 20.0 Max -- ns Unit
12.5 -- -- 0.0 21.0 41.0 16.0
-- 13.0 23.0 -- -- -- -- ns ns ns ns ns ns
4.75 x TC - 6.0 6.75 x TC - 6.0 1.5 x TC - 4.0 TC - 4.0 2.5 x TC - 4.0 4 x TC - 4.0 1.25 x TC - 4.0 0.75 x TC - 4.0 2.25 x TC - 4.2 3.5 x TC - 4.5 3.75 x TC - 4.3 3.25 x TC - 4.3 0.5 x TC - 4.0 2.5 x TC - 4.0
41.5 61.5 11.0 6.0 21.0 36.0 8.5 3.5 18.3 30.5 33.2 28.2 1.0 21.0
-- -- -- -- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write)
3-20
DSP56367
MOTOROLA
Specifications External Memory Expansion Port (Port A)
Table 3-9 DRAM Page Mode Timings, Three Wait States (Continued)
100 MHz No. Characteristics Symbol Expression Min 151 152 153 154 155 156 Note: WR assertion to CAS assertion Last RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid6 WR assertion to data active WR deassertion to data high impedance 1. 2. 3. 4. 5. 6. tWCS tROH tGA tGZ 0.75 x TC - 0.3 0.25 x TC 1.25 x TC - 4.3 3.5 x TC - 4.0 2.5 x TC - 7.0 8.2 31.0 -- 0.0 7.2 -- Max -- -- 18.0 -- -- 2.5 ns ns ns ns ns ns Unit
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56367. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 4 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
Table 3-10 DRAM Page Mode Timings, Four Wait States1, 2, 3
100 MHz No. Characteristics Symbol Expression
4
Unit Min Max
131
Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses tPC
5 x TC
50.0
--
ns
4.5 x TC 2.75 x TC - 5.7 3.75 x TC - 5.7
45.0
-- 21.8 31.8 -- -- -- --
ns ns ns ns ns ns ns
132 133 134 135 136 137
CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width
tCAC tAA tOFF tRSH tRHCP tCAS
-- -- 0.0
3.5 x TC - 4.0 6 x TC - 4.0 2.5 x TC - 4.0
31.0 56.0 21.0
MOTOROLA
DSP56367
3-21
Specifications External Memory Expansion Port (Port A)
Table 3-10 DRAM Page Mode Timings, Four Wait States1, 2, 3 (Continued)
100 MHz No. Characteristics Symbol Expression4 Min 138 Last CAS deassertion to RAS assertion5 BRW[1-0] = 00, 01--Not applicable BRW[1-0] = 10 BRW[1-0] = 11 CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) WR assertion to CAS assertion Last RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid6 WR assertion to data active WR deassertion to data high impedance 1. 2. 3. 4. tCRP -- 5.25 x TC - 6.0 7.25 x TC - 6.0 tCP tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS tROH tGA tGZ 0.75 x TC - 1.5 0.25 x TC 2 x TC - 4.0 TC - 4.0 3.5 x TC - 4.0 5 x TC - 4.0 1.25 x TC - 4.0 1.25 x TC - 3.7 3.25 x TC - 4.2 4.5 x TC - 4.5 4.75 x TC - 4.3 3.75 x TC - 4.3 0.5 x TC - 4.5 3.5 x TC - 4.0 1.25 x TC - 4.3 4.5 x TC - 4.0 3.25 x TC - 5.7 -- 46.5 66.5 16.0 6.0 31.0 46.0 8.5 8.8 28.3 40.5 43.2 33.2 0.5 31.0 8.2 41.0 -- 0.0 6.0 -- Max Unit
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 26.8 -- -- 2.5
-- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Note:
5. 6.
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56367. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals 3 x TC for read-after-read or write-after-write sequences). An expressions is used to calculate the maximum or minimum value listed, as appropriate. BRW[1-0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
3-22
DSP56367
MOTOROLA
Specifications External Memory Expansion Port (Port A)
RAS 136 131 CAS 137 140 141 A0-A17
Row Add Column Address Column Address
135
139
138 142
Last Column Address
151 145 WR 146 RD 155
144
143 147
148
156 150
149 D0-D23
Data Out Data Out Data Out AA0473
Figure 3-12 DRAM Page Mode Write Accesses
MOTOROLA
DSP56367
3-23
Specifications External Memory Expansion Port (Port A)
RAS
136 131 CAS 137 140 A0-A17
Row Add Column Address
135
139 141
Column Address
138 142
Last Column Address
143 WR 132 133 153 RD 134 154 D0-D23
Data In Data In Data In AA0474
152
Figure 3-13 DRAM Page Mode Read Accesses
3-24
DSP56367
MOTOROLA
Specifications External Memory Expansion Port (Port A)
DRAM Type (tRAC ns)
Note:This figure should be use for primary selection. For exact and detailed timings see the following tables.
100
80
70
60
50 40 66 80 100 120 11 Wait States 15 Wait States
Chip Frequency (MHz)
4 Wait States 8 Wait States
AA047
Figure 3-14 DRAM Out-of-Page Wait States Selection Guide
Table 3-11 DRAM Out-of-Page and Refresh Timings, Four Wait States
20 MHz4 No. Characteristics3 Symbol Expression Min 157 158 159 160 161 162 163 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width tRC tRAC tCAC tAA tOFF tRP tRAS 1.75 x TC - 4.0 3.25 x TC - 4.0 5 x TC 2.75 x TC - 7.5 1.25 x TC - 7.5 1.5 x TC - 7.5 250.0 -- -- -- 0.0 83.5 158.5 Max -- 130.0 55.0 67.5 -- -- -- Min 166.7 -- -- -- 0.0 54.3 104.3 Max -- 84.2 34.2 42.5 -- -- -- ns ns ns ns ns ns ns 30 MHz4 Unit
MOTOROLA
DSP56367
3-25
Specifications External Memory Expansion Port (Port A)
Table 3-11 DRAM Out-of-Page and Refresh Timings, Four Wait States
20 MHz4 No. Characteristics3 Symbol Expression Min 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion RAS deassertion to WR assertion CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH tGA 1.75 x TC - 4.0 2.75 x TC - 4.0 1.25 x TC - 4.0 1.5 x TC 2 1.25 x TC 2 2.25 x TC - 4.0 1.75 x TC - 4.0 1.75 x TC - 4.0 1.25 x TC - 4.0 0.25 x TC - 4.0 1.75 x TC - 4.0 3.25 x TC - 4.0 2 x TC - 4.0 1.5 x TC - 3.8 0.75 x TC - 3.7 0.25 x TC - 3.7 1.5 x TC - 4.2 3 x TC - 4.2 4.5 x TC - 4.5 4.75 x TC - 4.3 4.25 x TC - 4.3 2.25 x TC - 4.0 1.75 x TC - 4.0 3.25 x TC - 4.0 3 x TC - 4.3 0.5 x TC - 4.0 1.25 x TC - 4.0 4.5 x TC - 4.0 4 x TC - 7.5 83.5 133.5 58.5 73.0 60.5 108.5 83.5 83.5 58.5 8.5 83.5 158.5 96.0 71.2 33.8 8.8 70.8 145.8 220.5 233.2 208.2 108.5 83.5 158.5 145.7 21.0 58.5 221.0 -- Max -- -- -- 77.0 64.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 192.5 Min 54.3 87.7 37.7 48.0 39.7 71.0 54.3 54.3 37.7 4.3 54.3 104.3 62.7 46.2 21.3 4.6 45.8 95.8 145.5 154.0 137.4 71.0 54.3 104.3 95.7 12.7 37.7 146.0 -- Max -- -- -- 52.0 43.7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 125.8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 30 MHz4 Unit
3-26
DSP56367
MOTOROLA
Specifications External Memory Expansion Port (Port A)
Table 3-11 DRAM Out-of-Page and Refresh Timings, Four Wait States
20 MHz4 No. Characteristics3 Symbol Expression Min 193 194 195 Note: RD deassertion to data not valid3 WR assertion to data active WR deassertion to data high impedance 1. 2. 3. 4. tGZ 0.75 x TC - 0.3 0.25 x TC 0.0 37.2 -- Max -- -- 12.5 Min 0.0 24.7 -- Max -- -- 8.3 ns ns ns 30 MHz4 Unit
The number of wait states for out of page access is specified in the DCR. The refresh period is specified in the DCR. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (Figure 3-14).
MOTOROLA
DSP56367
3-27
Specifications External Memory Expansion Port (Port A)
Table 3-12 DRAM Out-of-Page and Refresh Timings, Eleven Wait States
100 MHz No. Characteristics4 Symbol Expression3 Min 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR5 assertion RAS deassertion to WR5 assertion CAS assertion to WR deassertion RAS assertion to WR deassertion tRC tRAC tCAC tAA tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR 4.25 x TC - 4.0 7.75 x TC - 4.0 5.25 x TC - 4.0 6.25 x TC - 4.0 3.75 x TC - 4.0 2.5 x TC 4.0 1.75 x TC 4.0 5.75 x TC - 4.0 4.25 x TC - 4.0 4.25 x TC - 4.0 1.75 x TC - 4.0 0.75 x TC - 4.0 5.25 x TC - 4.0 7.75 x TC - 4.0 6 x TC - 4.0 3.0 x TC - 4.0 1.75 x TC - 4.0 0.25 x TC - 2.0 5 x TC - 4.2 7.5 x TC - 4.2 12 x TC 6.25 x TC - 7.0 3.75 x TC - 7.0 4.5 x TC - 7.0 120.0 -- -- -- 0.0 38.5 73.5 48.5 58.5 33.5 21.0 13.5 53.5 38.5 38.5 13.5 3.5 48.5 73.5 56.0 26.0 13.5 0.5 45.8 70.8 Max -- 55.5 30.5 38.0 -- -- -- -- -- -- 29.0 21.5 -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
3-28
DSP56367
MOTOROLA
Specifications External Memory Expansion Port (Port A)
Table 3-12 DRAM Out-of-Page and Refresh Timings, Eleven Wait States
100 MHz No. Characteristics4 Symbol Expression3 Min 182 183 184 185 186 187 188 189 190 191 192 WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH tGA 11.5 x TC - 4.5 11.75 x TC - 4.3 10.25 x TC - 4.3 5.75 x TC - 4.0 5.25 x TC - 4.0 7.75 x TC - 4.0 6.5 x TC - 4.3 1.5 x TC - 4.0 2.75 x TC - 4.0 11.5 x TC - 4.0 110.5 113.2 103.2 53.5 48.5 73.5 60.7 11.0 23.5 111.0 -- 10 x TC - 7.0 0.0 0.75 x TC - 0.3 0.25 x TC 7.2 -- -- -- 2.5 ns ns ns Max -- -- -- -- -- -- -- -- -- -- 93.0 ns ns ns ns ns ns ns ns ns ns ns Unit
193 194 195 Note:
RD deassertion to data not valid4 WR assertion to data active WR deassertion to data high impedance 1. 2. 3. 4. 5.
tGZ
The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56367. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Either tRCH or tRRH must be satisfied for read cycles.
Table 3-13 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2
100 MHz No. Characteristics Symbol Expression3 Min 157 158 159 160 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) tRC tRAC tCAC tAA 16 x TC 8.25 x TC - 5.7 4.75 x TC - 5.7 5.5 x TC - 5.7 160.0 -- -- -- Max -- 76.8 41.8 49.3 ns ns ns ns Unit
MOTOROLA
DSP56367
3-29
Specifications External Memory Expansion Port (Port A)
Table 3-13 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2
100 MHz No. Characteristics Symbol Expression3 Min 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR4 assertion RAS deassertion to WR4 assertion CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tCSR 0.0 6.25 x TC - 4.0 9.75 x TC - 4.0 6.25 x TC - 4.0 8.25 x TC - 4.0 4.75 x TC - 4.0 3.5 x TC 2 2.75 x TC 2 7.75 x TC - 4.0 6.25 x TC - 6.0 6.25 x TC - 4.0 2.75 x TC - 4.0 0.75 x TC - 4.0 6.25 x TC - 4.0 9.75 x TC - 4.0 7 x TC - 4.0 5 x TC - 3.8 1.75 x TC - 3.7 0.25 x TC - 2.0 6 x TC - 4.2 9.5 x TC - 4.2 15.5 x TC - 4.5 15.75 x TC - 4.3 14.25 x TC - 4.3 8.75 x TC - 4.0 6.25 x TC - 4.0 9.75 x TC - 4.0 9.5 x TC - 4.3 1.5 x TC - 4.0 0.0 58.5 93.5 58.5 78.5 43.5 33.0 25.5 73.5 56.5 58.5 23.5 3.5 58.5 93.5 66.0 46.2 13.8 0.5 55.8 90.8 150.5 153.2 138.2 83.5 58.5 93.5 90.7 11.0 Max -- -- -- -- -- -- 37.0 29.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
3-30
DSP56367
MOTOROLA
Specifications External Memory Expansion Port (Port A)
Table 3-13 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2
100 MHz No. Characteristics Symbol Expression3 Min 190 191 192 RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid tRPC tROH tGA tGZ 0.75 x TC - 1.5 0.25 x TC 4.75 x TC - 4.0 15.5 x TC - 4.0 14 x TC - 5.7 43.5 151.0 -- Max -- -- 134.3 ns 193 194 195 Note: RD deassertion to data not valid5 WR assertion to data active WR deassertion to data high impedance 1. 2. 3. 4. 5. 0.0 6.0 -- -- -- 2.5 ns ns ns ns ns Unit
The number of wait states for an out-of-page access is specified in the DCR. The refresh period is specified in the DCR. An expression is used to compute the maximum or minimum value listed (or both if the expression includes ). Either tRCH or tRRH must be satisfied for read cycles. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
MOTOROLA
DSP56367
3-31
Specifications External Memory Expansion Port (Port A)
157 162 RAS 167 169 168 170 CAS 171 173 174 175 A0-A17
Row Address Column Address
163 165
162
164 166
172 177 191 WR 160 159 RD 158 192
176 179
168
193 161
Data In AA0476
D0-D23
Figure 3-15 DRAM Out-of-Page Read Access
3-32
DSP56367
MOTOROLA
Specifications External Memory Expansion Port (Port A)
157 162 RAS 167 169 168 170 CAS 171 173 172 176 A0-A17 Row Address 181 175 188 WR 182 184 183 RD 185 194 D0-D23 Data Out
AA0477
163 165 164
162
166
174
Column Address
180
187 186 195
Figure 3-16 DRAM Out-of-Page Write Access
MOTOROLA
DSP56367
3-33
Specifications External Memory Expansion Port (Port A)
157 162 RAS 190 170 CAS 165 163 162
189 177 WR
AA0478
Figure 3-17 DRAM Refresh Access
3-34
DSP56367
MOTOROLA
Specifications External Memory Expansion Port (Port A)
3.10.3
ARBITRATION TIMINGS
Table 3-14 Asynchronous Bus Arbitration Timing
150 MHz No. Characteristics Expression Min
250 BB assertion window from BG input negation. Delay from BB assertion to BG assertion 1. 2. 3. 2 .5* Tc + 5 --
Max
21.7
Un it
ns
251 Note:
2 * Tc + 5
18.3
--
ns
Bit 13 in the OMR register must be set to enter Asynchronous Arbitration mode If Asynchronous Arbitration mode is active, none of the timings in Table 3-14 is required. In order to guarantee timings 250, and 251, it is recommended to assert BG inputs to different 56300 devices (on the same bus) in a non overlap manner as shown in Figure 3-18.
BG1
BB 250
BG2 251
Figure 3-18 Asynchronous Bus Arbitration Timing
MOTOROLA
DSP56367
3-35
Specifications Parallel Host Interface (HDI08) Timing
BG1
BG2
250+251
Figure 3-19 Asynchronous Bus Arbitration Timing Background explanation for Asynchronous Bus Arbitration: The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs. These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this delay, a 56300 part may assume mastership and assert BB for some time after BG is negated. This is the reason for timing 250. Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other 56300 components which are potential masters on the same bus. If BG input is asserted before that time, a situation of BG asserted, and BB negated, may cause another 56300 component to assume mastership at the same time. Therefore some non-overlap period between one BG input active to another BG input active is required. Timing 251 ensures that such a situation is avoided.
3.11
PARALLEL HOST INTERFACE (HDI08) TIMING
Table 3-15 Host Interface (HDI08) Timing
150 MHz
No.
Characteristics
4
3
Expression Min Max
--
Unit
317
Read data strobe assertion width HACK read assertion width
TC + 9.9
16.7
ns
318
Read data strobe deassertion width HACK read deassertion width
4
--
9.9
--
ns
3-36
DSP56367
MOTOROLA
Specifications Parallel Host Interface (HDI08) Timing
Table 3-15 Host Interface (HDI08) Timing (Continued)
150 MHz No. Characteristics3
4
Expression Min Max
--
Unit
319
Read data strobe deassertion width after "Last Data Register"
2.5 x TC + 6.6
23.3
ns
5,6 reads , or between two consecutive CVR, ICR, or ISR
reads
7 5,6
-- 13.2 -- ns
HACK deassertion width after "Last Data Register" reads 320 Write data strobe assertion width HACK write assertion width
8
321
Write data strobe deassertion width8 HACK write deassertion width 5 * after ICR, CVR and "Last Data Register" writes * * * after IVR writes, or after TXH:TXM writes (with HBE=0), or after TXL:TXM writes (with HBE=1)
2.5 x TC + 6.6
23.3
--
ns
16.5
--
322 323 324
HAS assertion width HAS deassertion to data strobe assertion
--
9.9 0.0 9.9
-- -- --
ns ns ns
9 8
-- --
Host data input setup time before write data strobe deassertion Host data input setup time before HACK write deassertion Host data input hold time after write data strobe deassertion Host data input hold time after HACK write deassertion Read data strobe assertion to output data active from high impedance HACK read assertion to output data active from high impedance
325
8
--
3.3
--
ns
326
4
--
3.3
--
ns
327
Read data strobe assertion to output data valid HACK read assertion to output data valid
4
--
--
24.2
ns
328
Read data strobe deassertion to output data high impedance HACK read deassertion to output data high impedance Output data hold time after read data strobe deassertion Output data hold time after HACK read deassertion HCS assertion to read data strobe deassertion
4
--
--
9.9
ns
329
4
--
3.3
--
ns
330 331 332 333
4 8
TC +9.9 -- --
16.7 9.9 -- 0.0
-- -- 19.1 --
ns ns ns ns
HCS assertion to write data strobe deassertion HCS assertion to output data valid HCS hold time after data strobe deassertion
9
--
MOTOROLA
DSP56367
3-37
Specifications Parallel Host Interface (HDI08) Timing
Table 3-15 Host Interface (HDI08) Timing (Continued)
150 MHz No. Characteristics3
Address (AD7-AD0) setup time before HAS deassertion (HMUX=1) Address (AD7-AD0) hold time after HAS deassertion (HMUX=1) A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W setup time before data strobe assertion * Read * 337 Write --
Expression Min Max
--
Unit
334
--
4.7
ns
335
--
3.3
--
ns
336
9
--
0
--
ns
4.7 3.3
-- -- ns
A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W hold time after data strobe deassertion
9
TC
338
Delay from read data strobe deassertion to host request assertion for "Last Data Register" read
4, 5, 10
2 x TC
6.7
--
ns
339
Delay from write data strobe deassertion to host request assertion for "Last Data Register" write
5, 8, 10
--
13.4
--
ns
340
Delay from data strobe assertion to host request deassertion for "Last Data Register" read or write (HROD = 0)
5, 9, 10
--
19.1
ns
341
Delay from data strobe assertion to host request deassertion for "Last Data Register" read or write (HROD = 1, open drain Host Request)
--
--
300.0
ns
5, 9, 10, 11
ns 2 x TC + 19.1 1.5 x TC + 19.1 32.5 29.2 0.0 -- -- -- -- -- 20.2 ns
342
Delay from DMA HACK deassertion to HOREQ assertion * * * For "Last Data Register" read
5 5
For "Last Data Register" write For other cases
343
Delay from DMA HACK assertion to HOREQ deassertion 5 * HROD = 0 Delay from DMA HACK assertion to HOREQ deassertion for "Last Data Register" read or write 5, 11 * HROD = 1, open drain Host Request
344
--
--
300.0
ns
3-38
DSP56367
MOTOROLA
Specifications Parallel Host Interface (HDI08) Timing
Table 3-15 Host Interface (HDI08) Timing (Continued)
150 MHz No. Characteristics3
1. 2. 3. 4. 5. 6.
Expression Min Max
Unit
Note:
7. 8. 9. 10. 11.
See Host Port Usage Considerations in the DSP56367 User's Manual. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. VCC = 1.8 V 5%; TJ = -40C to +95C, CL = 50 pF The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode. The "last data register" is the register at address $7, which is the last location to be read or written in data transfers. This timing is applicable only if a read from the "last data register" is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal. This timing is applicable only if two consecutive reads from one of these registers are executed. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode. The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single data strobe mode. The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode. In this calculation, the host request signal is pulled up by a 4.7 k resistor in the open-drain mode.
317 HACK 327 326 HD7-HD0 329 328
318
HOREQ
AA1105
Figure 3-20 Host Interrupt Vector Register (IVR) Read Timing Diagram
MOTOROLA
DSP56367
3-39
Specifications Parallel Host Interface (HDI08) Timing
HA0-HA2 336 330 HCS 337 333
317 HRD, HDS 318 328 332 327 326 HD0-HD7 340 341 HOREQ, HRRQ, HTRQ 338 319 329
AA0484
Figure 3-21 Read Timing Diagram, Non-Multiplexed Bus
3-40
DSP56367
MOTOROLA
Specifications Parallel Host Interface (HDI08) Timing
HA0-HA2 336 337 331 333 HCS
320 HWR, HDS 321 324 325 HD0-HD7 340 341 HOREQ, HRRQ, HTRQ
AA0485
339
Figure 3-22 Write Timing Diagram, Non-Multiplexed Bus
MOTOROLA
DSP56367
3-41
Specifications Parallel Host Interface (HDI08) Timing
HA8-HA10 322 HAS 336 337
323 317
HRD, HDS 334 335 327 328 329 HAD0-HAD7 Address 326 340 341 HOREQ, HRRQ, HTRQ
AA0486
318 319
Data
338
Figure 3-23 Read Timing Diagram, Multiplexed Bus
3-42
DSP56367
MOTOROLA
Specifications Parallel Host Interface (HDI08) Timing
HA8-HA10 322 HAS 336
323 320
HWR, HDS 334 335 HAD0-HAD7 Address Data 340 341 HOREQ, HRRQ, HTRQ
AA0487
324
321 325
339
Figure 3-24 Write Timing Diagram, Multiplexed Bus
MOTOROLA
DSP56367
3-43
Specifications Parallel Host Interface (HDI08) Timing
HOREQ (Output) 343 344 320 HACK (Input) TXH/M/L Write 324 325 H0-H7 (Input) Data Valid 342
321
Figure 3-25 Host DMA Write Timing Diagram
HOREQ (Output)
343 342
342 317 318
HACK (Input) 327 326 H0-H7 (Output)
RXH Read
328 329
Data Valid
Figure 3-26 Host DMA Read Timing Diagram
3-44
DSP56367
MOTOROLA
Specifications Serial Host Interface SPI Protocol Timing
3.12
SERIAL HOST INTERFACE SPI PROTOCOL TIMING
Table 3-16 Serial Host Interface SPI Protocol Timing
No. 140
Characteristics1 Tolerable spike width on clock or data in
Mode --
Filter Mode Bypassed Narrow Wide
Expression3 -- -- -- 6xTC+46 6xTC+152 6xTC+223 0.5xtSPICC -10 0.5xtSPICC -10 0.5xtSPICC -10 2.5xTC+12 2.5xTC+102 2.5xTC+189 0.5xtSPICC -10 0.5xtSPICC -10 0.5xtSPICC -10 2.5xTC+12 2.5xTC+102 2.5xTC+189 -- --
Min -- -- -- 86.2 192.2 263.2 38 91 126.5 28.8 118.8 205.8 38 91 126.5 28.8 118.8 205.8 -- --
Max 0 50 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 2000
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
141
Minimum serial clock cycle = tSPICC(min)
Master
Bypassed Narrow Wide
142
Serial clock high period
Master
Bypassed Narrow Wide
Slave
Bypassed Narrow Wide
143
Serial clock low period
Master
Bypassed Narrow Wide
Slave
Bypassed Narrow Wide
144
Serial clock rise/fall time
Master Slave
-- --
MOTOROLA
DSP56367
3-45
Specifications Serial Host Interface SPI Protocol Timing
Table 3-16 Serial Host Interface SPI Protocol Timing (Continued)
No. 146 Characteristics1 SS assertion to first SCK edge CPHA = 0 Mode Slave Filter Mode Bypassed Narrow Wide Expression3 3.5xTC+15 0 0 Min 38.5 0 0 Max -- -- -- Unit ns ns ns
CPHA = 1
Slave
Bypassed Narrow Wide
10 0 0 12 102 189 0 MAX{(20-TC), 0} MAX{(40-TC), 0} 2.5xTC+10 2.5xTC+30 2.5xTC+50 2 9 2xTC+33 2xTC+123 2xTC+210 TC+5 TC+55 TC+106 TC+33
10 0 0 12 102 189 0 13.3 33.3 26.8 46.8 66.8 2 -- -- -- -- 11.7 61.7 112.7 --
-- -- -- -- -- -- -- -- -- -- -- -- -- 9 46.4 136.4 223.4 -- -- -- 39.7
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
147
Last SCK edge to SS not asserted
Slave
Bypassed Narrow Wide
148
Data input valid to SCK edge (data input set-up time)
Master/ Slave
Bypassed Narrow Wide
149
SCK last sampling edge to data input not valid
Master/ Slave
Bypassed Narrow Wide
150 151 152
SS assertion to data out active SS deassertion to data high impedance2 SCK edge to data out valid (data out delay time)
Slave Slave Master/ Slave
-- -- Bypassed Narrow Wide
153
SCK edge to data out not valid (data out hold time)
Master/ Slave
Bypassed Narrow Wide
154
SS assertion to data out valid (CPHA = 0)
Slave
--
3-46
DSP56367
MOTOROLA
Specifications Serial Host Interface SPI Protocol Timing
Table 3-16 Serial Host Interface SPI Protocol Timing (Continued)
No. 157 Characteristics1 First SCK sampling edge to HREQ output deassertion Mode Slave Filter Mode Bypassed Narrow Wide 158 Last SCK sampling edge to HREQ output not deasserted (CPHA = 1) Slave Bypassed Narrow Wide 159 SS deassertion to HREQ output not deasserted (CPHA = 0) SS deassertion pulse width (CPHA = 0) HREQ in assertion to first SCK edge Slave -- Expression3 2.5xTC+30 2.5xTC+120 2.5xTC+217 2.5xTC+30 2.5xTC+80 2.5xTC+136 2.5xTC+30 Min -- -- -- 46.8 96.8 152.8 46.8 Max 46.8 136.8 233.8 -- -- -- -- Unit ns ns ns ns ns ns ns
160 161
Slave Master
-- Bypassed
TC+6 0.5 x tSPICC + 2.5xTC+43 0.5 xtSPICC + 2.5xTC+43 0.5 xtSPICC + 2.5xTC+43 0
12.7 97.8
-- --
ns ns
Narrow
160.8
--
ns
Wide
196.8
--
ns
162
HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) (CPHA = 1) First SCK edge to HREQ in not asserted (HREQ in hold time) 1. 2. 3.
Master
--
0
--
ns
163
Master
--
0
0
--
ns
Note:
VCC = 1.8 V 5%; TJ = -40C to +95C, CL = 50 pF Periodically sampled, not 100% tested The timing values calculated are based on simulation data at 150MHz. Tester restrictions limit SHI testing to lower clock frequencies.
MOTOROLA
DSP56367
3-47
Specifications Serial Host Interface SPI Protocol Timing
SS (Input) 143 142 CK (CPOL = 0) (Output) 142 143 CK (CPOL = 1) (Output) 148 149 MISO (Input)
MSB Valid
141 144 144
141 144 144
148
LSB Valid
149
152 MOSI (Output) 161 163 HREQ (Input) MSB
153 LSB
AA027
Figure 3-27 SPI Master Timing (CPHA = 0)
3-48
DSP56367
MOTOROLA
Specifications Serial Host Interface SPI Protocol Timing
SS (Input) 143 142 CK (CPOL = 0) (Output) 142 143 CK (CPOL = 1) (Output) 148 149 MISO (Input)
MSB Valid LSB Valid
141 144 144
141 144 144
148 149
152 MOSI (Output) 161 163 HREQ (Input) MSB 162
153 LSB
AA0272
Figure 3-28 SPI Master Timing (CPHA = 1)
MOTOROLA
DSP56367
3-49
Specifications Serial Host Interface SPI Protocol Timing
SS (Input) 143 142 SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 154 150 MISO (Output) 148 149 MOSI (Input) HREQ (Output)
AA027 MSB Valid LSB Valid
141 144 144 160
147
142 143
141 144 144
152 153 MSB
153
151 LSB 148 149
157
159
Figure 3-29 SPI Slave Timing (CPHA = 0)
3-50
DSP56367
MOTOROLA
Specifications Serial Host Interface (SHI) I2C Protocol Timing
SS (Input) 143 142 SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 152 150 MISO (Output) 148 149 MOSI (Input) HREQ (Output)
AA027 MSB Valid LSB Valid
141 144 144
147
142 143
144 144
152 MSB
153
151 LSB 148 149
157
158
Figure 3-30 SPI Slave Timing (CPHA = 1)
3.13
SERIAL HOST INTERFACE (SHI) I2C PROTOCOL TIMING
Table 3-17 SHI I2C Protocol Timing
Standard I2C* No. Characteristics1,2,3 Tolerable spike width on SCL or SDA Filters bypassed Narrow filters enabled Wide filters enabled 171 SCL clock frequency FSCL Symbol/ Expression -- -- -- -- -- 0 50 100 100 -- -- -- -- 0 50 100 400 ns ns ns kHz Standard4,6 Min Max Fast-Mode55,6 Min Max Unit
MOTOROLA
DSP56367
3-51
Specifications Serial Host Interface (SHI) I2C Protocol Timing
Table 3-17 SHI I2C Protocol Timing (Continued)
Standard I2C* No. 171 172 173 174 175 176 177 178 179 180 181 Characteristics1,2,3 SCL clock cycle Bus free time Start condition set-up time Start condition hold time SCL low period SCL high period SCL and SDA rise time SCL and SDA fall time Data set-up time Data hold time DSP clock frequency * * * 182 183 184 186 Filters bypassed Narrow filters enabled Wide filters enabled SCL low to data out valid Stop condition setup time HREQ in deassertion to last SCL edge (HREQ in set-up time) First SCL sampling edge to HREQ output deassertion * * * 187 TVD;DAT TSU;STO tSU;RQI TNG;RQO 2 x TC + 30 2 x TC + 120 2 x TC + 208 -- -- -- 50 140 228 -- -- -- 50 140 228 ns ns ns Symbol/ Expression TSCL TBUF TSU;STA THD;STA TLOW THIGH TR TF TSU;DAT THD;DAT FDSP 10.6 11.8 13.1 -- 4.0 0.0 -- -- -- 3.4 -- -- 28.5 39.7 61.0 -- 0.6 0.0 -- -- -- 0.9 -- -- MHz MHz MHz s s ns Standard4,6 Min 10 4.7 4.7 4.0 4.7 4.0 -- -- 250 0.0 Max -- -- -- -- -- -- 1000 300 -- -- Fast-Mode55,6 Min 2.5 1.3 0.6 0.6 1.3 1.3 20 + 0.1 x Cb 20 + 0.1 x Cb 100 0.0 Max -- -- -- -- -- -- 300 300 -- 0.9 s s s s s s ns ns ns s Unit
2
Filters bypassed Narrow filters enabled Wide filters enabled
Last SCL edge to HREQ output not deasserted * * * Filters bypassed Narrow filters enabled Wide filters enabled
2
TAS;RQO 2 x TC + 30 2 x TC + 80 2 x TC + 135 0.5 x TI2CCP 0.5 x TC - 21 tHO;RQI TAS;RQI 50 100 155 -- -- -- 50 100 155 -- -- -- ns ns ns
188
HREQ in assertion to first SCL edge * * * Filters bypassed Narrow filters enabled Wide filters enabled
4327 4282 4238 0.0
-- -- -- --
927 882 838 0.0
-- -- -- --
ns ns ns ns
187 Note:
First SCL edge to HREQ in not asserted (HREQ in hold time.) 1. 2. 3. 4. 5. 6.
VCC = 1.8 V 5%; TJ = -40C to +95C, CL = 50 pF Pull-up resistor: R P (min) = 1.5 kOhm Capacitive load: C b (max) = 400 pF It is recommended to enable the wide filters when operating in the I 2 C Standard Mode. It is recommended to enable the narrow filters when operating in the I 2 C Fast Mode. The timing values are derived from frequencies not exceeding 100 MHz.
3-52
DSP56367
MOTOROLA
Specifications Serial Host Interface (SHI) I2C Protocol Timing
3.13.1
PROGRAMMING THE SERIAL CLOCK
2
The programmed serial clock cycle, T I CCP , is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock control register). The expression for T I CCP is
2
T I2CCP = [TC x 2 x (HDM[7:0] + 1) x (7 x (1 - HRS) + 1)]
where - HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed. HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be selected.
-
In I2C mode, the user may select a value for the programmed serial clock cycle from
6 x TC (if HDM[7:0] = $02 and HRS = 1)
to
4096 x TC (if HDM[7:0] = $FF and HRS = 0)
2
The programmed serial clock cycle (TI CCP ), SCL rise time (TR), and the filters selected should be chosen in order to achieve the desired SCL serial clock cycle (TSCL), as shown in Table 3-18. Table 3-18 SCL Serial Clock Cycle (TSCL) Generated as Master
Filters bypassed Narrow filters enabled Wide filters enabled
TI2CCP + 2.5 x TC + 45ns + TR TI2CCP + 2.5 x TC + 135ns + TR TI2CCP + 2.5 x TC + 223ns + TR
EXAMPLE: For DSP clock frequency of 100 MHz (i.e. TC = 10ns), operating in a standard mode I2C environment (FSCL = 100 kHz (i.e. TSCL = 10s), TR = 1000ns), with wide filters enabled:
TI2CCP = 10s - 2.5x10ns - 223ns - 1000ns = 8752ns
MOTOROLA
DSP56367
3-53
Specifications Serial Host Interface (SHI) I2C Protocol Timing
Choosing HRS = 0 gives
HDM[7:0] = 8752ns / (2 x 10ns x 8) - 1 = 53.7
Thus the HDM[7:0] value should be programmed to $36 (=54). The resulting TI CCP will be:
2
T I2CCP = [TC x 2 x (HDM[7:0] + 1) x (7 x (1 - 0) + 1)] T I2CCP = [10ns x 2 x (54 + 1) x (7 x (1 - 0) + 1)] T I2CCP = [10ns x 2 x 54 x 8] = 8640ns
171 173 SCL 177 172 SDA
Stop
176
175
178 179
180
Start
MSB
LSB
ACK
Stop
174 189 188
HREQ
186 184
182
183 187
AA027
Figure 3-31 I2C Timing
3-54
DSP56367
MOTOROLA
Specifications Enhanced Serial Audio Interface Timing
3.14
ENHANCED SERIAL AUDIO INTERFACE TIMING
Table 3-19 Enhanced Serial Audio Interface Timing
No. 430
Characteristics1, 2, 3 Clock cycle5
Symbol tSSICC
Expression3 4 x TC 3 x TC TXC:max[3*tc; t454]
Min 26.8 20.1 26.5
Max -- -- --
Condition4 i ck x ck x ck
Unit ns
431
Clock high period * For internal clock * For external clock
--
2 x TC - 10.0 1.5 x TC
3.4
--
ns
10.0 3.4
-- -- ns
432
Clock low period * For internal clock * For external clock
--
2 x TC - 10.0 1.5 x TC
10.0 -- -- -- -- -- -- -- -- -- -- -- -- 0.0 19.0 5.0 3.0 23.0 1.0 23.0 1.0 3.0 0.0
-- 37.0 22.0 37.0 22.0 39.0 24.0 39.0 24.0 36.0 21.0 37.0 22.0 -- -- -- -- -- -- -- -- -- -- x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a ns
433
RXC rising edge to FSR out (bl) high
--
--
434
RXC rising edge to FSR out (bl) low
--
--
ns
435
RXC rising edge to FSR out (wr) high6
--
--
ns
436
RXC rising edge to FSR out (wr) low6
--
--
ns
437
RXC rising edge to FSR out (wl) high
--
--
ns
438
RXC rising edge to FSR out (wl) low
--
--
ns
439
Data in setup time before RXC (SCK in synchronous mode) falling edge Data in hold time after RXC falling edge FSR input (bl, wr) high before RXC falling edge 6
--
--
ns
440
--
--
ns
441
--
--
ns
442
FSR input (wl) high before RXC falling edge FSR input hold time after RXC falling edge
--
--
ns
443
--
--
ns
MOTOROLA
DSP56367
3-55
Specifications Enhanced Serial Audio Interface Timing
Table 3-19 Enhanced Serial Audio Interface Timing (Continued)
No. 444 Characteristics1, 2, 3 Flags input setup before RXC falling edge Flags input hold time after RXC falling edge TXC rising edge to FST out (bl) high Symbol Expression3 -- Min 0.0 19.0 6.0 0.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.0 21.0 -- Max -- -- -- -- 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 26.5 21.0 31.0 16.0 34.0 20.0 -- -- 27.0 Condition4 x ck i ck s x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck -- Unit ns
--
--
445
--
ns
446
--
--
ns
447
TXC rising edge to FST out (bl) low
--
--
ns
448
TXC rising edge to FST out (wr) high6
--
--
ns
449
TXC rising edge to FST out (wr) low6
--
--
ns
450
TXC rising edge to FST out (wl) high
--
--
ns
451
TXC rising edge to FST out (wl) low
--
--
ns
452
TXC rising edge to data out enable from high impedance TXC rising edge to transmitter #0 drive enable assertion TXC rising edge to data out valid
--
--
ns
453
--
--
ns
454
--
23 + 0.5 x TC 21.0
ns
455
TXC rising edge to data out high impedance7
--
--
ns
456
TXC rising edge to transmitter #0 drive enable deassertion7
--
--
ns
457
FST input (bl, wr) setup time before TXC falling edge6
--
--
ns
458
FST input (wl) to data out enable from high impedance FST input (wl) to transmitter #0 drive enable assertion FST input (wl) setup time before TXC falling edge FST input hold time after TXC falling edge
--
--
--
ns
459
--
--
31.0
--
ns
460
--
--
2.0 21.0 4.0 0.0
-- -- -- --
x ck i ck x ck i ck
ns
461
--
--
ns
3-56
DSP56367
MOTOROLA
Specifications Enhanced Serial Audio Interface Timing
Table 3-19 Enhanced Serial Audio Interface Timing (Continued)
No. 462 Characteristics1, 2, 3 Flag output valid after TXC rising edge Symbol -- Expression3 -- Min -- -- 40.0 -- -- Max 32.0 18.0 -- 27.5 27.5 Condition4 x ck i ck Unit ns
463 464 465 Note:
HCKR/HCKT clock cycle HCKT input rising edge to TXC output HCKR input rising edge to RXC output 1. 2.
-- -- --
-- -- --
ns ns ns
3.
4.
5. 6.
7. 8. 9.
VCC = 1.8 V 5%; TJ = -40C to +95C, CL = 50 pF i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that TXC and RXC are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that TXC and RXC are the same clock) bl = bit length wl = word length wr = word length relative TXC(SCKT pin) = transmit clock RXC(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. Periodically sampled and not 100% tested The timing values calculated are based on simulation data at 150MHz. Tester restrictions limit ESAI testing to lower clock frequencies. ESAI_1 specs match those of ESAI_0.
MOTOROLA
DSP56367
3-57
Specifications Enhanced Serial Audio Interface Timing
430 TXC (Input/Output ) 431 432
446 FST (Bit) Out
447
450
451
FST (Word) Out
454 452
454 455
First Bit Last Bit
Data Out
459
Transmitter #0 Drive Enable
457 461
453
456
FST (Bit) In 458 460 FST (Word) In 461
462
See Note
Flags Out Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. AA0490
Figure 3-32 ESAI Transmitter Timing
3-58
DSP56367
MOTOROLA
Specifications Enhanced Serial Audio Interface Timing
430 431 RXC (Input/Output) 433 FSR (Bit) Out 437 FSR (Word) Out 440 439 Data In 441 FSR (Bit) In 442 FSR (Word) In 444 Flags In
AA0491
432 434
438
First Bit 443
Last Bit
443
445
Figure 3-33 ESAI Receiver Timing
MOTOROLA
DSP56367
3-59
Specifications Enhanced Serial Audio Interface Timing
HCKT 463 464
SCKT(output)
Figure 3-34 ESAI HCKT Timing
HCKR 463 465
SCKR (output)
Figure 3-35 ESAI HCKR Timing
3-60
DSP56367
MOTOROLA
Specifications Digital Audio Transmitter Timing
3.15
DIGITAL AUDIO TRANSMITTER TIMING
Table 3-20 Digital Audio Transmitter Timing
150 MHz No. Characteristic Expression Min
ACI frequency (see note) ACI period ACI high duration ACI low duration ACI rising edge to ADO valid 1 / (2 x TC) 2 x TC 0.5 x TC 0.5 x TC 1.5 x TC -- 13.4 3.4 3.4 --
Unit Max
75 -- -- -- 10.0 MHz ns ns ns ns
220 221 222 223
Note:
In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the DSP56367 internal clock frequency. For example, if the DSP56367 is running at 150 MHz internally, the ACI frequency should be less than 75 MHz.
ACI 220 223 ADO
AA1280
221
222
Figure 3-36 Digital Audio Transmitter Timing
MOTOROLA
DSP56367
3-61
Specifications Timer Timing
3.16
TIMER TIMING
Table 3-21 Timer Timing
150 MHz No . Characteristics Expression Mi n
15.4 15.4
Ma x
-- --
Uni t
480 481
TIO Low TIO High
2 x TC + 2.0 2 x TC + 2.0
ns ns
Note:
VCC = 1.8 V 0.09 V; TJ = -40C to +95C, CL = 50 pF
TIO 480 481
AA0492
Figure 3-37 TIO Timer Event Input Restrictions
3-62
DSP56367
MOTOROLA
Specifications GPIO Timing
3.17
GPIO TIMING
Table 3-22 GPIO Timing
No.
Characteristics1 EXTAL edge to GPIO out valid (GPIO out delay time) EXTAL edge to GPIO out not valid (GPIO out hold time) GPIO In valid to EXTAL edge (GPIO in set-up time) EXTAL edge to GPIO in not valid (GPIO in hold time) Fetch to EXTAL edge before GPIO change GPIO out rise time GPIO out fall time 1. 2. VCC = 1.8 V 0.09 V; TJ = -40C to +95C, CL = 50 pF Valid only when PLL enabled with multiplication factor equal to one.
Expression
Min
Max
Uni t ns ns ns ns ns ns ns
4902 491 492 493 4942 495 496 Note:
-- 4.8 10.2 1.8 6.75 x TC-1.8 -- -- 43.4 -- --
32.8 -- -- -- -- 13 13
EXTAL (Input) 490 491 GPIO (Output) 492 GPIO (Input) Valid 493
A0-A17 494 Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register. GPIO (Output) 495 496
Figure 3-38 GPIO Timing
MOTOROLA
DSP56367
3-63
Specifications JTAG Timing
3.18
JTAG TIMING
Table 3-23 JTAG Timing
All frequencies
No.
Characteristics Min Max 22.0 -- -- 3.0 -- -- 40.0 40.0 -- -- 44.0 44.0
Unit
500 501 502 503 504 505 506 507 508 509 510 511 Note:
TCK frequency of operation (1/(TC x 3); maximum 22 MHz) TCK cycle time in Crystal mode TCK clock pulse width measured at 1.5 V TCK rise and fall times Boundary scan input data setup time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance 1. 2.
0.0 45.0 20.0 0.0 5.0 24.0 0.0 0.0 5.0 25.0 0.0 0.0
MHz ns ns ns ns ns ns ns ns ns ns ns
VCC = 1.8 V 0.09 V; TJ = -40C to +95C, CL = 50 pF All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
501 502 TCK (Input)
VIH VM VIL
502
VM
503
503
AA0496
Figure 3-39 Test Clock Input Timing Diagram
3-64
DSP56367
MOTOROLA
Specifications JTAG Timing
TCK (Input)
VIL 504
VIH 505
Data Inputs 506 Data Outputs 507 Data Outputs 506 Data Outputs
Input Data Valid
Output Data Valid
Output Data Valid
AA0497
Figure 3-40 Boundary Scan (JTAG) Timing Diagram
TCK (Input) TDI TMS (Input)
VIH VIL 508 509
Input Data Valid 510
TDO (Output) 511 TDO (Output) 510 TDO (Output)
Output Data Valid
Output Data Valid
AA0498
Figure 3-41 Test Access Port Timing Diagram
MOTOROLA
DSP56367
3-65
Specifications JTAG Timing
3-66
DSP56367
MOTOROLA
SECTION
4
DESIGN CONSIDERATIONS
4.1 THERMAL DESIGN CONSIDERATIONS
An estimation of the chip junction temperature, TJ, in C can be obtained from the following equation:
T J = TA + ( P D x R JA )
Where:
TA = ambient temperature C RqJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package W
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance.
R JA = R JC + RCA
Where:
RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W
RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate.
MOTOROLA
DSP56367
4-1
Design Considerations Thermal Design Considerations
A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages. * To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ - TT)/PD.
*
*
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, thermal characterization parameter or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
4-2
DSP56367
MOTOROLA
Design Considerations Electrical Design Considerations
4.2
ELECTRICAL DESIGN CONSIDERATIONS
CAUTION
This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). The suggested value for a pullup or pulldown resistor is 10 k ohm.
Use the following list of recommendations to assure correct DSP operation: * * * * * Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the board ground to each GND pin. Use at least six 0.01-0.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 1.2 cm (0.5 inch) per capacitor lead. Use at least a four-layer PCB with two inner layers for VCC and GND. Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQD, and TA pins. Maximum PCB trace lengths on the order of 15 cm (6 inches) are recommended. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for the three pins with internal pull-up resistors (TMS, TDI, TCK). Take special care to minimize noise levels on the VCCP and GNDP pins. If multiple DSP56367 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices.
*
* * *
MOTOROLA
DSP56367
4-3
Design Considerations Power Consumption Considerations
* *
RESET must be asserted when the chip is powered up. A stable EXTAL signal must be supplied before deassertion of RESET. At power-up, ensure that the voltage difference between the 3.3 V tolerant pins and the chip VCC never exceeds a TBD voltage.
4.3
POWER CONSUMPTION CONSIDERATIONS
Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by the following formula:
I = CxVxf
where
C = node/pin capacitance V = voltage swing f = frequency of node/pin toggle
Example 4-1 Current Consumption
For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 100 MHz clock, toggling at its maximum possible rate (50 MHz), the current consumption is
I = 50 x 10
- 12
x 3.3 x 50 x 10 = 8.25mA
6
The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. The typical internal current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. For applications that require very low current consumption, do the following: * * * Set the EBD bit when not accessing external memory. Minimize external memory accesses and use internal memory accesses. Minimize the number of pins that are switching.
4-4
DSP56367
MOTOROLA
Design Considerations PLL Performance Issues
* * *
Minimize the capacitive load on the pins. Connect the unused inputs to pull-up or pull-down resistors. Disable unused peripherals.
One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). A benchmark power consumption test algorithm is listed in Appendix E on page E-1. Use the test algorithm, specific test current measurements, and the following equation to derive the current per MIPS value.
I MIPS = I MHz = ( I typF2 - I typF1 ) ( F2 - F1 )
where :
ItypF2 ItypF1 F2 F1
= = = =
current at F2 current at F1 high frequency (any specified operating frequency) low frequency (any specified operating frequency lower than
F2)
Note:
F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application.
4.4
PLL PERFORMANCE ISSUES
The following explanations should be considered as general observations on expected PLL behavior. There is no testing that verifies these exact numbers. These observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges.
4.4.1
INPUT (EXTAL) JITTER REQUIREMENTS
The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be 2%. The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values.
MOTOROLA
DSP56367
4-5
Design Considerations PLL Performance Issues
4-6
DSP56367
MOTOROLA
SECTION
5
MEMORY CONFIGURATION
5.1 DATA AND PROGRAM MEMORY MAPS
The on-chip memory configuration of the DSP56367 is affected by the state of the CE (Cache Enable), MSW0, MSW1, and MS (Memory Switch) control bits in the OMR register, and by the SC bit in the Status Register. The internal data and program memory configurations are shown in Table 5-1. The address ranges for the internal memory are shown in Table 5-2 and Table 5-3. The memory maps for each memory configuration are shown in Figure 5-1 to Figure 5-16.
MOTOROLA
DSP56367
5-1
Memory Configuration Data and Program Memory Maps
Table 5-1 Internal Memory Configurations
Bit Settings MS W1 X X 0 0 1 0 0 1 X X 0 0 1 0 0 1 MS W0 X X 0 1 0 0 1 0 X X 0 1 0 0 1 0 Prog RAM 3K 2K 10K 8K 5K 9K 7K 4K 3K 2K 10K 8K 5K 9K 7K 4K Prog Cache n.a. 1K n.a. n.a. n.a. 1K 1K 1K n.a. 1K n.a. n.a. n.a. 1K 1K 1K Prog ROM 40K 40K 40K 40K 40K 40K 40K 40K n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. Memory Sizes (24-bit words) Boot ROM 192 192 192 192 192 192 192 192 n.a. n.a. n.a. n.a. n.a. n.a. n.a. n.a. X Data RAM 13K 13K 8K 8K 11K 8K 8K 11K 13K 13K 8K 8K 11K 8K 8K 11K Y Data RAM 7K 7K 5K 7K 7K 5K 7K 7K 7K 7K 5K 7K 7K 5K 7K 7K X Data ROM 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Y Data ROM 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K
CE
MS
SC
0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1
0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Table 5-2 On-chip RAM Memory Locations
Bit Settings Prog. RAM $0000 - $0BFF $0000 - $07FF $0000 -$27FF $0000 - $1BFF and $2400 - $27FF RAM Memory Locations Prog. Cache n.a. enabled n.a. n.a. X Data RAM $0000 - $33FF $0000 - $33FF $0000 - $1FFF $0000 - $1FFF Y Data RAM $0000-$1BFF $0000-$1BFF $0000 - $13FF $0000-$1BFF
MSW1
MSW0
CE
MS
SC
X X 0 0
X X 0 1
0 1 0 0
0 0 1 1
X X X X
5-2
DSP56367
MOTOROLA
Memory Configuration Data and Program Memory Maps
Table 5-2 On-chip RAM Memory Locations
Bit Settings Prog. RAM $0000 - $ 0FFF and $2400 - $27FF $0000 - $23FF $0000 - $1BFF $0000 - $0FFF RAM Memory Locations Prog. Cache n.a. X Data RAM $0000 - $2BFF Y Data RAM $0000-$1BFF
MSW1
MSW0
CE
MS
SC
1
0
0
1
X
0 0 1
0 1 0
1 1 1
1 1 1
X X X
enabled enabled enabled
$0000 - $1FFF $0000 - $1FFF $0000 - $2BFF
$0000 - $13FF $0000 - $1BFF $0000 - $1BFF
Table 5-3 On-chip ROM Memory Locations
Bit Settings Prog. ROM $FF1000 $FFAFCF no access ROM Memory Locations Boot. ROM $FF0000 $FF00BF no access X Data ROM $004000$00BFFF $004000$00BFFF Y Data ROM $004000$005FFF $004000$005FFF
MSW1
MSW0
CE
MS
SC
X
X
X
X
0
X
X
X
X
1
MOTOROLA
DSP56367
5-3
Memory Configuration Data and Program Memory Maps
PROGRAM
$FFFFFF $FFB000 $FFAFCF $FF1000 $FF00C0 $FF0000 INTERNAL RESERVED 40K INTERNAL ROM INTERNAL RESERVED BOOT ROM $00C000 $FF0000 $FFFFFF $FFFF80 $FFF000
X DATA
INTERNAL I/O (128 words) EXTERNAL INTERNAL RESERVED $FFFFFF $FFFFB0 $FFFF80 $FFF000 $FF0000
Y DATA
EXTERNAL I/O (80 words) INTERNAL I/O (48 words) EXTERNAL INTERNAL RESERVED EXTERNAL $006000
EXTERNAL
32K INTERNAL ROM EXTERNAL $004000 $003400 $000C00 $000000 3K INTERNAL RAM $000000 13K INTERNAL RAM $000000 INT. RESERVED $004000 $001C00
8K INTERNAL ROM INT. RESERVED
7K INTERNAL RAM
Figure 5-1 Memory Maps for MSW=(X,X), CE=0, MS=0, SC=0
PROGRAM
$FFFFFF $FFB000 $FFAFCF INTERNAL RESERVED 40K INTERNAL ROM INTERNAL RESERVED BOOT ROM $00C000 $FF0000 $FFFFFF $FFFF80 $FFF000
X DATA
INTERNAL I/O (128 words) EXTERNAL INTERNAL RESERVED $FFFFFF $FFFFB0 $FFFF80 $FFF000 $FF0000
Y DATA
EXTERNAL I/O (80 words) INTERNAL I/O (48 words) EXTERNAL INTERNAL RESERVED EXTERNAL $006000
$FF1000 $FF00C0 $FF0000
EXTERNAL
32K INTERNAL ROM EXTERNAL $004000 $003400 $000800 $000000 2K INTERNAL RAM 1K I-CACHE ENABLED $000000 13K INTERNAL RAM $000000 INT. RESERVED $004000 $001C00
8K INTERNAL ROM INT. RESERVED
7K INTERNAL RAM
Figure 5-2 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=0
5-4
DSP56367
MOTOROLA
Memory Configuration Data and Program Memory Maps
PROGRAM
$FFFFFF $FFB000 $FFAFCF INTERNAL RESERVED 40K INTERNAL ROM INTERNAL RESERVED BOOT ROM $00C000 $FF0000 $FFFFFF $FFFF80 $FFF000
X DATA
INTERNAL I/O (128 words) EXTERNAL INTERNAL RESERVED $FFFFFF $FFFFB0 $FFFF80 $FFF000 $FF0000
Y DATA
EXTERNAL I/O (80 words) INTERNAL I/O (48 words) EXTERNAL INTERNAL RESERVED EXTERNAL $006000
$FF1000 $FF00C0 $FF0000
EXTERNAL
32K INTERNAL ROM EXTERNAL $004000 $002000 $002800 $000000 10K INTERNAL RAM $000000 8K INTERNAL RAM $000000 INT. RESERVED $004000 $001400
8K INTERNAL ROM INT. RESERVED
5K INTERNAL RAM
Figure 5-3 Memory Maps for MSW=(0,0), CE=0 MS=1, SC=0
PROGRAM
$FFFFFF $FFB000 $FFAFCF INTERNAL RESERVED 40K INTERNAL ROM INTERNAL RESERVED BOOT ROM $00C000 EXTERNAL $FF0000 $FFFFFF $FFFF80 $FFF000
X DATA
INTERNAL I/O (128 words) EXTERNAL INTERNAL RESERVED $FFFFFF $FFFFB0 $FFFF80 $FFF000 $FF0000
Y DATA
EXTERNAL I/O (80 words) INTERNAL I/O (48 words) EXTERNAL INTERNAL RESERVED EXTERNAL $006000
$FF1000 $FF00C0 $FF0000
EXTERNAL
32K INTERNAL ROM $004000 $004000 INT. RESERVED $001C00
8K INTERNAL ROM INT. RESERVED
$002800 $002400 $001C00 $000000
1K RAM INT. RESERVED 7K INTERNAL RAM
$002000
$000000
8K INTERNAL RAM
$000000
7K INTERNAL RAM
Figure 5-4 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=0
MOTOROLA
DSP56367
5-5
Memory Configuration Data and Program Memory Maps
PROGRAM
$FFFFFF $FFB000 $FFAFCF INTERNAL RESERVED 40K INTERNAL ROM INTERNAL RESERVED BOOT ROM $00C000 EXTERNAL $FF0000 $FFFFFF $FFFF80 $FFF000
X DATA
INTERNAL I/O (128 words) EXTERNAL INTERNAL RESERVED $FFFFFF $FFFFB0 $FFFF80 $FFF000 $FF0000
Y DATA
EXTERNAL I/O (80 words) INTERNAL I/O (48 words) EXTERNAL INTERNAL RESERVED EXTERNAL $006000
$FF1000 $FF00C0 $FF0000
EXTERNAL
32K INTERNAL ROM $004000 $004000 INT. RESERVED $001C00
8K INTERNAL ROM INT. RESERVED
$002800 $002400 $001000 $000000
1K RAM INT. RESERVED 4K INTERNAL RAM
$002C00
$000000
11K INTERNAL RAM
$000000
7K INTERNAL RAM
Figure 5-5 Memory Maps for MSW=(1,0), CE=0, MS=1, SC=0
PROGRAM
$FFFFFF $FFB000 $FFAFCF INTERNAL RESERVED 40K INTERNAL ROM INTERNAL RESERVED BOOT ROM $00C000 $FF0000 $FFFFFF $FFFF80 $FFF000
X DATA
INTERNAL I/O (128 words) EXTERNAL INTERNAL RESERVED $FFFFFF $FFFFB0 $FFFF80 $FFF000 $FF0000
Y DATA
EXTERNAL I/O (80 words) INTERNAL I/O (48 words) EXTERNAL INTERNAL RESERVED EXTERNAL $006000
$FF1000 $FF00C0 $FF0000
EXTERNAL
32K INTERNAL ROM EXTERNAL $004000 $002000 $002400 $000000 9K INTERNAL RAM 1K I-CACHE ENABLED $000000 8K INTERNAL RAM $000000 INT. RESERVED $004000 $001400
8K INTERNAL ROM INT. RESERVED
5K INTERNAL RAM
Figure 5-6 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=0
5-6
DSP56367
MOTOROLA
Memory Configuration Data and Program Memory Maps
PROGRAM
$FFFFFF $FFB000 $FFAFCF INTERNAL RESERVED 40K INTERNAL ROM INTERNAL RESERVED BOOT ROM $00C000 $FF0000 $FFFFFF $FFFF80 $FFF000
X DATA
INTERNAL I/O (128 words) EXTERNAL INTERNAL RESERVED $FFFFFF $FFFFB0 $FFFF80 $FFF000 $FF0000
Y DATA
EXTERNAL I/O (80 words) INTERNAL I/O (48 words) EXTERNAL INTERNAL RESERVED EXTERNAL $006000
$FF1000 $FF00C0 $FF0000
EXTERNAL
32K INTERNAL ROM EXTERNAL $002400 $001C00 $000000 INT. RESERVED 7K INTERNAL RAM 1K I-CACHE ENABLED 8K INTERNAL RAM $004000 $002000 INT. RESERVED $004000 $001C00
8K INTERNAL ROM INT. RESERVED
$000000
$000000
7K INTERNAL RAM
Figure 5-7 Memory Maps for MSW=(0,1), CE=1, MS=1, SC=0
PROGRAM
$FFFFFF $FFB000 $FFAFCF INTERNAL RESERVED 40K INTERNAL ROM INTERNAL RESERVED BOOT ROM $00C000 $FF0000 $FFFFFF $FFFF80 $FFF000
X DATA
INTERNAL I/O (128 words) EXTERNAL INTERNAL RESERVED $FFFFFF $FFFFB0 $FFFF80 $FFF000 $FF0000
Y DATA
EXTERNAL I/O (80 words) INTERNAL I/O (48 words) EXTERNAL INTERNAL RESERVED EXTERNAL $006000
$FF1000 $FF00C0 $FF0000
EXTERNAL
32K INTERNAL ROM EXTERNAL $002400 $001000 $000000 INT. RESERVED 4K INTERNAL RAM 1K I-CACHE ENABLED 11K INTERNAL RAM $004000 $002C00 INT. RESERVED $004000 $001C00
8K INTERNAL ROM INT. RESERVED
$000000
$000000
7K INTERNAL RAM
Figure 5-8 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=0
MOTOROLA
DSP56367
5-7
Memory Configuration Data and Program Memory Maps
PROGRAM
$FFFF $FFFF $FF80
X DATA
INTERNAL I/O (128 words) $FFFF $FFB0
Y DATA
EXTERNAL I/O (82 words) INTERNAL I/O (46 words) $FF80
EXTERNAL EXTERNAL $C000 32K INTERNAL ROM $4000 $3400 $0C00 $0000 3K INTERNAL RAM $0000 13K INTERNAL RAM $0000 $4000 INT. RESERVED $1C00 $6000
EXTERNAL
8K INTERNAL ROM INT. RESERVED
7K INTERNAL RAM
Figure 5-9 Memory Maps for MSW=(X,X), CE=0, MS=0, SC=1
PROGRAM
$FFFF $FFFF $FF80
X DATA
INTERNAL I/O (128 words) $FFFF $FFB0
Y DATA
EXTERNAL I/O (80 words) INTERNAL I/O (48words) $FF80
EXTERNAL EXTERNAL $C000 32K INTERNAL ROM $4000 $3400 $0800 $0000 2K INTERNAL RAM 1K I-CACHE ENABLED $0000 13K INTERNAL RAM $0000 $4000 INT. RESERVED $1C00 $6000
EXTERNAL
8K INTERNAL ROM INT. RESERVED
7K INTERNAL RAM
Figure 5-10 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=1
5-8
DSP56367
MOTOROLA
Memory Configuration Data and Program Memory Maps
PROGRAM
$FFFF $FFFF $FF80
X DATA
INTERNAL I/O (128 words) $FFFF $FFB0
Y DATA
EXTERNAL I/O (80 words) INTERNAL I/O (48words) $FF80
EXTERNAL EXTERNAL $C000 32K INTERNAL ROM $4000 $2000 $2800 $0000 10K INTERNAL RAM $0000 8K INTERNAL RAM $0000 INT. RESERVED $4000 $1400 $6000
EXTERNAL
8K INTERNAL ROM INT. RESERVED
5K INTERNAL RAM
Figure 5-11 Memory Maps for MSW=(0,0), CE=0, MS=1, SC=1
PROGRAM
$FFFF $FFFF $FF80
X DATA
INTERNAL I/O (128 words) $FFFF $FFB0
Y DATA
EXTERNAL I/O (80 words) INTERNAL I/O (48 words) $FF80
EXTERNAL EXTERNAL $C000 32K INTERNAL ROM $4000 $2800 $2400 $1C00 $0000 1K RAM INT. RESERVED 7K INTERNAL RAM $2000 INT. RESERVED $4000 $1C00 $6000
EXTERNAL
8K INTERNAL ROM INT. RESERVED
$0000
8K INTERNAL RAM
$0000
7K INTERNAL RAM
Figure 5-12 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=1
MOTOROLA
DSP56367
5-9
Memory Configuration Data and Program Memory Maps
PROGRAM
$FFFF $FFFF $FF80
X DATA
INTERNAL I/O (128 words) $FFFF $FFB0
Y DATA
EXTERNAL I/O (80 words) INTERNAL I/O (48 words) $FF80
EXTERNAL EXTERNAL $C000 32K INTERNAL ROM $4000 $2800 1K RAM $2400 $1000 $0000 INT. RESERVED 4K INTERNAL RAM 11K INTERNAL RAM $2C00 INT. RESERVED $4000 $1C00 $6000
EXTERNAL
8K INTERNAL ROM INT. RESERVED
$0000
$0000
7K INTERNAL RAM
Figure 5-13 Memory Maps for MSW=(1,0), CE=0, MS=1, SC=1
PROGRAM
$FFFF $FFFF $FF80
X DATA
INTERNAL I/O (128 words) $FFFF $FFB0
Y DATA
EXTERNAL I/O (80 words) INTERNAL I/O (48 words) $FF80
EXTERNAL EXTERNAL $C000 32K INTERNAL ROM $4000 $2000 $2400 $0000 9K INTERNAL RAM 1K I-CACHE ENABLED $0000 8K INTERNAL RAM $0000 INT. RESERVED $4000 $1400 $6000
EXTERNAL
8K INTERNAL ROM INT. RESERVED
5K INTERNAL RAM
Figure 5-14 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=1
5-10
DSP56367
MOTOROLA
Memory Configuration Data and Program Memory Maps
PROGRAM
$FFFF $FFFF $FF80
X DATA
INTERNAL I/O (128 words) $FFFF $FFB0
Y DATA
EXTERNAL I/O (80 words) INTERNAL I/O (48 words) $FF80
EXTERNAL EXTERNAL $C000 32K INTERNAL ROM $4000 $2000 $2400 $1C00 $0000 INT. RESERVED 7K INTERNAL RAM 1K I-CACHE ENABLED INT. RESERVED $4000 $1C00 $6000
EXTERNAL
8K INTERNAL ROM INT. RESERVED
$0000
8K INTERNAL RAM
$0000
7K INTERNAL RAM
Figure 5-15 Memory Maps for MSW=(0,1), CE=1, MS=1, SC=1
PROGRAM
$FFFF $FFFF $FF80
X DATA
INTERNAL I/O (128 words) $FFFF $FFB0
Y DATA
EXTERNAL I/O (80 words) INTERNAL I/O (48 words) $FF80
EXTERNAL EXTERNAL $C000 32K INTERNAL ROM $4000 $2C00 $2400 $1000 $0000 INT. RESERVED 4K INTERNAL RAM 1K I-CACHE ENABLED 11K INTERNAL RAM INT. RESERVED $4000 $1C00 $6000
EXTERNAL
8K INTERNAL ROM INT. RESERVED
$0000
$0000
7K INTERNAL RAM
Figure 5-16 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=1
MOTOROLA
DSP56367
5-11
Memory Configuration Data and Program Memory Maps
5.1.1
RESERVED MEMORY SPACES
The reserved memory spaces should not be accessed by the user. They are reserved for future expansion.
5.1.2
PROGRAM ROM AREA RESERVED FOR MOTOROLA USE
The last 48 words ($FFAFD0-$FFAFFF) of the Program ROM are reserved for Motorola use. This memory area is reserved for use as expansion area for the bootstrap ROM as well as for testing purposes. Customer code should not use this area. The contents of this Program ROM segment is defined by the Bootstrap ROM Contents on page Appendix A-1.
5.1.3
BOOTSTRAP ROM
The 192-word Bootstrap ROM occupies locations $FF0000-$FF00BF. The bootstrap ROM is factory-programmed to perform the bootstrap operation following hardware reset. The contents of the Bootstrap ROM are defined by the Bootstrap ROM source code in Bootstrap ROM Contents on page Appendix A-1.
5.1.4
DYNAMIC MEMORY CONFIGURATION SWITCHING
The internal memory configuration is altered by re-mapping RAM modules from Y and X data memory into program memory space and vice-versa. The contents of the switched RAM modules are preserved. The memory can be dynamically switched from one configuration to another by changing the MS, MSW0 or MSW1 bits in OMR. The address ranges that are directly affected by the switch operation are specified in Table 5-2. The memory switch can be accomplished provided that the affected address ranges are not being accessed during the instruction cycle in which the switch operation takes place. Accordingly, the following condition must be observed for trouble-free dynamic switching: Note: No accesses (including instruction fetches) to or from the affected address ranges in program and data memories are allowed during the switch cycle. The switch cycle actually occurs 3 instruction cycles after the instruction that modifies the MS, MSW0 or MSW1 bits.
Note:
5-12
DSP56367
MOTOROLA
Memory Configuration Data and Program Memory Maps
Any sequence that complies with the switch condition is valid. For example, if the program flow executes in the address range that is not affected by the switch, the switch condition can be met very easily. In this case a switch can be accomplished by just changing the MS, MSW0 or MSW1 bits in OMR in the regular program flow, assuming no accesses to the affected address ranges of the data memory occur up to 3 instructions after the instruction that changes the OMR bit. Special care should be taken in relation to the interrupt vector routines since an interrupt could cause the DSP to fetch instructions out of sequence and might violate the switch condition. Special attention should be given when running a memory switch routine using the OnCE port. Running the switch routine in Trace mode, for example, can cause the switch to complete after the MS bit change while the DSP is in Debug mode. As a result, subsequent instructions might be fetched according to the new memory configuration (after the switch), and thus might execute improperly.
5.1.5
EXTERNAL MEMORY SUPPORT
The DSP56367 does not support the SSRAM memory type. It does support SRAM and DRAM as indicated in the DSP56300 24-Bit Digital Signal Processor Family Manual, Motorola publication DSP56300FM/AD. Also, care should be taken when accessing external memory to ensure that the necessary address lines are available. For example, when using glueless SRAM interfacing, it is possible to directly address 3 x 218 memory locations (768k) when using the 18 address lines and the three programmable address attribute lines.
MOTOROLA
DSP56367
5-13
Memory Configuration Internal I/O Memory Map
5.2
INTERNAL I/O MEMORY MAP
The DSP56367 on-chip peripheral modules have their register files programmed to the addresses in the internal X-I/O memory range (the top 128 locations of the X data memory space) and internal Y-I/O memory range (48 locations of the Ydata memory space) as shown in Table 5-4. Table 5-4 Internal I/O Memory Map
Peripheral IPR PLL ONCE BIU Address X:$FFFFFF X:$FFFFFE X:$FFFFFD X:$FFFFFC X:$FFFFFB X:$FFFFFA X:$FFFFF9 X:$FFFFF8 X:$FFFFF7 X:$FFFFF6 X:$FFFFF5 DMA X:$FFFFF4 X:$FFFFF3 X:$FFFFF2 X:$FFFFF1 X:$FFFFF0 DMA0 X:$FFFFEF X:$FFFFEE X:$FFFFED X:$FFFFEC DMA1 X:$FFFFEB X:$FFFFEA X:$FFFFE9 X:$FFFFE8 DMA2 X:$FFFFE7 X:$FFFFE6 X:$FFFFE5 X:$FFFFE4 DMA3 X:$FFFFE3 X:$FFFFE2 X:$FFFFE1 X:$FFFFE0 DMA4 X:$FFFFDF X:$FFFFDE X:$FFFFDD X:$FFFFDC Register Name INTERRUPT PRIORITY REGISTER CORE (IPR-C) INTERRUPT PRIORITY REGISTER PERIPHERAL (IPR-P) PLL CONTROL REGISTER (PCTL) ONCE GDB REGISTER (OGDB) BUS CONTROL REGISTER (BCR) DRAM CONTROL REGISTER (DCR) ADDRESS ATTRIBUTE REGISTER 0 (AAR0) ADDRESS ATTRIBUTE REGISTER 1 (AAR1) ADDRESS ATTRIBUTE REGISTER 2 (AAR2) ADDRESS ATTRIBUTE REGISTER 3 (AAR3) [pin not available] ID REGISTER (IDR) DMA STATUS REGISTER (DSTR) DMA OFFSET REGISTER 0 (DOR0) DMA OFFSET REGISTER 1 (DOR1) DMA OFFSET REGISTER 2 (DOR2) DMA OFFSET REGISTER 3 (DOR3) DMA SOURCE ADDRESS REGISTER (DSR0) DMA DESTINATION ADDRESS REGISTER (DDR0) DMA COUNTER (DCO0) DMA CONTROL REGISTER (DCR0) DMA SOURCE ADDRESS REGISTER (DSR1) DMA DESTINATION ADDRESS REGISTER (DDR1) DMA COUNTER (DCO1) DMA CONTROL REGISTER (DCR1) DMA SOURCE ADDRESS REGISTER (DSR2) DMA DESTINATION ADDRESS REGISTER (DDR2) DMA COUNTER (DCO2) DMA CONTROL REGISTER (DCR2) DMA SOURCE ADDRESS REGISTER (DSR3) DMA DESTINATION ADDRESS REGISTER (DDR3) DMA COUNTER (DCO3) DMA CONTROL REGISTER (DCR3) DMA SOURCE ADDRESS REGISTER (DSR4) DMA DESTINATION ADDRESS REGISTER (DDR4) DMA COUNTER (DCO4) DMA CONTROL REGISTER (DCR4)
5-14
DSP56367
MOTOROLA
Memory Configuration Internal I/O Memory Map
Table 5-4 Internal I/O Memory Map (Continued)
Peripheral DMA5 Address X:$FFFFDB X:$FFFFDA X:$FFFFD9 X:$FFFFD8 PORT D X:$FFFFD7 X:$FFFFD6 X:$FFFFD5 DAX X:$FFFFD4 X:$FFFFD3 X:$FFFFD2 X:$FFFFD1 X:$FFFFD0 X:$FFFFCF X:$FFFFCE X:$FFFFCD X:$FFFFCC X:$FFFFCB X:$FFFFCA PORT B HDI08 X:$FFFFC9 X:$FFFFC8 X:$FFFFC7 X:$FFFFC6 X:$FFFFC5 X:$FFFFC4 X:$FFFFC3 X:$FFFFC2 X:$FFFFC1 X:$FFFFC0 PORT C X:$FFFFBF X:$FFFFBE X:$FFFFBD Register Name DMA SOURCE ADDRESS REGISTER (DSR5) DMA DESTINATION ADDRESS REGISTER (DDR5) DMA COUNTER (DCO5) DMA CONTROL REGISTER (DCR5) PORT D CONTROL REGISTER (PCRD) PORT D DIRECTION REGISTER (PRRD) PORT D DATA REGISTER (PDRD) DAX STATUS REGISTER (XSTR) DAX AUDIO DATA REGISTER B (XADRB) DAX AUDIO DATA REGISTER A (XADRA) DAX NON-AUDIO DATA REGISTER (XNADR) DAX CONTROL REGISTER (XCTR) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED HOST PORT GPIO DATA REGISTER (HDR) HOST PORT GPIO DIRECTION REGISTER (HDDR) HOST TRANSMIT REGISTER (HOTX) HOST RECEIVE REGISTER (HORX) HOST BASE ADDRESS REGISTER (HBAR) HOST PORT CONTROL REGISTER (HPCR) HOST STATUS REGISTER (HSR) HOST CONTROL REGISTER (HCR) RESERVED RESERVED PORT C CONTROL REGISTER (PCRC) PORT C DIRECTION REGISTER (PRRC) PORT C GPIO DATA REGISTER (PDRC)
MOTOROLA
DSP56367
5-15
Memory Configuration Internal I/O Memory Map
Table 5-4 Internal I/O Memory Map (Continued)
Peripheral ESAI Address X:$FFFFBC X:$FFFFBB X:$FFFFBA X:$FFFFB9 X:$FFFFB8 X:$FFFFB7 X:$FFFFB6 X:$FFFFB5 X:$FFFFB4 X:$FFFFB3 X:$FFFFB2 X:$FFFFB1 X:$FFFFB0 X:$FFFFAF X:$FFFFAE X:$FFFFAD X:$FFFFAC X:$FFFFAB X:$FFFFAA X:$FFFFA9 X:$FFFFA8 X:$FFFFA7 X:$FFFFA6 X:$FFFFA5 X:$FFFFA4 X:$FFFFA3 X:$FFFFA2 X:$FFFFA1 X:$FFFFA0 X:$FFFF9F X:$FFFF9E X:$FFFF9D X:$FFFF9C X:$FFFF9B X:$FFFF9A X:$FFFF99 X:$FFFF98 X:$FFFF97 X:$FFFF96 X:$FFFF95 SHI X:$FFFF94 X:$FFFF93 X:$FFFF92 X:$FFFF91 X:$FFFF90 Register Name ESAI RECEIVE SLOT MASK REGISTER B (RSMB) ESAI RECEIVE SLOT MASK REGISTER A (RSMA) ESAI TRANSMIT SLOT MASK REGISTER B (TSMB) ESAI TRANSMIT SLOT MASK REGISTER A (TSMA) ESAI RECEIVE CLOCK CONTROL REGISTER (RCCR) ESAI RECEIVE CONTROL REGISTER (RCR) ESAI TRANSMIT CLOCK CONTROL REGISTER (TCCR) ESAI TRANSMIT CONTROL REGISTER (TCR) ESAI COMMON CONTROL REGISTER (SAICR) ESAI STATUS REGISTER (SAISR) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ESAI RECEIVE DATA REGISTER 3 (RX3) ESAI RECEIVE DATA REGISTER 2 (RX2) ESAI RECEIVE DATA REGISTER 1 (RX1) ESAI RECEIVE DATA REGISTER 0 (RX0) RESERVED ESAI TIME SLOT REGISTER (TSR) ESAI TRANSMIT DATA REGISTER 5 (TX5) ESAI TRANSMIT DATA REGISTER 4 (TX4) ESAI TRANSMIT DATA REGISTER 3 (TX3) ESAI TRANSMIT DATA REGISTER 2 (TX2) ESAI TRANSMIT DATA REGISTER 1 (TX1) ESAI TRANSMIT DATA REGISTER 0 (TX0) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SHI RECEIVE FIFO (HRX) SHI TRANSMIT REGISTER (HTX) SHI I2C SLAVE ADDRESS REGISTER (HSAR) SHI CONTROL/STATUS REGISTER (HCSR) SHI CLOCK CONTROL REGISTER (HCKR)
5-16
DSP56367
MOTOROLA
Memory Configuration Internal I/O Memory Map
Table 5-4 Internal I/O Memory Map (Continued)
Peripheral TRIPLE TIMER Address X:$FFFF8F X:$FFFF8E X:$FFFF8D X:$FFFF8C X:$FFFF8B X:$FFFF8A X:$FFFF89 X:$FFFF88 X:$FFFF87 X:$FFFF86 X:$FFFF85 X:$FFFF84 X:$FFFF83 X:$FFFF82 X:$FFFF81 X:$FFFF80 ESAI MUX PIN CONTROL Y:$FFFFAF Y:$FFFFAE Y:$FFFFAD Y:$FFFFAC Y:$FFFFAB Y:$FFFFAA Y:$FFFFA9 Y:$FFFFA8 Y:$FFFFA7 Y:$FFFFA6 Y:$FFFFA5 Y:$FFFFA4 Y:$FFFFA3 Y:$FFFFA2 Y:$FFFFA1 Y:$FFFFA0 PORT E Y:$FFFF9F Y:$FFFF9E Y:$FFFF9D Register Name TIMER 0 CONTROL/STATUS REGISTER (TCSR0) TIMER 0 LOAD REGISTER (TLR0) TIMER 0 COMPARE REGISTER (TCPR0) TIMER 0 COUNT REGISTER (TCR0) TIMER 1 CONTROL/STATUS REGISTER (TCSR1) TIMER 1 LOAD REGISTER (TLR1) TIMER 1 COMPARE REGISTER (TCPR1) TIMER 1 COUNT REGISTER (TCR1) TIMER 2 CONTROL/STATUS REGISTER (TCSR2) TIMER 2 LOAD REGISTER (TLR2) TIMER 2 COMPARE REGISTER (TCPR2) TIMER 2 COUNT REGISTER (TCR2) TIMER PRESCALER LOAD REGISTER (TPLR) TIMER PRESCALER COUNT REGISTER (TPCR) RESERVED RESERVED MUX PIN CONTROL REGISTER (EMUXR) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED PORT E CONTROL REGISTER (PCRE) PORT E DIRECTION REGISTER(PPRE) PORT E GPIO DATA REGISTER(PDRE)
MOTOROLA
DSP56367
5-17
Memory Configuration Internal I/O Memory Map
Table 5-4 Internal I/O Memory Map (Continued)
Peripheral ESAI_1 Address Y:$FFFF9C Y:$FFFF9B Y:$FFFF9A Y:$FFFF99 Y:$FFFF98 Y:$FFFF97 Y:$FFFF96 Y:$FFFF95 Y:$FFFF94 Y:$FFFF93 Y:$FFFF92 Y:$FFFF91 Y:$FFFF90 Y:$FFFF8F Y:$FFFF8E Y:$FFFF8D Y:$FFFF8C Y:$FFFF8B Y:$FFFF8A Y:$FFFF89 Y:$FFFF88 Y:$FFFF87 Y:$FFFF86 Y:$FFFF85 Y:$FFFF84 Y:$FFFF83 Y:$FFFF82 Y:$FFFF81 Y:$FFFF80 Register Name ESAI_1 RECEIVE SLOT MASK REGISTER B (RSMB_1) ESAI_1 RECEIVE SLOT MASK REGISTER A (RSMA_1) ESAI_1 TRANSMIT SLOT MASK REGISTER B (TSMB_1) ESAI_1 TRANSMIT SLOT MASK REGISTER A (TSMA_1) ESAI_1 RECEIVE CLOCK CONTROL REGISTER (RCCR_1) ESAI_1 RECEIVE CONTROL REGISTER (RCR_1) ESAI_1 TRANSMIT CLOCK CONTROL REGISTER (TCCR_1) ESAI_1 TRANSMIT CONTROL REGISTER (TCR_1) ESAI_1 COMMON CONTROL REGISTER (SAICR_1) ESAI_1 STATUS REGISTER (SAISR_1) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ESAI_1 RECEIVE DATA REGISTER 3 (RX3_1) ESAI_1 RECEIVE DATA REGISTER 2 (RX2_1) ESAI_1 RECEIVE DATA REGISTER 1 (RX1_1) ESAI_1 RECEIVE DATA REGISTER 0 (RX0_1) RESERVED ESAI_1 TIME SLOT REGISTER (TSR_1) ESAI_1 TRANSMIT DATA REGISTER 5 (TX5_1) ESAI_1 TRANSMIT DATA REGISTER 4 (TX4_1) ESAI_1 TRANSMIT DATA REGISTER 3 (TX3_1) ESAI_1 TRANSMIT DATA REGISTER 2 (TX2_1) ESAI_1 TRANSMIT DATA REGISTER 1 (TX1_1) ESAI_1 TRANSMIT DATA REGISTER 0 (TX0_1)
5-18
DSP56367
MOTOROLA
SECTION
6
CORE CONFIGURATION
6.1 INTRODUCTION
This chapter contains DSP56300 core configuration information details specific to the DSP56367. These include the following: * * * * * * * * Operating modes Bootstrap program Interrupt sources and priorities DMA request sources OMR PLL control register AA control registers JTAG BSR
For more information on specific registers or modules in the DSP56300 core, refer to the DSP56300 Family Manual (DSP56300FM/AD).
MOTOROLA
DSP56367
6-1
Core Configuration Operating Mode Register (OMR)
6.2
OPERATING MODE REGISTER (OMR)
The contents of the Operating Mode Register (OMR) are shown in Table 6-1. Refer to the DSP56300 24-Bit Digital Signal Processor Family Manual, Motorola publication DSP56300FM/AD for a description of the OMR bits. Table 6-1 Operating Mode Register (OMR)
SCS 23 22 21 20 19 18 17 16 15 14 13 EOM 12 11 10 9 8 7 6 5 COM 4 3 2 1 0
PEN MSW 1: 0 SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CDP1:0 MS SD PEN MSW1 MSW0 SEN WRP EOV EUN XYS - Patch Enable - Memory switch mode 1 - Memory switch mode 0 - Stack Extension Enable - Extended Stack Wrap Flag - Extended Stack Overflow Flag - Extended Stack Underflow Flag - Stack Extension Space Select
EBD MD MC MB MA - Master memory Switch Mode - Stop Delay
ATE APD ABE BRT TAS
BE CDP1 CDP0
- Address Tracing Enable - Address Priority Disable - Asyn. Bus Arbitration Enable - Bus Release Timing - TA Synchronize Select - Burst Mode Enable - Core-Dma Priority 1 - Core-Dma Priority 0
MS SD
EBD MD MC MB MA
- External Bus Disable - Operating Mode D - Operating Mode C - Operating Mode B - Operating Mode A
- Reserved bit. Read as zero, should be written with zero for future compatibility
6.2.1
ASYNCHRONOUS BUS ARBITRATION ENABLE (ABE) BIT 13
The asynchronous bus arbitration mode is activated by setting the ABE bit in the OMR register. Hardware reset clears the ABE bit.
6.2.2
ADDRESS ATTRIBUTE PRIORITY DISABLE (APD) - BIT 14
The Address Attribute Priority Disable (APD) bit is used to turn off the address attribute priority mechanism. When this bit is set, more than one address attribute pin AA/RAS(2:0) may be simultaneously asserted according to its AAR settings. The APD bit is cleared by hardware reset.
6-2
DSP56367
MOTOROLA
Core Configuration Operating Mode Register (OMR)
6.2.3
ADDRESS TRACING ENABLE (ATE) - BIT 15
The Address Tracing Enable (ATE) bit is used to turn on Address Tracing (AT) Mode. When the AT Mode is enabled, the DSP56300 Core reflects the addresses of internal fetches and program space moves (MOVEM) to the Address Bus (A0-A17), if the Address Bus is not needed by the DSP56300 Core for external accesses. The ATE bit is cleared on hardware reset.
6.2.4
PATCH ENABLE (PEN) - BIT 23
The Patch Enable function is used for patching Program ROM locations. i.e. to replace during program execution, the contents of the Program ROM. This is done by using the Instruction Cache to supply the instruction word instead of the Program ROM. The Patch Enable function is activated by setting bit 23 (PEN) in the OMR Register. The PEN bit is cleared by hardware reset. The Instruction Cache should be initialized with the new instructions according to the following procedure: These steps should be executed from external memory or by download via host interface: 1. Set Cache Enable = 1 2. Set Patch Enable = 1 3. initialize TAGs to different values by unlock eight different external sectors 4. lock the PATCH sector(s) 5. move new code to locked sector(s), to the addresses that should be replaced 6. start regular PROM program
;**************************************************************************** ; PATCH initialization example ;**************************************************************************** page nolist 132,55,0,0,0
INCLUDE "ioequ.asm" INCLUDE "intequ.asm"
MOTOROLA
DSP56367
6-3
Core Configuration Operating Mode Register (OMR)
list START address PATCH_OFSET M_PAE M_PROMS M_PROME equ equ equ equ equ org move bset bset move move sector size move dup punlock different ; values endm plock (r2) ; lock patch's sector ; (start/mid/end) #(M_PROMS+PATCH_OFSET),r2 8 (r1)+n1 $100 128 23 $ffafec $ffafff P:START #M_PROMS,r0 #M_CE,sr #M_PAE,omr #$800000,r1 #128,n1 ; ; ; ; CacheEnable = 1 PatchEnable = 1 any external address 128 for 1K ICACHE, ; main program starting ; patch offset ; Patch Enable ; ROM area Start ; ROM area End
; initialize TAGs to
move ; ; replace ROM code by PATCH ; do movem movem nop PATCH_LOOP jsr execution ENDTEST jmp nop nop nop nop
#PATCH_DATA_START,r1
#(PATCH_DATA_END-PATCH_DATA_START+1),PATCH_LOOP p:(r1)+,x0 x0,p:(r2)+ ; Do-loop restriction
#M_PROMS
; start ROM code
ENDTEST
; ; patch data ;
6-4
DSP56367
MOTOROLA
Core Configuration Operating Modes
PATCH_DATA_START move move move PATCH_DATA_END ;**************************************************************************** #5,m0 #6,m1 #7,m2
6.3
OPERATING MODES
The operating modes are defined as shown in Table 6-2. The operating modes are latched from MODA, MODB, MODC and MODD pins during reset. Each operating mode is briefly described below. Except for modes 0 and 8, the operation of all other modes is defined by the Bootstrap ROM source code in Bootstrap ROM Contents on page Appendix A-1. Table 6-2 DSP56367 Operating Modes
Mode 0 1 2 3 4 5 6 MOD D 0 0 0 0 0 0 0 MOD C 0 0 0 0 1 1 1 MOD B 0 0 1 1 0 0 1 MOD A 0 1 0 1 0 1 0 Reset Vector $C00000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000 Expanded mode Bootstrap from byte-wide memory Jump to PROM starting address Reserved Reserved Bootstrap from SHI (slave SPI mode) Bootstrap from SHI (slave I2C mode)(HCKFR=1, 100ns filter enabled) Bootstrap from SHI (slave I2C mode)(HCKR=0) Expanded mode Reserved for Burn-in testing Reserved Reserved HDI08 Bootstrap in ISA Mode HDI08 Bootstrap in HC11 non-multiplexed mode HDI08 Bootstrap in 8051 multiplexed bus mode HDI08 Bootstrap in 68302 bus mode Description
7 8 9 A B C D E F
0 1 1 1 1 1 1 1 1
1 0 0 0 0 1 1 1 1
1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1
$FF0000 $008000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000
MOTOROLA
DSP56367
6-5
Core Configuration Operating Modes
Table 6-3 DSP56367 Mode Descriptions
Mode 0 The DSP starts fetching instructions beginning at address $C00000. Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected. Address $C00000 is reflected as address $00000 on Port A pins A0-A17. The bootstrap program loads instructions through Port A from external byte-wide memory, connected to the least significant byte of the data bus (bits 7-0), and starting at address P:$D00000. The bootstrap code expects to read 3 bytes specifying the number of program words, 3 bytes specifying the address to start loading the program words and then 3 bytes for each program word to be loaded. The number of words, the starting address and the program words are read least significant byte first followed by the mid and then by the most significant byte. The program words will be stored in contiguous PRAM memory locations starting at the specified starting address. After reading the program words, program execution starts from the same address where loading started.The SRAM memory access type is selected by the values in Address Attribute Register 1 (AAR1), with 31 wait states for each memory access. Address $D00000 is reflected as address $00000 on Port A pins A0-A17. The DSP starts fetching instructions from the starting address of the on-chip Program ROM. Reserved. Reserved. In this mode, the internal PRAM is loaded from the Serial Host Interface (SHI). The SHI operates in the SPI slave mode, with 24-bit word width.The bootstrap code expects to read a 24-bit word specifying the number of program words, a 24-bit word specifying the address to start loading the program words and then a 24-bit word for each program word to be loaded. The program words will be stored in contiguous PRAM memory locations starting at the specified starting address. After reading the program words, program execution starts from the same address where loading started. Same as Mode 5 except SHI interface operates in the I2C slave mode with HCKFR set to 1 and the 100ns filter enabled. Same as Mode 5 except SHI interface operates in the I2C slave mode with HCKFR set to 0. The DSP starts fetching instructions beginning at address $008000. Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected. Reserved. Used for Burn-In testing. Reserved. Reserved. Instructions are loaded through the HDI08, which is configured to interface with an ISA bus. The HOST ISA bootstrap code expects to read a 24-bit word specifying the number of program words, a 24-bit word specifying the address to start loading the program words and then a 24-bit word for each program word to be loaded. The program words will be stored in contiguous PRAM memory locations starting at the specified starting address. After reading the program words, program execution starts from the same address where loading started. The Host Interface bootstrap load program may be stopped by setting the Host Flag 0 (HF0). This will start execution of the loaded program from the specified starting address. As in Mode C, but HDI08 is set for interfacing to Motorola HC11 microcontroller in non-multiplexed mode As in Mode C, but HDI08 is set for interfacing to Intel 8051 multiplexed bus
Mode 1
Mode 2 Mode 3 Mode 4
Mode 5
Mode 6 Mode 7
Mode 8
Mode 9 Mode A Mode B
Mode C
Mode D Mode E
6-6
DSP56367
MOTOROLA
Core Configuration Interrupt Priority Registers
Table 6-3 DSP56367 Mode Descriptions
Mode F As in Mode C, but HDI08 is set for interfacing to Motorola 68302 bus.
6.4
INTERRUPT PRIORITY REGISTERS
There are two interrupt priority registers in the DSP56367: 1. IPR-C is dedicated for DSP56300 Core interrupt sources. 2. IPR-P is dedicated for DSP56367 peripheral interrupt sources. The interrupt priority registers are shown in Figure 6-1 and Figure 6-2. The Interrupt Priority Level bits are defined in Table 6-4. The interrupt vectors are shown in Table 6-6 and the interrupt priorities are shown in Table 6-5. Table 6-4 Interrupt Priority Level Bits
IPL bits xxL1 0 0 1 1 xxL0 0 1 0 1 Interrupts Enabled No Yes Yes Yes Interrupt Priority Level -- 0 1 2
MOTOROLA
DSP56367
6-7
Core Configuration Interrupt Priority Registers
11 10 9 8 ESL11 ESL10 TAL1 TAL0
7 DAL1
6
5
4
3 SHL1
2 SHL0
1 ESL1
0 ESL0 ESAI IPL SHI IPL HDI08 IPL DAX IPL TRIPLE TIMER IPL ESAI_1 IPL
DAL0 HDL1 HDL0
23
22
21
20
19
18
17
16
15
14
13
12
reserved
Reserved bit. Read as zero, should be written with zero for future compatibility.
Figure 6-1 Interrupt Priority Register P
11 IDL2
10 IDL1
9 IDL0
8 ICL2
7 ICL1
6 ICL0
5 IBL2
4 IBL1
3 IBL0
2 IAL2
1 IAL1
0 IAL0 IRQA IPL IRQA mode IRQB IPL IRQB mode IRQC IPL IRQC mode IRQD IPL IRQD mode
23 D5L1
22 D5L0
21 D4L1
20 D4L0
19 D3L1
18 D3L0
17 D2L1
16 D2L0
15 D1L1
14 D1L0
13 D0L1
12 D0L0 DMA0 IPL DMA1 IPL DMA2 IPL DMA3 IPL DMA4 IPL DMA5 IPL
Figure 6-2 Interrupt Priority Register C
6-8
DSP56367
MOTOROLA
Core Configuration Interrupt Priority Registers
Table 6-5 Interrupt Sources Priorities Within an IPL
Priority Level 3 (Nonmaskable) Highest Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Lowest Levels 0, 1, 2 (Maskable) Highest IRQA (External Interrupt) IRQB (External Interrupt) IRQC (External Interrupt) IRQD (External Interrupt) DMA Channel 0 Interrupt DMA Channel 1 Interrupt DMA Channel 2 Interrupt DMA Channel 3 Interrupt DMA Channel 4 Interrupt DMA Channel 5 Interrupt ESAI Receive Data with Exception Status ESAI Receive Even Data ESAI Receive Data ESAI Receive Last Slot ESAI Transmit Data with Exception Status ESAI Transmit Last Slot ESAI Transmit Even Data ESAI Transmit Data SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data SHI Receive FIFO Not Empty HOST Command Interrupt HOST Receive Data Interrupt Non-Maskable Interrupt Interrupt Source
MOTOROLA
DSP56367
6-9
Core Configuration Interrupt Priority Registers
Table 6-5 Interrupt Sources Priorities Within an IPL (Continued)
Priority HOST Transmit Data Interrupt DAX Transmit Underrun Error DAX Block Transferred DAX Transmit Register Empty TIMER0 Overflow Interrupt TIMER0 Compare Interrupt TIMER1 Overflow Interrupt TIMER1 Compare Interrupt TIMER2 Overflow Interrupt TIMER2 Compare Interrupt ESAI_1 Receive Data with Exception Status ESAI_1 Receive Even Data ESAI_1 Receive Data ESAI_1 Receive Last Slot ESAI_1 Transmit Data with Exception Status ESAI_1 Transmit Last Slot ESAI_1 Transmit Even Data Lowest ESAI_1 Transmit Data Interrupt Source
Table 6-6 DSP56367 Interrupt Vectors
Interrupt Starting Address Interrupt Priority Level Range 3 3 3 3 3 3 3 3 0-2 0-2 0-2 Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Non-Maskable Interrupt (NMI) Reserved For Future Level-3 Interrupt Source Reserved For Future Level-3 Interrupt Source IRQA IRQB IRQC Interrupt Source
VBA:$00 VBA:$02 VBA:$04 VBA:$06 VBA:$08 VBA:$0A VBA:$0C VBA:$0E VBA:$10 VBA:$12 VBA:$14
6-10
DSP56367
MOTOROLA
Core Configuration Interrupt Priority Registers
Table 6-6 DSP56367 Interrupt Vectors (Continued)
Interrupt Starting Address Interrupt Priority Level Range 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 IRQD DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 DMA Channel 4 DMA Channel 5 Reserved Reserved DAX Underrun Error DAX Block Transferred Reserved DAX Audio Data Empty ESAI Receive Data ESAI Receive Even Data ESAI Receive Data With Exception Status ESAI Receive Last Slot ESAI Transmit Data ESAI Transmit Even Data ESAI Transmit Data with Exception Status ESAI Transmit Last Slot SHI Transmit Data SHI Transmit Underrun Error SHI Receive FIFO Not Empty Reserved SHI Receive FIFO Full SHI Receive Overrun Error SHI Bus Error Reserved Reserved Reserved TIMER0 Compare TIMER0 Overflow Interrupt Source
VBA:$16 VBA:$18 VBA:$1A VBA:$1C VBA:$1E VBA:$20 VBA:$22 VBA:$24 VBA:$26 VBA:$28 VBA:$2A VBA:$2C VBA:$2E VBA:$30 VBA:$32 VBA:$34 VBA:$36 VBA:$38 VBA:$3A VBA:$3C VBA:$3E VBA:$40 VBA:$42 VBA:$44 VBA:$46 VBA:$48 VBA:$4A VBA:$4C VBA:$4E VBA:$50 VBA:$52 VBA:$54 VBA:$56
MOTOROLA
DSP56367
6-11
Core Configuration Interrupt Priority Registers
Table 6-6 DSP56367 Interrupt Vectors (Continued)
Interrupt Starting Address Interrupt Priority Level Range 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 : 0-2 TIMER1 Compare TIMER1 Overflow TIMER2 Compare TIMER2 Overflow Host Receive Data Full Host Transmit Data Empty Host Command (Default) Reserved Reserved Reserved Reserved Reserved ESAI_1 Receive Data ESAI_1 Receive Even Data ESAI_1 Receive Data With Exception Status ESAI_1 Receive Last Slot ESAI_1 Transmit Data ESAI_1 Transmit Even Data ESAI_1 Transmit Data with Exception Status ESAI_1 Transmit Last Slot Reserved : Reserved Interrupt Source
VBA:$58 VBA:$5A VBA:$5C VBA:$5E VBA:$60 VBA:$62 VBA:$64 VBA:$66 VBA:$68 VBA:$6A VBA:$6C VBA:$6E VBA:$70 VBA:$72 VBA:$74 VBA:$76 VBA:$78 VBA:$7A VBA:$7C VBA:$7E VBA:$80 : VBA:$FE
6-12
DSP56367
MOTOROLA
Core Configuration DMA Request Sources
6.5
DMA REQUEST SOURCES
The DMA Request Source bits (DRS0-DRS4 bits in the DMA Control/Status registers) encode the source of DMA requests used to trigger the DMA transfers. The DMA request sources may be the internal peripherals or external devices requesting service through the IRQA, IRQB, IRQC and IRQD pins. The DMA Request Sources are shown in Table 6-7. Table 6-7 DMA Request Sources
DMA Request Source Bits DRS4...DRS0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111-11111 External (IRQA pin) External (IRQB pin) External (IRQC pin) External (IRQD pin) Transfer Done from DMA channel 0 Transfer Done from DMA channel 1 Transfer Done from DMA channel 2 Transfer Done from DMA channel 3 Transfer Done from DMA channel 4 Transfer Done from DMA channel 5 DAX Transmit Data ESAI Receive Data (RDF=1) ESAI Transmit Data (TDE=1) SHI HTX Empty SHI FIFO Not Empty SHI FIFO Full HDI08 Receive Data HDI08 Transmit Data TIMER0 (TCF=1) TIMER1 (TCF=1) TIMER2 (TCF=1) ESAI_1 Receive Data (RDF=1) ESAI_1 Transmit Data (TDE=1) RESERVED Requesting Device
MOTOROLA
DSP56367
6-13
Core Configuration PLL Initialization
6.6
PLL INITIALIZATION
6.6.1
PLL MULTIPLICATION FACTOR (MF0-MF11)
The DSP56367 PLL multiplication factor is set to 6 during hardware reset, i.e. the Multiplication Factor Bits MF0-MF11 in the PLL Control Register (PCTL) are set to $005.
6.6.2
PLL PRE-DIVIDER FACTOR (PD0-PD3)
The DSP56367 PLL Pre-Divider factor is set to 1 during hardware reset, i.e. the Pre-Divider Factor Bits PD0-PD3 in the PLL Control Register (PCTL) are set to $0.
6.6.3
CRYSTAL RANGE BIT (XTLR)
The Crystal Range (XTLR) bit controls the on-chip crystal oscillator transconductance. The on-chip crystal oscillator is not used on the DSP56367 since no XTAL pin is available. The XTLR bit is set to zero during hardware reset in the DSP56367.
6.6.4
XTAL DISABLE BIT (XTLD)
The XTAL Disable Bit (XTLD) is set to 1 (XTAL disabled) during hardware reset in the DSP56367.
6.7
DEVICE IDENTIFICATION (ID) REGISTER
The Device Identification Register (IDR) is a 24 bit read only factory programmed register used to identify the different DSP56300 core-based family members. This register specifies the derivative number and revision number. This information may be used in testing or by software. Table 6-8 shows the ID register configuration.
6-14
DSP56367
MOTOROLA
Core Configuration JTAG Identification (ID) Register
Table 6-8 Identification Register Configuration
23 16 Reserved $00 15 12 Revision Number $0 11 Derivative Number $367 0
6.8
JTAG IDENTIFICATION (ID) REGISTER
The JTAG Identification (ID) Register is a 32 bit, read only thought JTAG, factory programmed register used to distinguish the component on a board according to the IEEE 1149.1 standard. Table 6-9 shows the JTAG ID register configuration. Table 6-9 JTAG Identification Register Configuration
31 Version Information 0000 28 27 22 21 12 Sequence Number 0001010010 11 1 Manufacturer Identity 00000001110 0 1 1
Customer Part Number 000111
6.9
JTAG BOUNDARY SCAN REGISTER (BSR)
The boundary scan register (BSR) in the DSP56367 JTAG implementation contains bits for all device signal and clock pins and associated control signals. All bidirectional pins have a single register bit in the boundary scan register for pin data, and are controlled by an associated control bit in the boundary scan register. The boundary scan register bit definitions are described in Table 6-10. Table 6-10 DSP56367 BSR Bit Definition
Bit #
0 1 2 3 4
Pin Name SDO4_1/SDI1_1 SDO4_1/SDI1_1 IRQA IRQB IRQC -
Pin Type
BSR Cell Type Control Data Data Data Data
Bit # 76 77 78 79 80
Pin Name FST_1 FST_1 SDO5_1/SDI0_1 SDO5_1/SDI0_1 RES -
Pin Type
BSR Cell Type Control Data Control
Input/Output Input Input Input
Input/Output
Input/Output Input
Data Data
MOTOROLA
DSP56367
6-15
Core Configuration JTAG Boundary Scan Register (BSR)
Table 6-10 DSP56367 BSR Bit Definition (Continued)
Bit #
5 6 7 8 9 10 11 12 13 14 15 16
Pin Name IRQD D23 D22 D21 D20 D19 D18 D17 D16 D15 D[23:13] D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D[12:0] D2 D1 D0 A17 A16 A15 A[17:9]
Pin Type Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output3 Output3 Output3 -
BSR Cell Type Data Data Data Data Data Data Data Data Data Data Control Data Data Data Data Data Data Data Data Data Data Data Data Control Data Data Data Data Data Data Control
Bit # 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
Pin Name HAD0 HAD0 HAD1 HAD1 HAD2 HAD2 HAD3 HAD3 HAD4 HAD4 HAD5 HAD5 HAD6 HAD6 HAD7 HAD7 HAS/A0 HAS/A0 HA8/A1 HA8/A1 HA9/A2 HA9/A2 HCS/A10 HCS/A10 TIO0 TIO0 ACI ACI ADO ADO HREQ/HTRQ -
Pin Type
BSR Cell Type Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output -
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
6-16
DSP56367
MOTOROLA
Core Configuration JTAG Boundary Scan Register (BSR)
Table 6-10 DSP56367 BSR Bit Definition (Continued)
Bit # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 A14 A13 A12 A11 A10 A9 A8 A7 A6 A[8:0] A5 A4 A3 A2 A1 A0 BG AA0 AA0 AA1 AA1 RD WR BB BB BR TA PINIT SCKR_1 SCKR_1 FSR_1 Input/Output Pin Name Pin Type Output3 Output3 Output3 Output3 Output3 Output3 Output3 Output3 Output3 Output3 Output3 Output3 Output3 Output3 Output3 Input Output3 Output3 Output3 Output3 Input/Output Output2 Input Input BSR Cell Type Data Data Data Data Data Data Data Data Data Control Data Data Data Data Data Data Data Control Data Control Data Data Data Control Data Data Data Data Control Data Control Bit # 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 Pin Name HREQ/HTRQ HACK/RRQ HACK/RRQ HRW/RD HRW/RD HDS/WR HDS/WR HSCKR HSCKR HSCKT HSCKT SCKR SCKR SCKT SCKT FSR FSR FST FST SDO5/SDI0 SDO5/SDI0 SDO4/SDI1 SDO4/SDI1 SDO3/SDI2 SDO3/SDI2 SDO2/SDI3 SDO2/SDI3 SDO1 SDO1 SDO0 SDO0 Pin Type Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output BSR Cell Type Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data Control Data
MOTOROLA
DSP56367
6-17
Core Configuration JTAG Boundary Scan Register (BSR)
Table 6-10 DSP56367 BSR Bit Definition (Continued)
Bit # 67 68 69 70 71 72 73 74 75 Pin Name FSR_1 RD,WR EXTAL SCKT_1 SCKT_1 CAS CAS AA2 AA2 Pin Type Input/Output Input Input/Output Output3 Output3 BSR Cell Type Data Control Data Control Data Control Data Control Data Bit # 143 144 145 146 147 148 149 150 151 Pin Name HREQ HREQ SS SCK/SCL SCK/SCL MISO/SDA MISO/SDA MOSI/HA0 MOSI/HA0 Input/Output Input Input/Output Input/Output Input/Output Pin Type BSR Cell Type Control Data Data Control Data Control Data Control Data
6-18
DSP56367
MOTOROLA
SECTION
7
GENERAL PURPOSE INPUT/OUTPUT
7.1 INTRODUCTION
The DSP56367 provides up to 37 bidirectional signals that can be configured as GPIO signals or as peripheral dedicated signals. No dedicated GPIO signals are provided. All of these signals are GPIO by default after reset. The techniques for register programming for all GPIO functionality is very similar between these interfaces. This section describes how signals may be used as GPIO.
7.2
PROGRAMMING MODEL
The signals description section of this manual describes the special uses of these signals in detail. There are five groups of these signals which can be controlled separately or as groups: * * * * * Port B: up to 16 GPIO signals (shared with the HDI08 signals) Port C: 12 GPIO signals (shared with the ESAI signals) Port D: two GPIO signals (shared with the DAX signals) Port E: 10 GPIO signals (shared with the ESAI_1 signals) Timer: one GPIO signal (shared with the timer/event counter signal)
7.2.1
PORT B SIGNALS AND REGISTERS
When HDI08 is disabled, all 16 HDI08 signals can be used as GPIO. When HDI08 is enabled, five (HA8, HA9, HCS, HOREQ, and HACK) of the 16 port B signals, if not used as a HDI08 signal, can be configured as GPIO signals. The GPIO functionality of port B is controlled by three registers: host port control register (HPCR), host port GPIO data register (HDR), and host port GPIO direction register (HDDR). These registers are described in Section 8 - Host Interface (HDI08) of this document.
MOTOROLA
DSP56367
7-1
General Purpose Input/Output Programming Model
7.2.2
PORT C SIGNALS AND REGISTERS
Each of the 12 port C signals not used as an ESAI signal can be configured individually as a GPIO signal. The GPIO functionality of port C is controlled by three registers: port C control register (PCRC), port C direction register (PRRC), and port C data register (PDRC). These registers are described in Section 10 - Enhanced Serial Audio Interface (ESAI).
7.2.3
PORT D SIGNALS AND REGISTERS
Each of the two Port D signals not used as a DAX signal can be configured individually as a GPIO signal. The GPIO functionality of Port D is controlled by three registers: Port D control register (PCRD), Port D direction register (PRRD) and Port D data register (PDRD). These registers are described in Section 12 - Digital Audio Transmitter.
7.2.4
PORT E SIGNALS AND REGISTERS
Port E has 10 signals, shared with the ESAI_1. Six of the ESAI_1 signals have their own pin, so each of the six signals, if not used as an ESAI_1 signal, can be configured individually as a GPIO signal. The other four ESAI_1 signals share pins with the ESAI. For these shared pins, if the pin is not being used by the ESAI, Port C and the ESAI_1, then it may be used as a Port E GPIO signal. The GPIO functionality of port E is controlled by three registers: port E control register (PCRE), port E direction register (PRRE), and port E data register (PDRE). These registers are described in Section 11 - Enhanced Serial Audio Interface 1 (ESAI_1).
7.2.5
TIMER/EVENT COUNTER SIGNALS
The timer/event counter signal (TIO), when not used as a timer signal can be configured as a GPIO signal. The signal is controlled by the appropriate timer control status register (TCSR). The register is described in Section 13 - Timer/ Event Counter.
7-2
DSP56367
MOTOROLA
SECTION
8
HOST INTERFACE (HDI08)
8.1 INTRODUCTION
The host interface (HDI08) is a byte-wide, full-duplex, double-buffered, parallel port that can be connected directly to the data bus of a host processor. The HDI08 supports a variety of buses and provides glueless connection with a number of industry standard microcomputers, microprocessors, DSPs and DMA hardware. The host bus can operate asynchronously to the DSP core clock, therefore the HDI08 registers are divided into 2 banks. The host register bank is accessible to the external host and the DSP register bank is accessible to the DSP core. The HDI08 supports three classes of interfaces: * * * Host processor/Microcontroller (MCU) connection interface DMA controller interface General purpose I/O (GPIO) port
8.2
HDI08 FEATURES
8.2.1
*
INTERFACE - DSP SIDE
Mapping: - Registers are directly mapped into eight internal X data memory locations
*
Data Word: - 24-bit (native) data words are supported, as are 8-bit and 16-bit words
*
Transfer Modes: - - DSP to Host Host to DSP
MOTOROLA
DSP56367
8-1
Host Interface (HDI08) HDI08 Features
- *
Host Command
Handshaking Protocols: - - - Software polled Interrupt driven Core DMA accesses
*
Instructions: - - - Memory-mapped registers allow the standard MOVE instruction to be used to transfer data between the DSP and the external host. Special MOVEP instruction provides for I/O service capability using fast interrupts. Bit addressing instructions (e.g. BCHG, BCLR, BSET, BTST, JCLR, JSCLR, JSET, JSSET) simplify I/O service routines.
8.2.2
*
INTERFACE - HOST SIDE
Sixteen signals are provided to support non-multiplexed or multiplexed buses: - - - - - - - - H0-H7/HAD0-HAD7 Host data bus (H7-H0) or host multiplexed address/data bus (HAD0-HAD7) HAS/HA0 Address strobe (HAS) or Host address line HA0 HA8/HA1 Host address line HA8 or Host address line HA1 HA9/HA2 Host address line HA9 or Host address line HA2 HRW/HRD Read/write select (HRW) or Read Strobe (HRD) HDS/HWR Data Strobe (HDS) or Write Strobe (HWR) HCS/HA10 Host chip select (HCS) or Host address line HA10 HOREQ/HTRQ Host request (HOREQ) or Host transmit request (HTRQ)
8-2
DSP56367
MOTOROLA
Host Interface (HDI08) HDI08 Features
- *
HACK/HRRQ Host acknowledge (HACK) or Host receive request (HRRQ)
Mapping: - - HDI08 registers are mapped into eight consecutive byte locations in the external host bus address space. The HDI08 acts as a memory or IO-mapped peripheral for microprocessors, microcontrollers, etc.
*
Data Word: - 8-bit
*
Transfer Modes: - Mixed 8-bit, 16-bit and 24-bit data transfers * * - DSP to Host Host to DSP
Host Command
*
Handshaking Protocols: - - - Software polled Interrupt-driven (Interrupts are compatible with most processors, including the MC68000, 8051, HC11 and Hitachi H8). Cycle-stealing DMA with initialization
*
Dedicated Interrupts: - - Separate interrupt lines for each interrupt source Special host commands force DSP core interrupts under host processor control, which are useful for the following: * * * Real-Time Production Diagnostics Debugging Window for Program Development Host Control Protocols
*
Interface Capabilities: - Glueless interface (no external logic required) to the following: * * * Motorola HC11 Hitachi H8 8051 family
MOTOROLA
DSP56367
8-3
Host Interface (HDI08) HDI08 Host Port Signals
* * -
Thomson P6 family external DMA controllers
Minimal glue-logic (pullups, pulldowns) required to interface to the following: * * * ISA bus Motorola 68K family Intel X86 family.
8.3
HDI08 HOST PORT SIGNALS
If the Host Interface functionality is not required, the 16 pins may be defined as general purpose I/O pins PB0-PB15. When the HDI08 is in use, only five host port signals (HA8, HA9, HCS, HOREQ and HACK) may be individually programmed as GPIO pins if they are not needed for their HDI08 function. Summary of the HDI08 signals. Table 8-1 HDI08 Signal Summary
HDI08 Port Pin HAD0-HAD7 HAS/HA0 HA8/HA1 HA9/HA2 HCS/HA10 Multiplexed address/data bus Mode HAD0-HAD7 HAS/HAS HA8 HA9 HA10 Non Multiplexed bus Mode H0-H7 HA0 HA1 HA2 HCS/HCS GPIO Mode PB0-PB7 PB8 PB9 PB10 PB13
Table 8-2 Strobe Signals Support signals
HDI08 Port Pin HRW/HRD HDS/HWR Single strobe bus HRW HDS/HDS Dual strobe bus HRD/HRD HWR/HWR GPIO Mode PB11 PB12
Table 8-3 Host request support signals
HDI08 Port Pin HOREQ/HTRQ HACK/HRRQ Vector required HOREQ/HOREQ HACK/HACK No vector required HTRQ/HTRQ HRRQ/HRRQ GPIO Mode PB14 PB15
8-4
DSP56367
MOTOROLA
Host Interface (HDI08) HDI08 Block Diagram
8.4
HDI08 BLOCK DIAGRAM
Figure 8-1 shows the HDI08 registers. The top row of registers (HCR, HSR, HDDR, HDR, HBAR, HPCR, HOTX, HORX) can be accessed the DSP core. The bottom row of registers (ISR, ICR, CVR, IVR, RXH:RXM:RXL and TXH:TXM:TXL) can be accessed by the host processor.
Core DMA Data Bus DSP Peripheral Data Bus
24 24 24 24 24 24 24 24 24 24
HCR
HSR
HDDR
HDR
HBAR
8
HPCR
HOT
HOR
Address Comparator
24
24
5 3
ICR
ISR
CVR
IVR
Latch
RXH RXM RXL
8 8
TXH TXM RXL
8 8 8
8
8
8
8
8
3
8
HOST Bus
ICR CVR ISR IVR RXH/RXM/RXL TXH/TXM/TXL Interface Control Register Command Vector Register Interface Status Register Interrupt Vector Register Receive Register High/Middle/Low Transmit Register High/Middle/Low HCR HSR HPCR HBAR HOTX HORX HDDR HDR Host Control Register Host Status Register Host Port Control Register Host Base Address register Host Transmit register Host Receive register Host Data Direction Register Host Data Register
Figure 8-1 HDI08 Block Diagram
MOTOROLA
DSP56367
8-5
Host Interface (HDI08) HDI08 - DSP-Side Programmer's Model
8.5
HDI08 - DSP-SIDE PROGRAMMER'S MODEL
The DSP core threats the HDI08 as a memory-mapped peripheral occupying eight 24-bit words in X data memory space. The DSP may use the HDI08 as a normal memory-mapped peripheral, employing either standard polled or interrupt-driven programming techniques. Separate transmit and receive data registers are double-buffered to allow the DSP and host processor to transfer data efficiently at high speed. Direct memory mapping allows the DSP core to communicate with the HDI08 registers using standard instructions and addressing modes. In addition, the MOVEP instruction allows direct data transfers between the DSP memory and the HDI08 registers or vice-versa. The HOTX and HORX registers may be serviced by the on-chip DMA controller for data transfers. The eight host processor registers consists of two data registers and six control registers. All registers can be accessed by the DSP core but not by the external processor. Data registers are 24-bit registers used for high-speed data transfer to and from the DSP. They are as follows: * * Host Data Receive Register (HORX) Host Data Transmit Register (HOTX)
The control registers are 16-bit registers used to control the HDI08 functions. The eight MSBs in the control registers are read by the DSP as zero. The control registers are as follows: * * * * * * Host control register (HCR) Host status register (HSR) Host base address register (HBAR) Host port control register (HPCR) Host GPIO data direction register (HDDR) Host GPIO data register (HDR)
Hardware and software reset disable the HDI08. After reset, the HDI08 signals are configured as GPIO with all pins disconnected.
8.5.1
HOST RECEIVE DATA REGISTER (HORX)
The 24-bit read-only HORX register is used for host-to-DSP data transfers. The HORX register is loaded with 24-bit data from the transmit data registers (TXH:TXM:TXL) on the host side when both the transmit data register empty TXDE (host side) and host receive data
8-6
DSP56367
MOTOROLA
Host Interface (HDI08) HDI08 - DSP-Side Programmer's Model
full HRDF (DSP side) bits are cleared. This transfer operation sets both the TXDE and HRDF flags. The HORX register contains valid data when the HRDF bit is set. Reading HORX clears HRDF. The DSP may program the HRIE bit to cause a host receive data interrupt when HRDF is set. Also, a DMA channel may be programmed to read the HORX when HRDF is set.
8.5.2
HOST TRANSMIT DATA REGISTER (HOTX)
The 24-bit write-only HOTX register is used for DSP- to-host data transfers. Writing to the HOTX register clears the host transfer data empty flag HTDE (DSP side). The contents of the HOTX register are transferred as 24-bit data to the receive byte registers (RXH:RXM:RXL) when both the HTDE flag (DSP side) and receive data full RXDF flag (host side) are cleared. This transfer operation sets the RXDF and HTDE flags. The DSP may set the HTIE bit to cause a host transmit data interrupt when HTDE is set. Also, a DMA Channel may be programmed to write to HOTX when HTDE is set. To prevent the previous data from being overwritten, data should not be written to the HOTX until the HTDE flag is set. Note: When writing data to a peripheral device, there is a two-cycle pipeline delay until any status bits affected by the operation are updated. If the programmer reads any of those status bits within the next two cycles, the bit will not reflect its current status. See the DSP56300 24-Bit Digital Signal Processor Family Manual, Motorola publication DSP56300FM/AD for further details.
8.5.3
HOST CONTROL REGISTER (HCR)
The HCR is 16-bit read/write control register used by the DSP core to control the HDI08 operating mode. The initialization values for the HCR bits are described in Section 8.5.9. The HCR bits are described in the following paragraphs. Figure 8-2 Host Control Register (HCR) (X:$FFFFC2)
15 14 13 12 11 10 9 8 7 6 5 4 HF3 3 HF2 2 HCIE 1 HTIE 0 HRIE HDM2 HMD1 HDM0 - Reserved bit. Read as 0. Should be written with 0 for future compatibility.
8.5.3.1 HCR Host Receive Interrupt Enable (HRIE) Bit 0 The HRIE bit is used to enable the host receive data interrupt request. When the host receive data full (HRDF) status bit in the host status register (HSR) is set, a host receive data interrupt request occurs if HRIE is set. If HRIE is cleared, HRDF interrupts are disabled.
MOTOROLA
DSP56367
8-7
Host Interface (HDI08) HDI08 - DSP-Side Programmer's Model
8.5.3.2 HCR Host Transmit Interrupt Enable (HTIE) Bit 1 The HTIE bit is used to enable the host transmit data empty interrupt request. When the host transmit data empty (HTDE) status bit in the HSR is set, a host transmit data interrupt request occurs if HTIE is set. If HTIE is cleared, HTDE interrupts are disabled. 8.5.3.3 HCR Host Command Interrupt Enable (HCIE) Bit 2 The HCIE bit is used to enable the host command interrupt request. When the host command pending (HCP) status bit in the HSR is set, a host command interrupt request occurs if HCIE is set. If HCIE is cleared, HCP interrupts are disabled. The interrupt address is determined by the host command vector register (CVR). Note: Host interrupt request priorities: If more than one interrupt request source is asserted and enabled (e.g. HRDF=1, HCP=1, HRIE=1 and HCIE=1), the HDI08 generates interrupt requests according to the following table: Table 8-4 HDI08 IRQ
Priority Highest Interrupt Source Host Command (HCP=1) Transmit Data (HTDE=1) Lowest Receive Data (HRDF=1)
8.5.3.4 HCR Host Flags 2,3 (HF2,HF3) Bits 3-4 HF2 and HF3 bits are used as a general-purpose flags for DSP to host communication. HF2 and HF3 may be set or cleared by the DSP core. HF2 and HF3 are reflected in the interface status register (ISR) on the host side such that if they are modified by the DSP software, the host processor can read the modified values by reading the ISR. These two flags are not designated for any specific purpose but are general-purpose flags. They can be used individually or as encoded pairs in a simple DSP to host communication protocol, implemented in both the DSP and the host processor software. 8.5.3.5 HCR Host DMA Mode Control Bits (HDM0, HDM1, HDM2) Bits 5-7 The HDM[2:0] bits are used to enable the HDI08 DMA mode operation. The HDI08 DMA mode supports external DMA controller devices connected to the HDI08 on the Host side. This mode should not be confused with the operation of the on-chip DMA controller. With HDM[2:0] cleared, the HDI08 does not support DMA mode operation and the TREQ and RREQ control bits are used for host processor interrupt control via the external HOREQ output signal (or HRREQ and HTREQ output signals if HDREQ in the ICR is set). Also, in the non-DMA mode, the HACK input signal is used for the MC68000 Family vectored
8-8
DSP56367
MOTOROLA
Host Interface (HDI08) HDI08 - DSP-Side Programmer's Model
interrupt acknowledge input. If HDM[2:0] are not all cleared, the HDI08 operates as described in Table 8-5. Table 8-5 HDM[2:0] Functionality
HDM 2 0 1 0 0 0 Description DMA operation disabled INIT 1 0 0 DMA Operation Enabled. Host may set HM1 or HM0 in the ICR to enable DMA transfers. DMA Mode Data Output Transfers Enabled. (24-Bit words) DMA Mode Data Output Transfers Enabled. (16-Bit words) DMA Mode Data Output Transfers Enabled. (8-Bit words) DMA Mode Data Input Transfers Enabled. (24-Bit words) DMA Mode Data Input Transfers Enabled. (16-Bit words) DMA Mode Data Input Transfers Enabled. (8-Bit words) HLEND HF1 HF0 HDRQ TREQ RREQ Mode ICR
INIT
HM1
HM0
HF1
HF0
TREQ
RREQ
0
0
1
0
1
0
0
1
1
INIT
HDM1 HDM0
HF1
HF0
TREQ
RREQ
1
0
1
1
1
0
1
1
1
If HDM1 or HDM0 are set, the DMA mode is enabled, and the HOREQ signal is used to request DMA transfers (the value of the HM1, HM0, HLEND and HDREQ bits in the ICR have no affect). When the DMA mode is enabled, the HDM2 bit selects the direction of DMA transfers: - - setting HDM2 sets the direction of DMA transfer to be DSP to host and enables the HOREQ signal to request data transfer. clearing HDM2 sets the direction of DMA transfer to be host to DSP and enables the HOREQ signal to request data transfer.
The HACK input signal is used as a DMA transfer acknowledge input. If the DMA direction is from DSP to host, the contents of the selected register are driven onto the host data bus
MOTOROLA
DSP56367
8-9
Host Interface (HDI08) HDI08 - DSP-Side Programmer's Model
when HACK is asserted. If the DMA direction is from host to DSP, the selected register is written from the host data bus when HACK is asserted. The size of the DMA word to be transferred is determined by the DMA control bits, HDM[1:0]. Only the data registers TXH, TXM, TXL and RXH, RXM, RXL can be accessed in DMA mode.The HDI08 data register selected during a DMA transfer is determined by a 2-bit address counter, which is preloaded with the value in HDM[1:0]. The address counter substitutes for the address bits of the HDI08 during a DMA transfer. The address counter can be initialized with the INIT bit feature. After each DMA transfer on the host data bus, the address counter is incremented to the next register. When the address counter reaches the highest register (RXL or TXL), the address counter is not incremented but is loaded with the value in HDM[1:0]. This allows 8-, 16- or 24-bit data to be transferred in a circular fashion and eliminates the need for the DMA controller to supply the HA2, HA1, and HA0 signals. For 16- or 24-bit data transfers, the DSP CPU interrupt rate is reduced by a factor of 2 or 3, respectively, from the host request rate - i.e., for every two or three host processor data transfers of one byte each, there is only one 24-bit DSP CPU interrupt. If HDM1 or HDM0 are set, the HM[1:0] bits in the ICR register reflect the value of HDM[1:0]. The HDM[2:0] bits should be changed only while HEN is cleared in the HPCR. 8.5.3.6 HCR Reserved Bits 8-15 These bits are reserved. They read as zero and should be written with zero for future compatibility.
8.5.4
HOST STATUS REGISTER (HSR)
The HSR is a 16-bit read-only status register used by the DSP to read the status and flags of the HDI08. It cannot be directly accessed by the host processor. The initialization values for the HSR bits are described in Section 8.5.9. The HSR bits are described in the following paragraphs. Figure 8-3 Host Status Register (HSR) (X:FFFFC3)
15 14 13 12 11 10 9 8 7 DMA - Reserved bit. Read as 0. Should be written with 0 for future compatibility. 6 5 4 HF1 3 HF0 2 HCP 1 0 HTDE HRDF
8.5.4.1 HSR Host Receive Data Full (HRDF) Bit 0 The HRDF bit indicates that the host receive data register (HORX) contains data from the host processor. HRDF is set when data is transferred from the TXH:TXM:TXL registers to the HORX register. HRDF is cleared when HORX is read by the DSP core. If HRDF is set the
8-10
DSP56367
MOTOROLA
Host Interface (HDI08) HDI08 - DSP-Side Programmer's Model
HDI08 generates a receive data full DMA request, if enabled by a DSP core DMA Channel. If HRDF is set when HRIE is set, a host receive data interrupt request is generated. HRDF can also be cleared by the host processor using the initialize function. 8.5.4.2 HSR Host Transmit Data Empty (HTDE) Bit 1 The HTDE bit indicates that the host transmit data register (HOTX) is empty and can be written by the DSP core. HTDE is set when the HOTX register is transferred to the RXH:RXM:RXL registers. HTDE is cleared when HOTX is written by the DSP core. If HTDE is set the HDI08 generates a transmit data empty DMA request, if enabled by a DSP core DMA Channel. If HTDE is set when HTIE is set, a host transmit data interrupt request is generated. HTDE can also be set by the host processor using the initialize function. 8.5.4.3 HSR Host Command Pending (HCP) Bit 2 The HCP bit indicates that the host has set the HC bit and that a host command interrupt is pending. The HCP bit reflects the status of the HC bit in the command vector register (CVR). HC and HCP are cleared by the HDI08 hardware when the interrupt request is serviced by the DSP core. The host can clear HC, which also clears HCP. 8.5.4.4 HSR Host Flags 0,1 (HF0,HF1) Bits 3-4 HF0 and HF1 bits are used as a general-purpose flags for host to DSP communication. HF0 and HF1 may be set or cleared by the host. HF0 and HF1 reflect the status of host flags HF0 and HF1 in the ICR register on the host side. These two flags are not designated for any specific purpose but are general-purpose flags. They can be used individually or as encoded pairs in a simple host to DSP communication protocol, implemented in both the DSP and the host Processor software. 8.5.4.5 HSR Reserved Bits 5-6, 8-15 These bits are reserved. They read as zero and should be written with zero for future compatibility. 8.5.4.6 HSR DMA Status (DMA) Bit 7 The DMA status bit is set when the DMA mode of operation is enabled, and is cleared when the DMA mode is disabled. The DMA mode is enabled under the following conditions: * * HCR bits HDM[2:0] = 100 and the host processor has enabled the DMA mode by setting either or both the ICR bits HM1 and HM0 Either or both of the HCR bits HDM1 and HDM0 have been set
When the DMA bit is zero, the channel not in use can be used for polled or interrupt operation by the DSP.
MOTOROLA
DSP56367
8-11
Host Interface (HDI08) HDI08 - DSP-Side Programmer's Model
8.5.5
HOST BASE ADDRESS REGISTER (HBAR)
The HBAR is used in multiplexed bus modes. This register selects the base address where the host side registers are mapped into the bus address space. The address from the host bus is compared with the base address as programmed in the base address register. If the addresses match, an internal chip select is generated. The use of this register by the chip select logic is shown in Figure 8-5. Figure 8-4 Host Base Address Register (HBAR) (X:$FFFFC5)
15 14 13 12 11 10 9 8 7 BA10 6 BA9 5 BA8 4 BA7 3 BA6 2 BA5 1 BA4 0 BA3
- Reserved bit. Read as 0. Should be written with 0, for future compatibility.
8.5.5.1 HBAR Base Address (BA[10:3]) Bits 0-7 These bits define the base address where the host side registers are mapped into the bus address space. 8.5.5.2 HBAR Reserved Bits 8-15 These bits are reserved. They read as zero and should be written with zero for future compatibility.
HAD[0-7]
Latch
HAS HA[8:10]
A[3:7]
COMPARATOR
Chip select
Base DSP Peripheral data bus Address register 8 bits BA[3:7]
Figure 8-5 Self Chip Select logic
8-12
DSP56367
MOTOROLA
Host Interface (HDI08) HDI08 - DSP-Side Programmer's Model
8.5.6
HOST PORT CONTROL REGISTER (HPCR)
The HPCR is a 16-bit read/write control register used by the DSP to control the HDI08 operating mode. The initialization values for the HPCR bits are described in Section 8.5.9. The HPCR bits are described in the following paragraphs. Figure 8-6 Host Port Control Register (HPCR) (X:$FFFFC4)
15 HAP 14 HRP 13 12 11 10 9 8 7 6 HEN 5 4 3 2 1 0 HCSP HDDS HMUX HASP HDSP HROD HAEN HREN HCSEN HA9EN HA8EN HGEN
- Reserved bit. Read as 0. Should be written with 0, for future compatibility.
Note:
To assure proper operation of the HDI08, the HPCR bits HAP, HRP, HCSP, HDDS, HMUX, HASP, HDSP, HROD, HAEN and HREN should be changed only if HEN is cleared. Also, the HPCR bits HAP, HRP, HCSP, HDDS, HMUX, HASP, HDSP, HROD, HAEN, HREN, HCSEN, HA9EN and HA8EN should not be set when HEN is set or simultaneously with setting HEN.
8.5.6.1 HPCR Host GPIO Port Enable (HGEN) Bit 0 If the HGEN bit is set, pins configured as GPIO are enabled. If this bit is cleared, pins configured as GPIO are disconnected: outputs are high impedance, inputs are electrically disconnected. Pins configured as HDI08 are not affected by the state of HGEN. 8.5.6.2 HPCR Host Address Line 8 Enable (HA8EN) Bit 1 If the HA8EN bit is set and the HDI08 is used in multiplexed bus mode, then HA8/HA1 is used as host address line 8 (HA8). If this bit is cleared and the HDI08 is used in multiplexed bus mode, then HA8/HA1 is configured as GPIO pin according to the value of HDDR and HDR registers. HA8EN is ignored when the HDI08 is not in the multiplexed bus mode (HMUX=0). 8.5.6.3 HPCR Host Address Line 9 Enable (HA9EN) Bit 2 If the HA9EN bit is set and the HDI08 is used in multiplexed bus mode, then HA9/HA2 is used as host address line 9 (HA9). If this bit is cleared and the HDI08 is used in multiplexed bus mode, then HA9/HA2 is configured as GPIO pin according to the value of HDDR and HDR registers. HA9EN is ignored when the HDI08 is not in the multiplexed bus mode (HMUX=0). 8.5.6.4 HPCR Host Chip Select Enable (HCSEN) Bit 3 If the HCSEN bit is set, then HCS/HA10 is used as host chip select (HCS) in the non-multiplexed bus mode (HMUX=0), and as host address line 10 (HA10) in the multiplexed bus mode (HMUX=1). If this bit is cleared, then HCS/HA10 is configured as GPIO pin according to the value of HDDR and HDR registers.
MOTOROLA
DSP56367
8-13
Host Interface (HDI08) HDI08 - DSP-Side Programmer's Model
8.5.6.5 HPCR Host Request Enable (HREN) Bit 4 The HREN bit controls the host request signals. If HREN is set and the HDI08 is in the single host request mode (HDRQ=0 in the ICR), HOREQ/HTRQ is configured as the host request (HOREQ) output. If HREN is set in the double host request mode (HDRQ=1 in the ICR), HOREQ/HTRQ is configured as the host transmit request (HTRQ) output and HACK/HRRQ as the host receive request (HRRQ) output. If HREN is cleared, HOREQ/HTRQ and HACK/HRRQ are configured as GPIO pins according to the value of HDDR and HDR registers. 8.5.6.6 HPCR Host Acknowledge Enable (HAEN) Bit 5 The HAEN bit controls the HACK signal. In the single host request mode (HDRQ=0 in the ICR), if HAEN and HREN are both set, HACK/HRRQ is configured as the host acknowledge (HACK) input. If HAEN or HREN is cleared, HACK/HRRQ is configured as a GPIO pin according to the value of HDDR and HDR registers. In the double host request mode (HDRQ=1 in the ICR), HAEN is ignored. 8.5.6.7 HPCR Host Enable (HEN) Bit 6 If the HEN bit is set, the HDI08 operation is enabled as Host Interface. If cleared, the HDI08 is not active, and all the HDI08 pins are configured as GPIO pins according to the value of HDDR and HDR registers. 8.5.6.8 HPCR Reserved Bit 7 This bit is reserved. It reads as zero and should be written with zero for future compatibility. 8.5.6.9 HPCR Host Request Open Drain (HROD) Bit 8 The HROD bit controls the output drive of the host request signals. In the single host request mode (HDRQ=0 in ICR), if HROD is cleared and host requests are enabled (HREN=1 and HEN=1 in HPCR), the HOREQ signal is always driven. If HROD is set and host requests are enabled, the HOREQ signal is an open drain output. In the double host request mode (HDRQ=1 in the ICR), if HROD is cleared and host requests are enabled (HREN=1 and HEN=1 in the HPCR), the HTRQ and HRRQ signals are always driven. If HROD is set and host requests are enabled, the HTRQ and HRRQ signals are open drain outputs. 8.5.6.10 HPCR Host Data Strobe Polarity (HDSP) Bit 9 If the HDSP bit is cleared, the data strobe signals are configured as active low inputs, and data is transferred when the data strobe is low. If HDSP is set, the data strobe signals are configured as active high inputs, and data is transferred when the data strobe is high. The data strobe signals are either HDS by itself or HRD and HWR together.
8-14
DSP56367
MOTOROLA
Host Interface (HDI08) HDI08 - DSP-Side Programmer's Model
8.5.6.11 HPCR Host Address Strobe Polarity (HASP) Bit 10 If the HASP bit is cleared, the address strobe (HAS) signal is an active low input, and the address on the host address/data bus is sampled when the HAS signal is low. If HASP is set, HAS is an active high address strobe input, and the address on the host address/data bus 8 is sampled when the HAS signal is high. 8.5.6.12 HPCR Host Multiplexed bus (HMUX) Bit 11 If the HMUX bit is set, the HDI08 latches the lower portion of a multiplexed address/data bus. In this mode the internal address line values of the host registers are taken from the internal latch. If HMUX is cleared, it indicates that the HDI08 is connected to a non-multiplexed type of bus, and the address lines are taken from the HDI08 input signals. 8.5.6.13 HPCR Host Dual Data Strobe (HDDS) Bit 12 If the HDDS bit is cleared, the HDI08 operates in the single strobe bus mode. In this mode, the bus has a single data strobe signal for both reads and writes. If HDDS is set, the HDI08 operates in the dual strobe bus mode. In this mode, the bus has two separate data strobes, one for data reads, the other for data writes. See Figure 8-7 and Figure 8-8 for more information on the two types of buses.
HRW HDS In the single strobe bus mode, the HDS (Data-Strobe) signal qualifies the access, while the HRW (Read/Write) signal specifies the direction of the access.
Figure 8-7 Single strobe bus
Data HWR
Write data in Write cycle Read data out Read cycle
Data HRD
In the dual strobe bus mode, there are separate HRD and HWR signals that specify the access as being a read or write access, respectively.
Figure 8-8 Dual strobes bus
MOTOROLA
DSP56367
8-15
Host Interface (HDI08) HDI08 - DSP-Side Programmer's Model
8.5.6.14 HPCR Host Chip Select Polarity (HCSP) Bit 13 If the HCSP bit is cleared, the chip select (HCS) signal is configured as an active low input and the HDI08 is selected when the HCS signal is low. If HCSP is set, HCS is configured as an active high input and the HDI08 is selected when the HCS signal is high. This bit is ignored in the multiplexed mode. 8.5.6.15 HPCR Host Request Polarity (HRP) Bit 14 The HRP bit controls the polarity of the host request signals. In the single host request mode (HDRQ=0 in the ICR), if HRP is cleared and host requests are enabled (HREN=1 and HEN=1 in the HPCR), the HOREQ signal is an active low output. If HRP is set and host requests are enabled, the HOREQ signal is an active high output. In the double host request mode (HDRQ=1 in the ICR), if HRP is cleared and host requests are enabled (HREN=1 and HEN=1 in the HPCR), the HTRQ and HRRQ signals are active low outputs. If HRP is set and host requests are enabled, the HTRQ and HRRQ signals are active high outputs. 8.5.6.16 HPCR Host Acknowledge Polarity (HAP) Bit 15 If the HAP bit is cleared, the host acknowledge (HACK) signal is configured as an active low input, and the HDI08 drives the contents of the HIVR register onto the host bus when the HACK signal is low. If HAP is set, HACK is configured as an active high input, and the HDI08 outputs the contents of the HIVR register when the HACK signal is high.
8.5.7
DATA DIRECTION REGISTER (HDDR)
The HDDR controls the direction of the data flow for each of the HDI08 pins configured as GPIO. Even when the HDI08 is used as the host interface, some of its unused signals may be configured as GPIO pins. For information on the HDI08 GPIO configuration options, see Section 8.6.8. If bit DRxx is set, the corresponding HDI08 pin is configured as an output signal. If bit DRxx is cleared, the corresponding HDI08 pin is configured as an input signal. See Table 8-6. Figure 8-9 Host Data Direction Register (HDDR) (X:$FFFFC8)
15 DR15 14 DR14 13 DR13 12 DR12 11 DR11 10 DR10 9 DR9 8 DR8 7 DR7 6 DR6 5 DR5 4 DR4 3 DR3 2 DR2 1 DR1 0 DR0
8-16
DSP56367
MOTOROLA
Host Interface (HDI08) HDI08 - DSP-Side Programmer's Model
8.5.8
HOST DATA REGISTER (HDR)
The HDR register holds the data value of the corresponding bits of the HDI08 pins which are configured as GPIO pins. The functionality of the Dxx bit depends on the corresponding HDDR bit (DRxx). See Table 8-6. Figure 8-10 Host Data Register (HDR) (X:$FFFFC9)
15 D15 14 D14 13 D13 12 D12 11 D11 10 D10 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0
Table 8-6 HDR and HDDR Functionality
HDDR HDR Dxx DRxx GPIO pina 0 1 Read only bit. The value read is the binary value of the pin. The corresponding pin is configured as an input. Read/write bit. The value written is the value read. The corresponding pin is configured as an output, and is driven with the data written to Dxx. non-GPIO pina Read only bit. Does not contain significant data. Read/write bit. The value written is the value read.
a.Defined by the selected configuration
8.5.9
DSP-SIDE REGISTERS AFTER RESET
Table 8-7 shows the results of the four reset types on the bits in each of the HDI08 registers accessible by the DSP core. The hardware reset (HW) is caused by the RESET signal. The software reset (SW) is caused by executing the RESET instruction. The individual reset (IR)
MOTOROLA
DSP56367
8-17
Host Interface (HDI08) HDI08 - DSP-Side Programmer's Model
is caused by clearing the HEN bit (HPCR bit 6). The stop reset (ST) is caused by executing the STOP instruction. Table 8-7 DSP-Side Registers after Reset
Reset Type Register Name Register Data HW Reset 0 0 0 0 1 0 0 $80 0 -- empty empty SW Reset 0 0 0 0 1 0 0 $80 0 -- empty empty IR Reset -- -- -- 0 1 0 -- -- -- -- empty empty ST Reset -- -- -- 0 1 0 -- -- -- -- empty empty
HCR HPCR HSR
All bits All bits HF[1:0] HCP HTDE HRDF DMA
HBAR HDDR HDR HORX HOTX
BA[10:3] DR[15:0] D[15:0] HORX[23:0] HOTX[23:0]
Note: A long dash (--) denotes that the register value is not affected by the specified reset.
8.5.10
HOST INTERFACE DSP CORE INTERRUPTS
The HDI08 may request interrupt service from either the DSP core or the host processor. The DSP core interrupts are internal and do not require the use of an external interrupt pin. When the appropriate interrupt enable bit in the HCR is set, an interrupt condition caused by the host processor sets the appropriate bit in the HSR, generating an interrupt request to the DSP core. The DSP core acknowledges interrupts caused by the host processor by jumping to the appropriate interrupt service routine. The three possible interrupts are as follows: * * * Host command Transmit data register empty Receive data register full
Although there is a set of vectors reserved for host command use, the host command can access any interrupt vector in the interrupt vector table. The DSP interrupt service routine
8-18
DSP56367
MOTOROLA
Host Interface (HDI08) HDI08 - External Host Programmer's Model
must read or write the appropriate HDI08 register (clearing HRDF or HTDE, for example) to clear the interrupt. In the case of host command interrupts, the interrupt acknowledge from the DSP core program controller clears the pending interrupt condition. Figure 8-11 illustrates the HSR-HCR operation.
ENABLE 15 0 HF3 HF2 HCIE HTIE HRIE HCR DSP CORE INTERRUPTS
X:HCR
RECIEVE DATA FULL
TRANSMIT DATA EMPTY
HOST COMMAND
15
0 HF1 HF0 HCP HTDE HRDF HSR
X:HSR
STATUS
Figure 8-11 HSR-HCR Operation
8.6
HDI08 - EXTERNAL HOST PROGRAMMER'S MODEL
The HDI08 has been designed to provide a simple, high speed interface to a host processor. To the host bus, the HDI08 appears to be eight byte-wide registers. Separate transmit and receive data registers are double-buffered to allow the DSP core and host processor to transfer data efficiently at high speed. The host may access the HDI08 asynchronously by using polling techniques or interrupt-based techniques. The HDI08 appears to the host processor as a memory-mapped peripheral occupying 8 bytes in the host processor address space (See Table 8-8). The eight HDI08 include the following: * * * A control register (ICR) A status register (ISR) Three data registers (RXH/TXH, RXM/TXM and RXL/TXL)
MOTOROLA
DSP56367
8-19
Host Interface (HDI08) HDI08 - External Host Programmer's Model
*
Two vector registers (IVR and CVR)
These registers can be accessed only by the host processor. Host processors may use standard host processor instructions (e.g., byte move) and addressing modes to communicate with the HDI08 registers. The HDI08 registers are aligned so that 8-bit host processors can use 8/16/24-bit load and store instructions for data transfers. The HOREQ/HTRQ and HACK/HRRQ handshake flags are provided for polled or interrupt-driven data transfers with the host processor. Because the DSP interrupt response, most host microprocessors can load or store data at their maximum programmed I/O instruction rate without testing the handshake flags for each transfer. If full handshake is not needed, the host processor can treat the DSP as a fast device, and data can be transferred between the host processor and the DSP at the fastest host processor data rate. One of the most innovative features of the host interface is the host command feature. With this feature, the host processor can issue vectored interrupt requests to the DSP core. The host may select any of 128 DSP interrupt routines to be executed by writing a vector address register in the HDI08. This flexibility allows the host programmer to execute up to 128 pre-programmed functions inside the DSP. For example, host interrupts can allow the host processor to read or write DSP registers (X, Y, or program memory locations), force interrupt handlers (e.g. IRQA, IRQB, etc. interrupt routines), and perform control and debugging operations if interrupt routines are implemented in the DSP to perform these tasks. Table 8-8 HDI08 Host Side Register Map
Host Address 0 1 2 3 4 5 6 7 Big Endian HLEND=0 ICR CVR ISR IVR 00000000 RXH/TXH RXM/TXM RXL/TXL Little Endian HLEND=1 ICR CVR ISR IVR 00000000 RXL/TXL RXM/TXM RXH/TXH Receive/Transmit Bytes Function Interface Control Command Vector Interface Status Interrupt Vector Unused
Host Data Bus H0 - H7
Host Data Bus H0 - H7
Note: The RXH/TXH register is always mapped to the most significant byte of the DSP word.
8-20
DSP56367
MOTOROLA
Host Interface (HDI08) HDI08 - External Host Programmer's Model
8.6.1
INTERFACE CONTROL REGISTER (ICR)
The ICR is an 8-bit read/write control register used by the host processor to control the HDI08 interrupts and flags. The ICR cannot be accessed by the DSP core. The ICR is a read/write register, which allows the use of bit manipulation instructions on control register bits. The control bits are described in the following paragraphs. Bits 2, 5 and 6 of the ICR are affected by the condition of HDM[2:0] (HCR bits 5-7), as shown in Figure 8-12. Figure 8-12 Interface Control Register (ICR)
7 For HDM[2:0]=000 For HDM[2:0]=100 For HDM1=1 and/or HDM0=1 INIT INIT INIT HM1 HDM1 6 5 HLEND HM0 HDM0 4 HF1 HF1 HF1 3 HF0 HF0 HF0 2 HDRQ 1 TREQ TREQ TREQ 0 RREQ RREQ RREQ
HDM[1:0] - These read-only bits reflect the value of the HDM[1:0] bits in the HCR. - Reserved bit. Read as 0. Should be written with 0 for future compatibility.
8.6.1.1 ICR Receive Request Enable (RREQ) Bit 0 In interrupt mode (HDM[2:0]=000 or HM[1:0]=00), RREQ is used to enable host receive data requests via the host request (HOREQ or HRRQ) signal when the receive data register full (RXDF) status bit in the ISR is set. If RREQ is cleared, RXDF requests are disabled. If RREQ is set, the host request signal (HOREQ or HRRQ) is asserted if RXDF is set. In the DMA modes where HDM[2:0]=100 and (HM10 or HM00), RREQ must be set and TREQ must be cleared to direct DMA transfers from DSP to host. In the other DMA modes, RREQ is ignored. Table 8-9 summarizes the effect of RREQ and TREQ on the HOREQ, HTRQ and HRRQ signals. 8.6.1.2 ICR Transmit Request Enable (TREQ) Bit 1 In interrupt mode (HDM[2:0]=000 or HM[1:0]=00), TREQ is used to enable host transmit data requests via the host request (HOREQ or HTRQ) signal when the transmit data register empty (TXDE) status bit in the ISR is set. If TREQ is cleared, TXDE requests are disabled. If TREQ is set, the host request signal (HOREQ or HTRQ) is asserted if TXDE is set.
MOTOROLA
DSP56367
8-21
Host Interface (HDI08) HDI08 - External Host Programmer's Model
In the DMA modes where HDM[2:0]=100 and (HM10 or HM00), TREQ must be set and RREQ must be cleared to direct DMA transfers from host to DSP. In the other DMA modes, TREQ is ignored. Table 8-9 summarizes the effect of RREQ and TREQ on the HOREQ, HTRQ and HRRQ signals. Table 8-9 TREQ RREQ Interrupt Mode (HDM[2:0]=000 or HM[1:0]=00)
HDRQ=0 TREQ RREQ HOREQ signal 0 0 1 1 0 1 0 1 No Interrupts (Polling) RXDF Request (Interrupt) TXDE Request (Interrupt) RXDF and TXDE Requests (Interrupts) HTRQ signal No Interrupts (Polling) No Interrupts (Polling) TXDE Request (Interrupt) TXDE Request (Interrupt) HRRQ signal No Interrupts (Polling) RXDF Request (Interrupt) No Interrupts (Polling) RXDF Request (Interrupt) HDRQ=1
Table 8-10 TREQ RREQ DMA Mode (HM10 or HM00)
TREQ RREQ HDRQ=0 HOREQ signal 0 0 1 1 0 1 0 1 No DMA request DSP to Host Request (RX) Host to DSP Request (TX) Reserved HTRQ signal No DMA request No DMA request Host to DSP Request (TX) Reserved HDRQ=1 HRRQ signal No DMA request DSP to Host Request (RX) No DMA request Reserved
8.6.1.3 ICR Double Host Request (HDRQ) Bit 2 The HDRQ bit determines the functions of the HOREQ/HTRQ and HACK/HRRQ signals as shown in Table 8-11. Table 8-11 HDRQ
HDRQ 0 1 HOREQ/HTRQ pin HOREQ signal HTRQ signal HACK/HRRQ pin HACK signal HRRQ signal
8.6.1.4 ICR Host Flag 0 (HF0) Bit 3 The HF0 bit is used as a general purpose flag for host-to-DSP communication. HF0 may be set or cleared by the host processor and cannot be changed by the DSP core. HF0 is reflected in the HSR on the DSP side of the HDI08.
8-22
DSP56367
MOTOROLA
Host Interface (HDI08) HDI08 - External Host Programmer's Model
8.6.1.5 ICR Host Flag 1 (HF1) Bit 4 The HF1 bit is used as a general purpose flag for host-to-DSP communication. HF1 may be set or cleared by the host processor and cannot be changed by the DSP core. HF1 is reflected in the HSR on the DSP side of the HDI08. 8.6.1.6 ICR Host Little Endian (HLEND) Bit 5 If the HLEND bit is cleared, the HDI08 can be accessed by the host in big endian byte order. If set, the HDI08 can be accessed by the host in little endian byte order. If the HLEND bit is cleared, the RXH/TXH register is located at address $5, the RXM/TXM register is located at address $6, and the RXL/TXL register is located at address $7. If the HLEND bit is set, the RXH/TXH register is located at address $7, the RXM/TXM register is located at address $6, and the RXL/TXL is located at address $5. See Table 8-8 for an illustration of the effect of HLEND. The HLEND function is available only if HDM[2:0]=000 in the host control register (HCR). When HLEND is available, the ICR bit 6 has no function and should be regarded as reserved. 8.6.1.7 ICR Host Mode Control (HM1 and HM0 bits) Bits 5-6 Bits 6 and 5 function as read/write HM[1:0] bits only when the HCR bits HDM[2:0]=100 (See Table 8-5). The HM0 and HM1 bits select the transfer mode of the HDI08, as shown in Table 8-12. Table 8-12 Host Mode Bit Definition
HM1 0 0 1 1 HM0 0 1 0 1 Mode Interrupt Mode (DMA Off) DMA Mode (24 Bit) DMA Mode (16 Bit) DMA Mode (8 Bit)
When both HM1 and HM0 are cleared, the DMA mode is disabled and the interrupt mode is enabled. In interrupt mode, the TREQ and RREQ control bits are used for host processor interrupt control via the external HOREQ output signal, and the HACK input signal is used for the MC68000 Family vectored interrupt acknowledge input. When HM1 and/or HM0 are set, they enable the DMA mode and determine the size of the DMA word to be transferred. In the DMA mode, the HOREQ signal is used to request DMA transfers, the TREQ and RREQ bits select the direction of DMA transfers (see Table 8-10), and the HACK input signal is used as a DMA transfer acknowledge input. If the DMA direction is from DSP to host, the contents of the selected register are enabled onto the host data bus when HACK is asserted. If the DMA direction is from host to DSP, the selected register is written from the host data bus when HACK is asserted.
MOTOROLA
DSP56367
8-23
Host Interface (HDI08) HDI08 - External Host Programmer's Model
The size of the DMA word to be transferred is determined by the DMA control bits, HM0 and HM1. The HDI08 host side data register selected during a DMA transfer is determined by a 2-bit address counter, which is preloaded with the value in HM1 and HM0. The address counter substitutes for the HA1 and HA0 host address signals of the HDI08 during a DMA transfer. The host address signal HA2 is forced to one during each DMA transfer. The address counter can be initialized with the INIT bit feature. After each DMA transfer on the host data bus, the address counter is incremented to the next data register. When the address counter reaches the highest register (RXL or TXL), the address counter is not incremented but is loaded with the value in HM1 and HM0. This allows 8-, 16- or 24-bit data to be transferred in a circular fashion and eliminates the need for the DMA controller to supply the HA2, HA1, and HA0 address signals. For 16- or 24-bit data transfers, the DSP CPU interrupt rate is reduced by a factor of 2 or 3, respectively, from the host request rate - i.e., for every two or three host processor data transfers of one byte each, there is only one 24-bit DSP CPU interrupt. If either HDM1 or HDM0 in the HCR register are set, bits 6 and 5 become read-only bits that reflect the value of HDM[1:0]. 8.6.1.8 ICR Initialize Bit (INIT) Bit 7 The INIT bit is used by the host processor to force initialization of the HDI08 hardware. During initialization, the HDI08 transmit and receive control bits are configured. Using the INIT bit to initialize the HDI08 hardware may or may not be necessary, depending on the software design of the interface. The type of initialization done when the INIT bit is set depends on the state of TREQ and RREQ in the HDI08. The INIT command, which is local to the HDI08, is designed to conveniently configure the HDI08 into the desired data transfer mode. The effect of the INIT command is described in Table 8-13. When the host sets the INIT bit, the HDI08 hardware executes the INIT command. The interface hardware clears the INIT bit after the command has been executed. Table 8-13 INIT Command Effect
TREQ 0 0 1 1 RREQ 0 1 0 1 INIT=0 INIT=0; RXDF=0; HTDE=1 INIT=0; TXDE=1; HRDF=0 INIT=0; RXDF=0; HTDE=1; TXDE=1; HRDF=0 After INIT Execution Transfer Direction Initialized None DSP to Host Host to DSP Host to/from DSP
8-24
DSP56367
MOTOROLA
Host Interface (HDI08) HDI08 - External Host Programmer's Model
8.6.2
COMMAND VECTOR REGISTER (CVR)
The CVR is used by the host processor to cause the DSP core to execute an interrupt. The host command feature is independent of any of the data transfer mechanisms in the HDI08. It can be used to invoke execution of any of the 128 possible interrupt routines in the DSP core. Figure 8-13 Command Vector Register (CVR)
7 HC 6 HV6 5 HV5 4 HV4 3 HV3 2 HV2 1 HV1 0 HV0
8.6.2.1 CVR Host Vector (HV[6:0]) Bits 0-6 The seven HV bits select the host command interrupt address to be used by the host command interrupt logic. When the host command interrupt is recognized by the DSP interrupt control logic, the address of the interrupt routine taken is 2 HV. The host can write HC and HV in the same write cycle. The host processor can select the starting address of any of the 128 possible interrupt routines in the DSP by writing the interrupt routine address divided by 2 into the HV bits. The host processor can thus force execution of any of the existing interrupt handlers (IRQA, IRQB, etc.) and can use any of the reserved or otherwise unused addresses provided they have been pre-programmed in the DSP. HV[6:0] is set to $32 (vector location $0064) by hardware, software, individual and stop resets. 8.6.2.2 CVR Host Command Bit (HC) Bit 7 The HC bit is used by the host processor to handshake the execution of host command interrupts. Normally, the host processor sets HC to request the host command interrupt from the DSP core. When the host command interrupt is acknowledged by the DSP core, the HC bit is cleared by the HDI08 hardware. The host processor can read the state of HC to determine when the host command has been accepted. After setting HC, the host must not write to the CVR again until HC is cleared by the HDI08 hardware. Setting HC causes the host command pending (HCP) in the HSR to be set. The host can write to the HC and HV bits in the same write cycle.
8.6.3
INTERFACE STATUS REGISTER (ISR)
The ISR is an 8-bit read-only status register used by the host processor to interrogate the status and flags of the HDI08. The host processor can write to this address without affecting the internal state of the HDI08, which is useful if the user desires to access all of the HDI08
MOTOROLA
DSP56367
8-25
Host Interface (HDI08) HDI08 - External Host Programmer's Model
registers by stepping through the HDI08 addresses. The ISR cannot be accessed by the DSP core. The ISR bits are described in the following paragraphs. Figure 8-14 Interface Status Register (ISR)
7 HREQ 6 5 4 HF3 3 HF2 2 TRDY 1 TXDE 0 RXDF
- Reserved bit. Read as 0. Should be written with 0 for future compatibility.
8.6.3.1 ISR Receive Data Register Full (RXDF) Bit 0 The RXDF bit indicates that the receive byte registers (RXH:RXM:RXL) contain data from the DSP core and may be read by the host processor. RXDF is set when the contents of HOTX is transferred to the receive byte registers. RXDF is cleared when the receive data (RXL or RXH according to HLEND bit) register is read by the host processor. RXDF can be cleared by the host processor using the initialize function. RXDF may be used to assert the external HOREQ signal if the RREQ bit is set. Regardless of whether the RXDF interrupt is enabled, RXDF indicates whether the RX registers are full and data can be latched out (so that polling techniques may be used by the host processor). 8.6.3.2 ISR Transmit Data Register Empty (TXDE) Bit 1 The TXDE bit indicates that the transmit byte registers (TXH:TXM:TXL) are empty and can be written by the host processor. TXDE is set when the contents of the transmit byte registers are transferred to the HORX register. TXDE is cleared when the transmit (TXL or TXH according to HLEND bit) register is written by the host processor. TXDE can be set by the host processor using the initialize feature. TXDE may be used to assert the external HOREQ signal if the TREQ bit is set. Regardless of whether the TXDE interrupt is enabled, TXDE indicates whether the TX registers are full and data can be latched in (so that polling techniques may be used by the host processor). 8.6.3.3 ISR Transmitter Ready (TRDY) Bit 2 The TRDY status bit indicates that TXH:TXM:TXL and the HORX registers are empty. TRDY=TXDE * HRDF If TRDY is set, the data that the host processor writes to TXH:TXM:TXL is immediately transferred to the DSP side of the HDI08. This feature has many applications. For example, if the host processor issues a host command which causes the DSP core to read the HORX, the host processor can be guaranteed that the data it just transferred to the HDI08 is what is being received by the DSP core. 8.6.3.4 ISR Host Flag 2 (HF2) Bit 3 The HF2 bit in the ISR indicates the state of host flag 2 in the HCR on the DSP side. HF2 can be changed only by the DSP (see Section 8.5.3.4).
8-26
DSP56367
MOTOROLA
Host Interface (HDI08) HDI08 - External Host Programmer's Model
8.6.3.5 ISR Host Flag 3 (HF3) Bit 4 The HF3 bit in the ISR indicates the state of host flag 3 in the HCR on the DSP side. HF3 can be changed only by the DSP (see Section 8.5.3.4). 8.6.3.6 ISR Reserved Bits 5-6 These bits are reserved. They read as zero and should be written with zero for future compatibility. 8.6.3.7 ISR Host Request (HREQ) Bit 7 The HREQ bit indicates the status of the external host request output signal (HOREQ) if HDRQ is cleared. If HDRQ is set, it indicates the status of the external transmit and receive request output signals (HTRQ and HRRQ). Table 8-14 Host Request Status (HREQ)
HREQ 0 Status [HDRQ=0] HOREQ deasserted; no host processor interrupt is requested Status [HDRQ=1] HTRQ and HRRQ deasserted; no host processor interrupts are requested HTRQ and/or HRRQ asserted; host processor interrupts are requested
1
HOREQ asserted; a host processor interrupt is requested
The HREQ bit may be set from either or both of two conditions - either the receive byte registers are full or the transmit byte registers are empty. These conditions are indicated by the ISR RXDF and TXDE status bits, respectively. If the interrupt source has been enabled by the associated request enable bit in the ICR, HREQ is set if one or more of the two enabled interrupt sources is set.
8.6.4
INTERRUPT VECTOR REGISTER (IVR)
The IVR is an 8-bit read/write register which typically contains the interrupt vector number used with MC68000 Family processor vectored interrupts. Only the host processor can read and write this register. The contents of IVR are placed on the host data bus (H0-H7) when both the HOREQ and HACK signals are asserted. The contents of this register are initialized to $0F by hardware or software reset, which corresponds to the uninitialized interrupt vector in the MC68000 Family. Figure 8-15 Interrupt Vector Register (IVR)
7 IV7 6 IV6 5 IV5 4 IV4 3 IV3 2 IV2 1 IV1 0 IV0
MOTOROLA
DSP56367
8-27
Host Interface (HDI08) HDI08 - External Host Programmer's Model
8.6.5
RECEIVE BYTE REGISTERS (RXH:RXM:RXL)
The receive byte registers are viewed by the host processor as three 8-bit read-only registers. These registers are the receive high register (RXH), the receive middle register (RXM) and the receive low register (RXL). They receive data from the high, middle and low bytes, respectively, of the HOTX register and are selected by the external host address inputs (HA2, HA1 and HA0) during a host processor read operation. The memory locations of the receive byte registers are determined by the HLEND bit in the ICR. If the HLEND bit is set, the RXH is located at address $7, RXM at $6 and RXL at $5. If the HLEND bit is cleared, the RXH is located at address $5, RXM at $6 and RXL at $7. When data is transferred from the HOTX register to the receive byte registers, the receive data register full (RXDF) bit is set. The host processor may program the RREQ bit to assert the external HOREQ/HRRQ signal when RXDF is set. This indicates that the HDI08 has a full word (either 8, 16 or 24 bits) for the host processor. When the host reads the receive byte register at host address $7, the RXDF bit is cleared.
8.6.6
TRANSMIT BYTE REGISTERS (TXH:TXM:TXL)
The transmit byte registers are viewed as three 8-bit write-only registers by the host processor. These registers are the transmit high register (TXH), the transmit middle register (TXM) and the transmit low register (TXL). These registers send data to the high, middle and low bytes, respectively, of the HORX register and are selected by the external host address inputs (HA2, HA1 and HA0) during a host processor write operation. If the HLEND bit in the ICR is cleared, the TXH is located at address $5, TXM at $6 and TXL at $7. If the HLEND bit in the ICR is set, the TXH is located at address $7, TXM at $6 and TXL at $5. Data may be written into the transmit byte registers when the transmit data register empty (TXDE) bit is set. The host processor may program the TREQ bit to assert the external HOREQ/HTRQ signal when TXDE is set. This informs the host processor that the transmit byte registers are empty. Writing to the data register at host address $7 clears the TXDE bit. The contents of the transmit byte registers are transferred as 24-bit data to the HORX register when both TXDE and the HRDF bit are cleared. This transfer operation sets TXDE and HRDF.
8-28
DSP56367
MOTOROLA
Host Interface (HDI08) HDI08 - External Host Programmer's Model
8.6.7
HOST SIDE REGISTERS AFTER RESET
Table 8-15 shows the result of the four kinds of reset on bits in each of the HDI08 registers seen by the host processor. The hardware reset (HW) is caused by asserting the RESET signal. The software reset (SW) is caused by executing the RESET instruction. The individual reset (IR) is caused by clearing the HEN bit in the HPCR register. The stop reset (ST) is caused by executing the STOP instruction. Table 8-15 Host Side Registers After Reset
Reset Type Register Name Register Data HW Reset 0 0 $32 0 0 1 1 0 $0F empty empty SW Reset 0 0 $32 0 0 1 1 0 $0F empty empty IR Reset -- 0 -- 1 if TREQ is set; 0 otherwise -- 1 1 0 -- empty empty ST Reset -- 0 -- 1 if TREQ is set; 0 otherwise -- 1 1 0 -- empty empty
ICR CVR
All Bits HC HV[6:0]
ISR
HREQ HF3-HF2 TRDY TXDE RXDF
IVR RX TX
IV[7:0] RXH:RXM:RXL TXH:TXM:TXL
Note: A long dash (--) denotes that the register value is not affected by the specified reset.
8.6.8
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
When configured as general-purpose I/O, the HDI08 is viewed by the DSP core as memory-mapped registers (see Section 8.5, "HDI08 - DSP-Side Programmer's Model") that control up to 16 I/O pins. The software and hardware resets clear all DSP-side control registers and configure the HDI08 as GPIO with all 16 signals disconnected. External circuitry connected to the HDI08 may need external pull-up/pull-down resistors until the signals are configured for operation. The registers cleared are the HPCR, HDDR and HDR. Selection between GPIO and HDI08 is made by clearing HPCR bits 6 through 1 for GPIO or setting these bits for HDI08 functionality. If the HDI08 is in GPIO mode, the HDDR configures each corresponding signal in the HDR as an input signal if the HDDR bit is cleared or as an output signal if the HDDR bit is set (see Section 8.5.7 and Section 8.5.8).
MOTOROLA
DSP56367
8-29
Host Interface (HDI08) Servicing The Host Interface
8.7
SERVICING THE HOST INTERFACE
The HDI08 can be serviced by using one of the following protocols: * * Polling, Interrupts
8.7.1
HDI08 HOST PROCESSOR DATA TRANSFER
To the host processor, the HDI08 appears as a contiguous block of static RAM. To transfer data between itself and the HDI08, the host processor performs the following steps: 1. Asserts the HDI08 address to select the register to be read or written. 2. Selects the direction of the data transfer. If it is writing, the host processor drives the data on the bus. 3. Strobes the data transfer.
8.7.2
POLLING
In the polling mode of operation, the HOREQ/HTRQ signal is not connected to the host processor and HACK must be deasserted to ensure IVR data is not being driven on H0-H7 when other registers are being polled. The host processor first performs a data read transfer to read the ISR register.This allows the host processor to assess the status of the HDI08: 1. If RXDF=1, the receive byte registers are full and therefore a data read can be performed by the host processor. 2. If TXDE=1, the transmit byte registers are empty. A data write can be performed by the host processor. 3. If TRDY=1, the transmit byte registers and the receive data register on the DSP side are empty. Data written by the host processor is transferred directly to the DSP side. 4. If (HF2 * HF3) 0, depending on how the host flags have been defined, may indicate an application-specific state within the DSP core has been reached. Intervention by the host processor may be required.
8-30
DSP56367
MOTOROLA
Host Interface (HDI08) Servicing The Host Interface
5. If HREQ=1, the HOREQ/HTRQ/HRRQ signal has been asserted, and the DSP is requesting the attention of the host processor. One of the previous four conditions exists. After the appropriate data transfer has been made, the corresponding status bit is updated to reflect the transfer. If the host processor has issued a command to the DSP by writing the CVR and setting the HC bit, it can read the HC bit in the CVR to determine when the command has been accepted by the interrupt controller in the DSP core. When the command has been accepted for execution, the HC bit is cleared by the interrupt controller in the DSP core.
STATUS
7 0 0 0 HF3 HF2 TRDY TXDE RXDF ISR
$2
HREQ
Host Request ASSERTED
HRRQ HOREQ HTRQ
7
0 INIT 0 HLEND HF1 HF0 HDRQ TREQ RREQ ICR
$0
ENABLE
Figure 8-16 HDI08 Host Request Structure
8.7.3
SERVICING INTERRUPTS
If either the HOREQ/HTRQ or the HRRQ signal or both are connected to the host processor interrupt inputs, the HDI08 can request service from the host processor by asserting one of these signals. The HOREQ/HTRQ and/or the HRRQ signal is asserted when TXDE=1 and/or RXDF=1 and the corresponding enable bit (TREQ or RREQ, respectively) is set. This is depicted in Figure 8-16. HOREQ/HTRQ and HRRQ are normally connected to the host processor maskable interrupt inputs. The host processor acknowledges host interrupts by executing an interrupt service routine. The host processor can test RXDF and TXDE to determine the interrupt source. The host processor interrupt service routine must read or write the appropriate HDI08 data register to clear the interrupt. HOREQ/HTRQ and/or HRRQ is deasserted under the following conditions:
MOTOROLA
DSP56367
8-31
Host Interface (HDI08) Servicing The Host Interface
* *
The enabled request is cleared or masked The DSP is reset.
If the host processor is a member of the MC68000 family, there is no need for the additional step when the host processor reads the ISR to determine how to respond to an interrupt generated by the DSP. Instead, the DSP automatically sources the contents of the IVR on the data bus when the host processor acknowledges the interrupt by asserting HACK. The contents of the IVR are placed on the host data bus while HOREQ and HACK are simultaneously asserted. The IVR data tells the MC680XX host processor which interrupt routine to execute to service the DSP.
8-32
DSP56367
MOTOROLA
SECTION
9
SERIAL HOST INTERFACE
9.1 INTRODUCTION
The Serial Host Interface (SHI) is a serial I/O interface that provides a path for communication and program/coefficient data transfers between the DSP and an external host processor. The SHI can also communicate with other serial peripheral devices. The SHI supports two well-known and widely used synchronous serial buses: the Motorola Serial Peripheral Interface (SPI) bus and the Philips Inter-Integrated-Circuit Control (I2C) bus. The SHI supports either bus protocol as either a slave or a single-master device. To minimize DSP overhead, the SHI supports 8-bit, 16-bit and 24-bit data transfers. The SHI has a 1 or 10-word receive FIFO that permits receiving up to 30 bytes before generating a receive interrupt, reducing the overhead for data reception. When configured in the SPI mode, the SHI can perform the following functions: * * * * * * * * Identify its slave selection (in slave mode) Simultaneously transmit (shift out) and receive (shift in) serial data Directly operate with 8-, 16- and 24-bit words Generate vectored interrupts separately for receive and transmit events and update status bits Generate a separate vectored interrupt for a receive exception Generate a separate vectored interrupt for a bus-error exception Generate the serial clock signal (in master mode) Trigger DMA interrupts to service the transmit and receive events
When configured in the I2C mode, the SHI can perform the following functions: * * * * Detect/generate start and stop events Identify its slave (ID) address (in slave mode) Identify the transfer direction (receive/transmit) Transfer data byte-wise according to the SCL clock line
MOTOROLA
DSP56367
9-1
Serial Host Interface Serial Host Interface Internal Architecture
* * * * * * * *
Generate ACK signal following a byte receive Inspect ACK signal following a byte transmit Directly operate with 8-, 16- and 24-bit words Generate vectored interrupts separately for receive and transmit events and update status bits Generate a separate vectored interrupt for a receive exception Generate a separate vectored interrupt for a bus error exception Generate the clock signal (in master mode) Trigger DMA interrupts to service the transmit and receive events
9.2
SERIAL HOST INTERFACE INTERNAL ARCHITECTURE
The DSP views the SHI as a memory-mapped peripheral in the X data memory space. The DSP uses the SHI as a normal memory-mapped peripheral using standard polling or interrupt programming techniques and DMA transfers. Memory mapping allows DSP communication with the SHI registers to be accomplished using standard instructions and addressing modes. In addition, the MOVEP instruction allows interface-to-memory and memory-to-interface data transfers without going through an intermediate register. The DMA controller may be used to service the receive or transmit data path. The single master configuration allows the DSP to directly connect to dumb peripheral devices. For that purpose, a programmable baud-rate generator is included to generate the clock signal for serial transfers. The host side invokes the SHI for communication and data transfer with the DSP through a shift register that may be accessed serially using either the I2C or the SPI bus protocols. Figure 9-1 shows the SHI block diagram.
9-2
DSP56367
MOTOROLA
Serial Host Interface Characteristics Of The SPI Bus
Host Accessible
DSP Accessible DSP Global Data Bus HCKR HCSR Controller Logic HTX DSP DMA Data Bus
Clock Generator SCK/SCL
MISO/SDA
MOSI/HA0
Pin Control Logic
INPUT/OUTPUT Shift Register (IOSR)
SS/HA2
HREQ Slave Address Recognition Unit (SAR)
HRX (FIFO)
HSAR 24 BIT
AA0416
Figure 9-1 Serial Host Interface Block Diagram
9.3
CHARACTERISTICS OF THE SPI BUS
The SPI bus consists of two serial data lines (MISO and MOSI), a clock line (SCK), and a Slave Select line (SS). During an SPI transfer, a byte is shifted out one data pin while a different byte is simultaneously shifted in through a second data pin. It can be viewed as two 8-bit shift registers connected together in a circular manner, with one shift register on the master side and the other on the slave side. Thus the data bytes in the master device and slave device are exchanged. The MISO and MOSI data pins are used for transmitting and receiving serial data. When the SPI is configured as a master, MISO is the master data input line, and MOSI is the master data output line. When the SPI is configured as a slave device, MISO is the slave data output line, and MOSI is the slave data input line.
MOTOROLA
DSP56367
9-3
Serial Host Interface SHI Clock Generator
Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, the control bits in the HCKR select the appropriate clock rate, as well as the desired clock polarity and phase format (see Figure 9-6). The SS line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activity (i.e., they keep their MISO output pin in the high-impedance state). When the SHI is configured as an SPI master device, the SS line should be held high. If the SS line is driven low when the SHI is in SPI master mode, a bus error is generated (the HCSR HBER bit is set).
9.4
SHI CLOCK GENERATOR
The SHI clock generator generates the SHI serial clock if the interface operates in the master mode. The clock generator is disabled if the interface operates in the slave mode, except in I2C mode when the HCKFR bit is set in the HCKR register. When the SHI operates in the slave mode, the clock is external and is input to the SHI (HMST = 0). Figure 9-2 illustrates the internal clock path connections. It is the user's responsibility to select the proper clock rate within the range as defined in the I2C and SPI bus specifications.
HMST SHI Clock SCK/SCL Divide By 1 To Divide By 256 HMST = 0 Divide By 1 or 8 HMST = 1 CPHA, CPOL, HI2C Clock Logic SHI Controller
FOSC
Divide By 2
HDM0-HDM7
HRS
AA0417
Figure 9-2 SHI Clock Generator
9.5
SERIAL HOST INTERFACE PROGRAMMING MODEL
The Serial Host Interface programming model has two parts: * Host side--see Figure 9-3 below and Section 9.5.1
9-4
DSP56367
MOTOROLA
Serial Host Interface Serial Host Interface Programming Model
*
DSP side--see Figure 9-4 and Section 9.5.2 through Section 9.5.6 for detailed information.
23 0
IOSR
I/O Shift Register (IOSR)
AA0418
Figure 9-3 SHI Programming Model--Host Side
MOTOROLA
DSP56367
9-5
9-6
SHI I2C Slave Address Register (HSAR) X: $FFFF92 23 HA6 22 HA5 21 HA4 20 HA3 19 18 HA1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SHI Clock Control Register (HCKR) X: $FFFF90 23 22 21 20 19 18 17 16 15 14 13 HFM1 12 HFM0 11 10 HDM7 9 HDM6 8 HDM5 7 HDM4 6 HDM3 5 HDM2 4 HDM1 3 HDM0 2 HRS 1 CPOL 0 CPHA SHI Control/Status Register (HCSR) X: $FFFF91 23 22 HBUSY 21 HBER 20 HROE 19 HRFF 18 17 HRNE 16 15 HTDE 14 HTUE 13 12 11 HTIE 10 HBIE 9 HIDLE 8 HRQE1 7 HRQE0 6 5 4 3 2 HM0 1 HI2C 0 HEN HRIE1 HRIE0 HMST HFIFO HCKFR HM1
Serial Host Interface
Serial Host Interface Programming Model
Figure 9-4 SHI Programming Model--DSP Side
DSP56367 MOTOROLA
SHI Receive Data FIFO (HRX) (read only, X: $FFFF94) 23 HRX
0
FIFO (10 Words Deep)
SHI Transmit Data Register (HTX) (write only, X: $FFFF93) 23 HTX
0
Reserved bit, read as 0, should be written with 0 for future compatibility.
AA0419
Serial Host Interface Serial Host Interface Programming Model
The SHI interrupt vector table is shown in Table 9-1 and the exception priorities generated by the SHI are shown in Table 9-2. Table 9-1 SHI Interrupt Vectors
Program Address VBA:$0040 VBA:$0042 VBA:$0044 VBA:$0048 VBA:$004A VBA:$004C SHI Transmit Data SHI Transmit Underrun Error SHI Receive FIFO Not Empty SHI Receive FIFO Full SHI Receive Overrun Error SHI Bus Error Interrupt Source
Table 9-2 SHI Internal Interrupt Priorities
Priority Highest SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data Lowest SHI Receive FIFO Not Empty Interrupt
9.5.1
SHI INPUT/OUTPUT SHIFT REGISTER (IOSR)--HOST SIDE
The variable length Input/Output Shift Register (IOSR) can be viewed as a serial-to-parallel and parallel-to-serial buffer in the SHI. The IOSR is involved with every data transfer in both directions (read and write). In compliance with the I2C and SPI bus protocols, data is shifted in and out MSB first. In 8-bit data transfer modes, the most significant byte of the IOSR is used as the shift register. In 16-bit data transfer modes, the two most significant bytes become the shift register. In 24-bit transfer modes, the shift register uses all three bytes of the IOSR (see Figure 9-5).
MOTOROLA
DSP56367
9-7
Serial Host Interface Serial Host Interface Programming Model
Note:
The IOSR cannot be accessed directly either by the host processor or by the DSP. It is fully controlled by the SHI controller logic.
23
16
15
8
7
0
Mode of Operation
8-Bit Data Mode
16-Bit Data Mode
24-Bit Data Mode
Stops Data When Data Mode is Selected Passes Data When Data Mode is Selected
AA0420
Figure 9-5 SHI I/O Shift Register (IOSR)
9.5.2
SHI HOST TRANSMIT DATA REGISTER (HTX)--DSP SIDE
The host transmit data register (HTX) is used for DSP-to-Host data transfers. The HTX register is 24 bits wide. Writing to the HTX register by DSP core instructions or by DMA transfers clears the HTDE flag. The DSP may program the HTIE bit to cause a host transmit data interrupt when HTDE is set (See 9.5.6.10 HCSR Transmit-Interrupt Enable (HTIE)--Bit 11 on page Section 9-16.) Data should not be written to the HTX until HTDE is set in order to prevent overwriting the previous data. HTX is reset to the empty state when in stop mode and during hardware reset, software reset, and individual reset. In the 8-bit data transfer mode the most significant byte of the HTX is transmitted; in the 16-bit mode the two most significant bytes, and in the 24-bit mode all the contents of HTX is transferred.
9.5.3
SHI HOST RECEIVE DATA FIFO (HRX)--DSP SIDE
The 24-bit host receive data FIFO (HRX) is a 10-word deep, First-In-First-Out (FIFO) register used for Host-to-DSP data transfers. The serial data is received via the shift register and then loaded into the HRX. In the 8-bit data transfer mode, the most significant byte of the shift register is transferred to the HRX (the other bits are cleared); in the 16-bit mode the two most significant bytes are transferred (the least significant byte is cleared), and in the 24-bit mode, all 24 bits are transferred to the HRX. The HRX may be read by the DSP while the FIFO is
9-8
DSP56367
MOTOROLA
Serial Host Interface Serial Host Interface Programming Model
being loaded from the shift register. Reading all data from HRX clears the HRNE flag. The HRX may be read by DSP core instructions or by DMA transfers. The HRX FIFO is reset to the empty state when the chip is in stop mode, and during hardware reset, software reset, and individual reset.
9.5.4
SHI SLAVE ADDRESS REGISTER (HSAR)--DSP SIDE
The 24-bit slave address register (HSAR) is used when the SHI operates in the I2C slave mode and is ignored in the other operational modes. HSAR holds five bits of the 7-bit slave device address. The SHI also acknowledges the general call address specified by the I2C protocol (eight zeroes comprising a 7-bit address and a R/W bit), but treats any following data bytes as regular data. That is, the SHI does not differentiate between its dedicated address and the general call address. HSAR cannot be accessed by the host processor. 9.5.4.1 HSAR Reserved Bits--Bits 19, 17-0 These bits are reserved. They read as zero and should be written with zero for future compatibility. 9.5.4.2 HSAR I2C Slave Address (HA[6:3], HA1)--Bits 23-20,18 Part of the I2C slave device address is stored in the read/write HA[6:3], HA1 bits of HSAR. The full 7-bit slave device address is formed by combining the HA[6:3], HA1 bits with the HA0 and HA2 pins to obtain the HA[6:0] slave device address. The full 7-bit slave device address is compared to the received address byte whenever an I2C master device initiates an I2C bus transfer. During hardware reset or software reset, HA[6:3] = 1011 and HA1 is cleared; this results in a default slave device address of 1011[HA2]0[HA0].
9.5.5
SHI CLOCK CONTROL REGISTER (HCKR)--DSP SIDE
The HCKR is a 24-bit read/write register that controls SHI clock generator operation. The HCKR bits should be modified only while the SHI is in the individual reset state (HEN = 0 in the HCSR). For proper SHI clock setup, please consult the datasheet. The programmer should not use the combination HRS = 1 and HDM[7:0] = 00000000, since it may cause synchronization problems and improper operation (it is an illegal combination). The HCKR bits are cleared during hardware reset or software reset, except for CPHA, which is set. The HCKR is not affected by the stop state. The HCKR bits are described in the following paragraphs.
MOTOROLA
DSP56367
9-9
Serial Host Interface Serial Host Interface Programming Model
9.5.5.1 Clock Phase and Polarity (CPHA and CPOL)--Bits 1-0 The Clock Phase (CPHA) bit controls the relationship between the data on the master-in-slave-out (MISO) and master-out-slave-in (MOSI) pins and the clock produced or received at the SCK pin. The CPOL bit determines the clock polarity (1 = active-high, 0 = active-low). The clock phase and polarity should be identical for both the master and slave SPI devices. CPHA and CPOL are functional only when the SHI operates in the SPI mode, and are ignored in the I2C mode. The CPHA bit is set and the CPOL bit is cleared during hardware reset and software reset. The programmer may select any of four combinations of serial clock (SCK) phase and polarity when operating in the SPI mode (See Figure 9-6).
SS SCK SCK (CPOL = 0, CPHA = 0) (CPOL = 0, CPHA = 1)
SCK
(CPOL = 1, CPHA = 0)
SCK MISO/ MOSI
(CPOL = 1, CPHA = 1)
MSB
6
5
4
3
2
1
LSB
Internal Strobe for Data Capture
AA0421
Figure 9-6 SPI Data-To-Clock Timing Diagram If CPOL is cleared, it produces a steady-state low value at the SCK pin of the master device whenever data is not being transferred. If the CPOL bit is set, it produces a high value at the SCK pin of the master device whenever data is not being transferred. CPHA is used with the CPOL bit to select the desired clock-to-data relationship. The CPHA bit, in general, selects the clock edge that captures data and allows it to change states. It has its greatest impact on the first bit transmitted (MSB) in that it does or does not allow a clock transition before the data capture edge.
9-10
DSP56367
MOTOROLA
Serial Host Interface Serial Host Interface Programming Model
When the SHI is in slave mode and CPHA = 0, the SS line must be deasserted and asserted by the external master between each successive word transfer. SS must remain asserted between successive bytes within a word. The DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. However, the data is transferred to the shift register for transmission only when SS is deasserted. HTDE is set when the data is transferred from HTX to the shift register. When the SHI is in slave mode and CPHA = 1, the SS line may remain asserted between successive word transfers. The SS must remain asserted between successive bytes within a word. The DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. The HTX data is transferred to the shift register for transmission as soon as the shift register is empty. HTDE is set when the data is transferred from HTX to the shift register. When the SHI is in master mode and CPHA = 0, the DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. The data is transferred immediately to the shift register for transmission. HTDE is set only at the end of the data word transmission. Note: The master is responsible for deasserting and asserting the slave device SS line between word transmissions.
When the SHI is in master mode and CPHA = 1, the DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. The HTX data is transferred to the shift register for transmission as soon as the shift register is empty. HTDE is set when the data is transferred from HTX to the shift register. 9.5.5.2 HCKR Prescaler Rate Select (HRS)--Bit 2 The HRS bit controls a prescaler in series with the clock generator divider. This bit is used to extend the range of the divider when slower clock rates are desired. When HRS is set, the prescaler is bypassed. When HRS is cleared, the fixed divide-by-eight prescaler is operational. HRS is ignored when the SHI operates in the slave mode, except for I2C when HCKFR is set. The HRS bit is cleared during hardware reset and software reset. Note: Use the equations in the SHI datasheet to determine the value of HRS for the specific serial clock frequency required.
9.5.5.3 HCKR Divider Modulus Select (HDM[7:0])--Bits 10-3 The HDM[7:0] bits specify the divide ratio of the clock generator divider. A divide ratio between 1 and 256 (HDM[7:0] = $00 to $FF) may be selected. When the SHI operates in the slave mode, the HDM[7:0] bits are ignored (except for I2C when HCKFR is set). The HDM[7:0] bits are cleared during hardware reset and software reset. Note: Use the equations in the SHI datasheet to determine the value of HDM[7:0] for the specific serial clock frequency required.
MOTOROLA
DSP56367
9-11
Serial Host Interface Serial Host Interface Programming Model
9.5.5.4 HCKR Reserved Bits--Bits 23-14, 11 These bits in HCKR are reserved. They are read as zero and should be written with zero for future compatibility. 9.5.5.5 HCKR Filter Mode (HFM[1:0]) -- Bits 13-12 The read/write control bits HFM[1:0] specify the operational mode of the noise reduction filters, as described in Table 9-3. The filters are designed to eliminate undesired spikes that might occur on the clock and data-in lines and allow the SHI to operate in noisy environments when required. One filter is located in the input path of the SCK/SCL line and the other is located in the input path of the data line (i.e., the SDA line when in I2C mode, the MISO line when in SPI master mode, and the MOSI line when in SPI slave mode). Table 9-3 SHI Noise Reduction Filter Mode
HFM1 0 0 1 1 HFM0 0 1 0 1 Bypassed (Disabled) Reserved Narrow Spike Tolerance Wide Spike Tolerance Description
When HFM[1:0] = 00, the filter is bypassed (spikes are not filtered out). This mode is useful when higher bit-rate transfers are required and the SHI operates in a noise-free environment. When HFM[1:0] = 10, the narrow-spike-tolerance filter mode is selected. In this mode the filters eliminate spikes with durations of up to 50ns. This mode is suitable for use in mildly noisy environments and imposes some limitations on the maximum achievable bit-rate transfer. When HFM[1:0] = 11, the wide-spike-tolerance filter mode is selected. In this mode the filters eliminate spikes up to 100 ns. This mode is recommended for use in noisy environments; the bit-rate transfer is strictly limited. The wide-spike- tolerance filter mode is highly recommended for use in I2C bus systems as it fully conforms to the I2C bus specification and improves noise immunity. Note: HFM[1:0] are cleared during hardware reset and software reset.
After changing the filter bits in the HCKR to a non-bypass mode (HFM[1:0] not equal to `00'), the programmer should wait at least ten times the tolerable spike width before enabling the SHI (setting the HEN bit in the HCSR). Similarly, after changing the HI2C bit in the HCSR or the CPOL bit in the HCKR, while the filter mode bits are in a non-bypass mode (HFM[1:0] not equal to `00'), the programmer should wait at least ten times the tolerable spike width before enabling the SHI (setting HEN in the HCSR).
9-12
DSP56367
MOTOROLA
Serial Host Interface Serial Host Interface Programming Model
9.5.6
SHI CONTROL/STATUS REGISTER (HCSR)--DSP SIDE
The HCSR is a 24-bit register that controls the SHI operation and reflects its status. The control bits are read/write. The status bits are read-only. The bits are described in the following paragraphs. When in the stop state or during individual reset, the HCSR status bits are reset to their hardware-reset state, while the control bits are not affected. 9.5.6.1 HCSR Host Enable (HEN)--Bit 0 The read/write control bit HEN, when set, enables the SHI. When HEN is cleared, the SHI is disabled (that is, it is in the individual reset state, see below). The HCKR and the HCSR control bits are not affected when HEN is cleared. When operating in master mode, HEN should be cleared only when the SHI is idle (HBUSY = 0). HEN is cleared during hardware reset and software reset. 9.5.6.1.1 SHI Individual Reset While the SHI is in the individual reset state, SHI input pins are inhibited, output and bidirectional pins are disabled (high impedance), the HCSR status bits and the transmit/receive paths are reset to the same state produced by hardware reset or software reset. The individual reset state is entered following a one-instruction-cycle delay after clearing HEN. 9.5.6.2 HCSR I2C/SPI Selection (HI2C)--Bit 1 The read/write control bit HI2C selects whether the SHI operates in the I2C or SPI modes. When HI2C is cleared, the SHI operates in the SPI mode. When HI2C is set, the SHI operates in the I2C mode. HI2C affects the functionality of the SHI pins as described in Section 2 Signal/Connection Descriptions. It is recommended that an SHI individual reset be generated (HEN cleared) before changing HI2C. HI2C is cleared during hardware reset and software reset. 9.5.6.3 HCSR Serial Host Interface Mode (HM[1:0])--Bits 3-2 The read/write control bits HM[1:0] select the size of the data words to be transferred, as shown in Table 9-4. HM[1:0] should be modified only when the SHI is idle (HBUSY = 0). HM[1:0] are cleared during hardware reset and software reset. Table 9-4 SHI Data Size
HM1 0 0 1 1 HMO 0 1 0 1 Description 8-bit data 16-bit data 24-bit data Reserved
MOTOROLA
DSP56367
9-13
Serial Host Interface Serial Host Interface Programming Model
9.5.6.4 HCSR I2C Clock Freeze (HCKFR)--Bit 4 The read/write control bit HCKFR determines the behavior of the SHI when the SHI is unable to service the master request, when operating in the I2C slave mode. The HCKFR bit is used only in the I2C slave mode; it is ignored otherwise. If HCKFR is set, the SHI holds the clock line to GND if it is not ready to send data to the master during a read transfer or if the input FIFO is full when the master attempts to execute a write transfer. In this way, the master may detect that the slave is not ready for the requested transfer, without causing an error condition in the slave. When HCKFR is set for transmit sessions, the SHI clock generator must be programmed as if to generate the same serial clock as produced by the external master, otherwise erroneous operation may result. The programmed frequency should be in the range of 1 to 0.75 times the external clock frequency. If HCKFR is cleared, any attempt from the master to execute a transfer when the slave is not ready results in an overrun or underrun error condition. It is recommended that an SHI individual reset be generated (HEN cleared) before changing HCKFR. HCKFR is cleared during hardware reset and software reset. 9.5.6.5 HCSR FIFO-Enable Control (HFIFO)--Bit 5 The read/write control bit HFIFO selects the receive FIFO size. When HFIFO is cleared, the FIFO has one level. When HFIFO is set, the FIFO has 10 levels. It is recommended that an SHI individual reset be generated (HEN cleared) before changing HFIFO. HFIFO is cleared during hardware reset and software reset. 9.5.6.6 HCSR Master Mode (HMST)--Bit 6 The read/write control bit HMST determines the SHI operating mode. If HMST is set, the interface operates in the master mode. If HMST is cleared, the interface operates in the slave mode. The SHI supports a single-master configuration in both I2C and SPI modes. When configured as an SPI master, the SHI drives the SCK line and controls the direction of the data lines MOSI and MISO. The SS line must be held deasserted in the SPI master mode; if the SS line is asserted when the SHI is in SPI master mode, a bus error is generated (the HCSR HBER bit is set--see Section 9.5.6.18). When configured as an I2C master, the SHI controls the I2C bus by generating start events, clock pulses, and stop events for transmission and reception of serial data. It is recommended that an SHI individual reset be generated (HEN cleared) before changing HMST. HMST is cleared during hardware reset and software reset.
9-14
DSP56367
MOTOROLA
Serial Host Interface Serial Host Interface Programming Model
9.5.6.7 HCSR Host-Request Enable (HRQE[1:0])--Bits 8-7 The read/write control bits HRQE[1:0] are used to control the HREQ pin. When HRQE[1:0] are cleared, the HREQ pin is disabled and held in the high impedance state. If either of HRQE[1:0] are set and the SHI is in a master mode, the HREQ pin becomes an input controlling SCK: deasserting HREQ suspends SCK. If either of HRQE[1:0] are set and the SHI is in a slave mode, HREQ becomes an output and its operation is defined in Table 9-5. HRQE[1:0] should be changed only when the SHI is idle (HBUSY = 0). HRQE[1:0] are cleared during hardware reset and software reset. Table 9-5 HREQ Function In SHI Slave Modes
HRQE1 0 0 1 1 HRQE0 0 1 0 1 High impedance Asserted if IOSR is ready to receive a new word Asserted if IOSR is ready to transmit a new word I2C: Asserted if IOSR is ready to transmit or receive SPI: Asserted if IOSR is ready to transmit and receive HREQ Pin Operation
9.5.6.8 HCSR Idle (HIDLE)--Bit 9 The read/write control/status bit HIDLE is used only in the I2C master mode; it is ignored otherwise. It is only possible to set the HIDLE bit during writes to the HCSR. HIDLE is cleared by writing to HTX. To ensure correct transmission of the slave device address byte, HIDLE should be set only when HTX is empty (HTDE = 1). After HIDLE is set, a write to HTX clears HIDLE and causes the generation of a stop event, a start event, and then the transmission of the eight MSBs of the data as the slave device address byte. While HIDLE is cleared, data written to HTX is transmitted as is. If the SHI completes transmitting a word and there is no new data in HTX, the clock is suspended after sampling ACK. If HIDLE is set when the SHI completes transmitting a word with no new data in HTX, a stop event is generated. HIDLE determines the acknowledge that the receiver sends after correct reception of a byte. If HIDLE is cleared, the reception is acknowledged by sending a 0 bit on the SDA line at the ACK clock tick. If HIDLE is set, the reception is not acknowledged (a 1 bit is sent). It is used to signal an end-of-data to a slave transmitter by not generating an ACK on the last byte. As a result, the slave transmitter must release the SDA line to allow the master to generate the stop event. If the SHI completes receiving a word and the HRX FIFO is full, the clock is suspended before transmitting an ACK. While HIDLE is cleared the bus is busy, that is, the start event was sent but no stop event was generated. Setting HIDLE causes a stop event after receiving the current word. HIDLE is set while the SHI is not in the I2C master mode, while the chip is in the stop state, and during hardware reset, software reset and individual reset.
MOTOROLA
DSP56367
9-15
Serial Host Interface Serial Host Interface Programming Model
Note:
Programmers should take care to ensure that all DMA channel service to HTX is disabled before setting HIDLE.
9.5.6.9 HCSR Bus-Error Interrupt Enable (HBIE)--Bit 10 The read/write control bit HBIE is used to enable the SHI bus-error interrupt. If HBIE is cleared, bus-error interrupts are disabled, and the HBER status bit must be polled to determine if an SHI bus error occurred. If both HBIE and HBER are set, the SHI requests an SHI bus-error interrupt service from the interrupt controller. HBIE is cleared by hardware reset and software reset. Note: Clearing HBIE masks a pending bus-error interrupt only after a one instruction cycle delay. If HBIE is cleared in a long interrupt service routine, it is recommended that at least one other instruction separate the instruction that clears HBIE and the RTI instruction at the end of the interrupt service routine.
9.5.6.10 HCSR Transmit-Interrupt Enable (HTIE)--Bit 11 The read/write control bit HTIE is used to enable the SHI transmit data interrupts. If HTIE is cleared, transmit interrupts are disabled, and the HTDE status bit must be polled to determine if HTX is empty. If both HTIE and HTDE are set and HTUE is cleared, the SHI requests an SHI transmit-data interrupt service from the interrupt controller. If both HTIE and HTUE are set, the SHI requests an SHI transmit-underrun-error interrupt service from the interrupt controller. HTIE is cleared by hardware reset and software reset. Note: Clearing HTIE masks a pending transmit interrupt only after a one instruction cycle delay. If HTIE is cleared in a long interrupt service routine, it is recommended that at least one other instruction separate the instruction that clears HTIE and the RTI instruction at the end of the interrupt service routine.
9.5.6.11 HCSR Receive Interrupt Enable (HRIE[1:0])--Bits 13-12 The read/write control bits HRIE[1:0] are used to enable the SHI receive-data interrupts. If HRIE[1:0] are cleared, receive interrupts are disabled, and the HRNE and HRFF (bits 17 and 19, see below) status bits must be polled to determine if there is data in the receive FIFO. If HRIE[1:0] are not cleared, receive interrupts are generated according to Table 9-6. HRIE[1:0] are cleared by hardware and software reset. Table 9-6 HCSR Receive Interrupt Enable Bits
HRIE[1:0] 00 01 Disabled Receive FIFO not empty Receive Overrun Error Reserved Interrupt Not applicable HRNE = 1 and HROE = 0 HROE = 1 Not applicable Condition
10
9-16
DSP56367
MOTOROLA
Serial Host Interface Serial Host Interface Programming Model
Table 9-6 HCSR Receive Interrupt Enable Bits
HRIE[1:0] 11 Interrupt Receive FIFO full Receive Overrun Error Condition HRFF = 1 and HROE = 0 HROE = 1
Note:
Clearing HRIE[1:0] masks a pending receive interrupt only after a one instruction cycle delay. If HRIE[1:0] are cleared in a long interrupt service routine, it is recommended that at least one other instruction separate the instruction that clears HRIE[1:0] and the RTI instruction at the end of the interrupt service routine.
9.5.6.12 HCSR Host Transmit Underrun Error (HTUE)--Bit 14 The read-only status bit HTUE indicates whether a transmit-underrun error occurred. Transmit-underrun errors can occur only when operating in the SPI slave mode or the I2C slave mode when HCKFR is cleared. In a master mode, transmission takes place on demand and no underrun can occur. HTUE is set when both the shift register and the HTX register are empty and the external master begins reading the next word: * * When operating in the I2C mode, HTUE is set in the falling edge of the ACK bit. In this case, the SHI retransmits the previously transmitted word. When operating in the SPI mode, HTUE is set at the first clock edge if CPHA = 1; it is set at the assertion of SS if CPHA = 0.
If a transmit interrupt occurs with HTUE set, the transmit-underrun interrupt vector is generated. If a transmit interrupt occurs with HTUE cleared, the regular transmit-data interrupt vector is generated. HTUE is cleared by reading the HCSR and then writing to the HTX register. HTUE is cleared by hardware reset, software reset, SHI individual reset, and during the stop state. 9.5.6.13 HCSR Host Transmit Data Empty (HTDE)--Bit 15 The read-only status bit HTDE indicates whether the HTX register is empty and can be written by the DSP. HTDE is set when the data word is transferred from HTX to the shift register, except in SPI master mode when CPHA = 0 (see HCKR). When in the SPI master mode with CPHA = 0, HTDE is set after the end of the data word transmission. HTDE is cleared when the DSP writes the HTX either with write instructions or DMA transfers. HTDE is set by hardware reset, software reset, SHI individual reset, and during the stop state. 9.5.6.14 HCSR Reserved Bits--Bits 23, 18 and 16 These bits are reserved. They read as zero and should be written with zero for future compatibility.
MOTOROLA
DSP56367
9-17
Serial Host Interface Serial Host Interface Programming Model
9.5.6.15 Host Receive FIFO Not Empty (HRNE)--Bit 17 The read-only status bit HRNE indicates that the Host Receive FIFO (HRX) contains at least one data word. HRNE is set when the FIFO is not empty. HRNE is cleared when HRX is read by the DSP (read instructions or DMA transfers), reducing the number of words in the FIFO to zero. HRNE is cleared during hardware reset, software reset, SHI individual reset, and during the stop state. 9.5.6.16 Host Receive FIFO Full (HRFF)--Bit 19 The read-only status bit HRFF indicates, when set, that the Host Receive FIFO (HRX) is full. HRFF is cleared when HRX is read by the DSP (read instructions or DMA transfers) and at least one place is available in the FIFO. HRFF is cleared by hardware reset, software reset, SHI individual reset, and during the stop state. 9.5.6.17 Host Receive Overrun Error (HROE)--Bit 20 The read-only status bit HROE indicates, when set, that a data-receive overrun error has occurred. Receive-overrun errors cannot occur when operating in the I2C master mode, because the clock is suspended if the receive FIFO is full; nor can they occur in the I2C slave mode when HCKFR is set. HROE is set when the shift register (IOSR) is filled and ready to transfer the data word to the HRX FIFO and the FIFO is already full (HRFF is set). When a receive-overrun error occurs, the shift register is not transferred to the FIFO. If a receive interrupt occurs with HROE set, the receive-overrun interrupt vector is generated. If a receive interrupt occurs with HROE cleared, the regular receive-data interrupt vector is generated. HROE is cleared by reading the HCSR with HROE set, followed by reading HRX. HROE is cleared by hardware reset, software reset, SHI individual reset, and during the stop state. 9.5.6.18 Host Bus Error (HBER)--Bit 21 The read-only status bit HBER indicates, when set, that an SHI bus error occurred when operating as a master (HMST set). In I2C mode, HBER is set if the transmitter does not receive an acknowledge after a byte is transferred; then a stop event is generated and transmission is suspended. In SPI mode, HBER is set if SS is asserted; then transmission is suspended at the end of transmission of the current word. HBER is cleared only by hardware reset, software reset, SHI individual reset, and during the stop state. 9.5.6.19 HCSR Host Busy (HBUSY)--Bit 22 The read-only status bit HBUSY indicates that the I2C bus is busy (when in the I2C mode) or that the SHI itself is busy (when in the SPI mode). When operating in the I2C mode, HBUSY is set after the SHI detects a start event and remains set until a stop event is detected. When operating in the slave SPI mode, HBUSY is set while SS is asserted. When operating in the master SPI mode, HBUSY is set if the HTX register is not empty or if the IOSR is not empty.
9-18
DSP56367
MOTOROLA
Serial Host Interface Characteristics Of The I2C Bus
HBUSY is cleared otherwise. HBUSY is cleared by hardware reset, software reset, SHI individual reset, and during the stop state.
9.6
CHARACTERISTICS OF THE I2C BUS
The I2C serial bus consists of two bidirectional lines, one for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. Note: In the I2C bus specifications, the standard mode (100 kHz clock rate) and a fast mode (400 kHz clock rate) are defined. The SHI can operate in either mode.
9.6.1
OVERVIEW
The I2C bus protocol must conform to the following rules: * * Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line when the clock line is high are interpreted as control signals (see Figure 9-7).
SDA
SCL Data Line Stable: Data Valid Change of Data Allowed
AA0422
Figure 9-7 I2C Bit Transfer Accordingly, the I2C bus protocol defines the following events: * * Bus not busy--Both data and clock lines remain high. Start data transfer--The start event is defined as a change in the state of the data line, from high to low, while the clock is high (see Figure 9-8).
MOTOROLA
DSP56367
9-19
Serial Host Interface Characteristics Of The I2C Bus
* *
Stop data transfer--The stop event is defined as a change in the state of the data line, from low to high, while the clock is high (see Figure 9-8). Data valid--The state of the data line represents valid data when, after a start event, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data.
SDA
SCL S Start Event P Stop Event
AA0423
Figure 9-8 I2C Start and Stop Events Each 8-bit word is followed by one acknowledge bit. This acknowledge bit is a high level put on the bus by the transmitter when the master device generates an extra acknowledge-related clock pulse. A slave receiver that is addressed must generate an acknowledge after each byte is received. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The acknowledging device must pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable low during the high period of the acknowledge-related clock pulse (see Figure 9-9).
Start Event SCL From Master Device Data Output by Transmitter Data Output by Receiver S
Clock Pulse For Acknowledgment
1
2
8
9
AA0424
Figure 9-9 Acknowledgment on the I2C Bus
9-20
DSP56367
MOTOROLA
Serial Host Interface Characteristics Of The I2C Bus
A device generating a signal is called a transmitter, and a device receiving a signal is called a receiver. A device controlling a signal is called a master and devices controlled by the master are called slaves. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte clocked out of the slave device. In this case the transmitter must leave the data line high to enable the master to generate the stop event. Handshaking may also be accomplished by using the clock synchronizing mechanism. Slave devices can hold the SCL line low, after receiving and acknowledging a byte, to force the master into a wait state until the slave device is ready for the next byte transfer. The SHI supports this feature when operating as a master device and waits until the slave device releases the SCL line before proceeding with the data transfer.
9.6.2
I2C DATA TRANSFER FORMATS
I2C bus data transfers follow the following process: after the start event, a slave device address is sent. The address consists of seven address bits and an eighth bit as a data direction bit (R/W). In the data direction bit, zero indicates a transmission (write), and one indicates a request for data (read). A data transfer is always terminated by a stop event generated by the master device. However, if the master device still wishes to communicate on the bus, it can generate another start event, and address another slave device without first generating a stop event (the SHI does not support this feature when operating as an I2C master device). This method is also used to provide indivisible data transfers. Various combinations of read/write formats are illustrated in Figure 9-10 and Figure 9-11.
ACK from Slave Device
ACK from Slave Device
ACK from Slave Device
S
Slave Address
0
A
First Data Byte
A
Data Byte
A S, P
Start Bit
R/W
AA0425
N = 0 to M Data Bytes
Start or Stop Bit
Figure 9-10 I2C Bus Protocol For Host Write Cycle
MOTOROLA
DSP56367
9-21
Serial Host Interface SHI Programming Considerations
ACK from Slave Device
ACK from Master Device
No ACK from Master Device
S
Slave Address
1
A
Data Byte
A
Last Data Byte
1
P
Start Bit
R/W
N = 0 to M Data Bytes
AA0426
Stop Bit
Figure 9-11 I2C Bus Protocol For Host Read Cycle Note: The first data byte in a write-bus cycle can be used as a user-predefined control byte (e.g., to determine the location to which the forthcoming data bytes should be transferred).
9.7
SHI PROGRAMMING CONSIDERATIONS
The SHI implements both SPI and I2C bus protocols and can be programmed to operate as a slave device or a single-master device. Once the operating mode is selected, the SHI may communicate with an external device by receiving and/or transmitting data. Before changing the SHI operational mode, an SHI individual reset should be generated by clearing the HEN bit. The following paragraphs describe programming considerations for each operational mode.
9.7.1
SPI SLAVE MODE
The SPI slave mode is entered by enabling the SHI (HEN=1), selecting the SPI mode (HI2C=0), and selecting the slave mode of operation (HMST=0). The programmer should verify that the CPHA and CPOL bits (in the HCKR) correspond to the external host clock phase and polarity. Other HCKR bits are ignored. When configured in the SPI slave mode, the SHI external pins operate as follows: * * * * SCK/SCL is the SCK serial clock input. MISO/SDA is the MISO serial data output. MOSI/HA0 is the MOSI serial data input. SS/HA2 is the SS slave select input.
9-22
DSP56367
MOTOROLA
Serial Host Interface SHI Programming Considerations
*
HREQ is the Host Request output.
In the SPI slave mode, a receive, transmit, or full-duplex data transfer may be performed. Actually, the interface performs data receive and transmit simultaneously. The status bits of both receive and transmit paths are active; however, the programmer may disable undesired interrupts and ignore irrelevant status bits. It is recommended that an SHI individual reset (HEN cleared) be generated before beginning data reception in order to reset the HRX FIFO to its initial (empty) state (e.g., when switching from transmit to receive data). If a write to HTX occurs, its contents are transferred to IOSR between data word transfers. The IOSR data is shifted out (via MISO) and received data is shifted in (via MOSI). The DSP may write HTX with either DSP instructions or DMA transfers if the HTDE status bit is set. If no writes to HTX occur, the contents of HTX are not transferred to IOSR, so the data shifted out when receiving is the data present in the IOSR at the time. The HRX FIFO contains valid receive data, which the DSP can read with either DSP instructions or DMA transfers (if the HRNE status bit is set). The HREQ output pin, if enabled for receive (HRQE[1:0] = 01), is asserted when the IOSR is ready for receive and the HRX FIFO is not full; this operation guarantees that the next received data word is stored in the FIFO. The HREQ output pin, if enabled for transmit (HRQE[1:0] = 10), is asserted when the IOSR is loaded from HTX with a new data word to transfer. If HREQ is enabled for both transmit and receive (HRQE[1:0] = 11), it is asserted when the receive and transmit conditions are both true. HREQ is deasserted at the first clock pulse of the next data word transfer. The HREQ line may be used to interrupt the external master device. Connecting the HREQ line between two SHI-equipped DSPs, one operating as an SPI master device and the other as an SPI slave device, enables full hardware handshaking if operating with CPHA = 1. The SS line should be kept asserted during a data word transfer. If the SS line is deasserted before the end of the data word transfer, the transfer is aborted and the received data word is lost.
9.7.2
SPI MASTER MODE
The SPI master mode is initiated by enabling the SHI (HEN = 1), selecting the SPI mode (HI2C = 0), and selecting the master mode of operation (HMST = 1). Before enabling the SHI as an SPI master device, the programmer should program the proper clock rate, phase and polarity in HCKR. When configured in the SPI master mode, the SHI external pins operate as follows: * * SCK/SCL is the SCK serial clock output. MISO/SDA is the MISO serial data input.
MOTOROLA
DSP56367
9-23
Serial Host Interface SHI Programming Considerations
* * *
MOSI/HA0 is the MOSI serial data output. SS/HA2 is the SS input. It should be kept deasserted (high) for proper operation. HREQ is the Host Request input.
The external slave device can be selected either by using external logic or by activating a GPIO pin connected to its SS pin. However, the SS input pin of the SPI master device should be held deasserted (high) for proper operation. If the SPI master device SS pin is asserted, the host bus error status bit (HBER) is set. If the HBIE bit is also set, the SHI issues a request to the DSP interrupt controller to service the SHI bus error interrupt. In the SPI master mode the DSP must write to HTX to receive, transmit or perform a full-duplex data transfer. Actually, the interface performs simultaneous data receive and transmit. The status bits of both receive and transmit paths are active; however, the programmer may disable undesired interrupts and ignore irrelevant status bits. In a data transfer, the HTX is transferred to IOSR, clock pulses are generated, the IOSR data is shifted out (via MOSI) and received data is shifted in (via MISO). The DSP programmer may write HTX (if the HTDE status bit is set) with either DSP instructions or DMA transfers to initiate the transfer of the next word. The HRX FIFO contains valid receive data, which the DSP can read with either DSP instructions or DMA transfers, if the HRNE status bit is set. It is recommended that an SHI individual reset (HEN cleared) be generated before beginning data reception in order to reset the receive FIFO to its initial (empty) state (e.g., when switching from transmit to receive data). The HREQ input pin is ignored by the SPI master device if the HRQE[1:0] bits are cleared, and considered if any of them is set. When asserted by the slave device, HREQ indicates that the external slave device is ready for the next data transfer. As a result, the SPI master sends clock pulses for the full data word transfer. HREQ is deasserted by the external slave device at the first clock pulse of the new data transfer. When deasserted, HREQ prevents the clock generation of the next data word transfer until it is asserted again. Connecting the HREQ line between two SHI-equipped DSPs, one operating as an SPI master device and the other as an SPI slave device, enables full hardware handshaking if CPHA = 1. For CPHA = 0, HREQ should be disabled by clearing HRQE[1:0].
9.7.3
I2C SLAVE MODE
The I2C slave mode is entered by enabling the SHI (HEN=1), selecting the I2C mode (HI2C=1), and selecting the slave mode of operation (HMST=0). In this operational mode the contents of HCKR are ignored. When configured in the I2C slave mode, the SHI external pins operate as follows:
9-24
DSP56367
MOTOROLA
Serial Host Interface SHI Programming Considerations
* * * * *
SCK/SCL is the SCL serial clock input. MISO/SDA is the SDA open drain serial data line. MOSI/HA0 is the HA0 slave device address input. SS/HA2 is the HA2 slave device address input. HREQ is the Host Request output.
When the SHI is enabled and configured in the I2C slave mode, the SHI controller inspects the SDA and SCL lines to detect a start event. Upon detection of the start event, the SHI receives the slave device address byte and enables the slave device address recognition unit. If the slave device address byte was not identified as its personal address, the SHI controller fails to acknowledge this byte by not driving low the SDA line at the ninth clock pulse (ACK = 1). However, it continues to poll the SDA and SCL lines to detect a new start event. If the personal slave device address was correctly identified, the slave device address byte is acknowledged (ACK = 0 is sent) and a receive/transmit session is initiated according to the eighth bit of the received slave device address byte (i.e., the R/W bit). 9.7.3.1 Receive Data in I2C Slave Mode A receive session is initiated when the personal slave device address has been correctly identified and the R/W bit of the received slave device address byte has been cleared. Following a receive initiation, data in the SDA line is shifted into IOSR MSB first. Following each received byte, an acknowledge (ACK = 0) is sent at the ninth clock pulse via the SDA line. Data is acknowledged bytewise, as required by the I2C bus protocol, and is transferred to the HRX FIFO when the complete word (according to HM[1:0]) is filled into IOSR. It is the responsibility of the programmer to select the correct number of bytes in an I2C frame so that they fit in a complete number of words. For this purpose, the slave device address byte does not count as part of the data; therefore, it is treated separately. In a receive session, only the receive path is enabled and HTX to IOSR transfers are inhibited. The HRX FIFO contains valid data, which may be read by the DSP with either DSP instructions or DMA transfers (if the HRNE status bit is set). If HCKFR is cleared, when the HRX FIFO is full and IOSR is filled, an overrun error occurs and the HROE status bit is set. In this case, the last received byte is not acknowledged (ACK=1 is sent) and the word in the IOSR is not transferred to the HRX FIFO. This may inform the external I2C master device of the occurrence of an overrun error on the slave side. Consequently the I2C master device may terminate this session by generating a stop event. If HCKFR is set, when the HRX FIFO is full the SHI holds the clock line to GND not letting the master device write to IOSR, which eliminates the possibility of reaching the overrun condition.
MOTOROLA
DSP56367
9-25
Serial Host Interface SHI Programming Considerations
The HREQ output pin, if enabled for receive (HRQE[1:0] = 01), is asserted when the IOSR is ready to receive and the HRX FIFO is not full; this operation guarantees that the next received data word is stored in the FIFO. HREQ is deasserted at the first clock pulse of the next received word. The HREQ line may be used to interrupt the external I2C master device. Connecting the HREQ line between two SHI-equipped DSPs, one operating as an I2C master device and the other as an I2C slave device, enables full hardware handshaking. 9.7.3.2 Transmit Data In I2C Slave Mode A transmit session is initiated when the personal slave device address has been correctly identified and the R/W bit of the received slave device address byte has been set. Following a transmit initiation, the IOSR is loaded from HTX (assuming the latter was not empty) and its contents are shifted out, MSB first, on the SDA line. Following each transmitted byte, the SHI controller samples the SDA line at the ninth clock pulse, and inspects the ACK status. If the transmitted byte was acknowledged (ACK = 0), the SHI controller continues and transmits the next byte. However, if it was not acknowledged (ACK = 1), the transmit session is stopped and the SDA line is released. Consequently, the external master device may generate a stop event in order to terminate the session. HTX contents are transferred to IOSR when the complete word (according to HM[1:0]) has been shifted out. It is, therefore, the responsibility of the programmer to select the correct number of bytes in an I2C frame so that they fit in a complete number of words. For this purpose, the slave device address byte does not count as part of the data; therefore, it is treated separately. In a transmit session, only the transmit path is enabled and the IOSR-to-HRX FIFO transfers are inhibited. When the HTX transfers its valid data word to IOSR, the HTDE status bit is set and the DSP may write a new data word to HTX with either DSP instructions or DMA transfers. If HCKFR is cleared and both IOSR and HTX are empty when the master device attempts a transmit session, an underrun condition occurs, setting the HTUE status bit, and the previous word is retransmitted. If HCKFR is set and both IOSR and HTX are empty when the master device attempts a transmit session, the SHI holds the clock line to GND to avoid an underrun condition. The HREQ output pin, if enabled for transmit (HRQE[1:0] = 10), is asserted when HTX is transferred to IOSR for transmission. When asserted, HREQ indicates that the slave device is ready to transmit the next data word. HREQ is deasserted at the first clock pulse of the next transmitted data word. The HREQ line may be used to interrupt the external I2C master device. Connecting the HREQ line between two SHI-equipped DSPs, one operating as an I2C master device and the other as an I2C slave device, enables full hardware handshaking.
9-26
DSP56367
MOTOROLA
Serial Host Interface SHI Programming Considerations
9.7.4
I2C MASTER MODE
The I2C master mode is entered by enabling the SHI (HEN=1), selecting the I2C mode (HI2C=1) and selecting the master mode of operation (HMST=1). Before enabling the SHI as an I2C master, the programmer should program the appropriate clock rate in HCKR. When configured in the I2C master mode, the SHI external pins operate as follows: * * * * * SCK/SCL is the SCL open drain serial clock output. MISO/SDA is the SDA open drain serial data line. MOSI/HA0 is the HA0 slave device address input. SS/HA2 is the HA2 slave device address input. HREQ is the Host Request input.
In the I2C master mode, a data transfer session is always initiated by the DSP by writing to the HTX register when HIDLE is set. This condition ensures that the data byte written to HTX is interpreted as being a slave address byte. This data byte must specify the slave device address to be selected and the requested data transfer direction. Note: The slave address byte should be located in the high portion of the data word, whereas the middle and low portions are ignored. Only one byte (the slave address byte) is shifted out, independent of the word length defined by the HM[1:0] bits.
In order for the DSP to initiate a data transfer the following actions are to be performed: * * * * * The DSP tests the HIDLE status bit. If the HIDLE status bit is set, the DSP writes the slave device address and the R/W bit to the most significant byte of HTX. The SHI generates a start event. The SHI transmits one byte only, internally samples the R/W direction bit (last bit), and accordingly initiates a receive or transmit session. The SHI inspects the SDA level at the ninth clock pulse to determine the ACK value. If acknowledged (ACK = 0), it starts its receive or transmit session according to the sampled R/W value. If not acknowledged (ACK = 1), the HBER status bit in HCSR is set, which causes an SHI Bus Error interrupt request if HBIE is set, and a stop event is generated.
The HREQ input pin is ignored by the I2C master device if HRQE[1:0] are cleared, and considered if either of them is set. When asserted, HREQ indicates that the external slave device is ready for the next data transfer. As a result, the I2C master device sends clock pulses
MOTOROLA
DSP56367
9-27
Serial Host Interface SHI Programming Considerations
for the full data word transfer. HREQ is deasserted by the external slave device at the first clock pulse of the next data transfer. When deasserted, HREQ prevents the clock generation of the next data word transfer until it is asserted again. Connecting the HREQ line between two SHI-equipped DSPs, one operating as an I2C master device and the other as an I2C slave device, enables full hardware handshaking. 9.7.4.1 Receive Data in I2C Master Mode A receive session is initiated if the R/W direction bit of the transmitted slave device address byte is set. Following a receive initiation, data in the SDA line is shifted into IOSR MSB first. Following each received byte, an acknowledge (ACK = 0) is sent at the ninth clock pulse via the SDA line if the HIDLE control bit is cleared. Data is acknowledged bytewise, as required by the I2C bus protocol, and is transferred to the HRX FIFO when the complete word (according to HM[1:0]) is filled into IOSR. It is the responsibility of the programmer to select the correct number of bytes in an I2C frame so that they fit in a complete number of words. For this purpose, the slave device address byte does not count as part of the data; therefore, it is treated separately. If the I2C slave transmitter is acknowledged, it should transmit the next data byte. In order to terminate the receive session, the programmer should set the HIDLE bit at the last required data word. As a result, the last byte of the next received data word is not acknowledged, the slave transmitter releases the SDA line, and the SHI generates the stop event and terminates the session. In a receive session, only the receive path is enabled and the HTX-to-IOSR transfers are inhibited. If the HRNE status bit is set, the HRX FIFO contains valid data, which may be read by the DSP with either DSP instructions or DMA transfers. When the HRX FIFO is full, the SHI suspends the serial clock just before acknowledge. In this case, the clock is reactivated when the FIFO is read (the SHI gives an ACK = 0 and proceeds receiving). 9.7.4.2 Transmit Data In I2C Master Mode A transmit session is initiated if the R/W direction bit of the transmitted slave device address byte is cleared. Following a transmit initiation, the IOSR is loaded from HTX (assuming HTX is not empty) and its contents are shifted out, MSB-first, on the SDA line. Following each transmitted byte, the SHI controller samples the SDA line at the ninth clock pulse, and inspects the ACK status. If the transmitted byte was acknowledged (ACK=0), the SHI controller continues transmitting the next byte. However, if it was not acknowledged (ACK=1), the HBER status bit is set to inform the DSP side that a bus error (or overrun, or any other exception in the slave device) has occurred. Consequently, the I2C master device generates a stop event and terminates the session. HTX contents are transferred to the IOSR when the complete word (according to HM[1:0]) has been shifted out. It is, therefore, the responsibility of the programmer to select the right
9-28
DSP56367
MOTOROLA
Serial Host Interface SHI Programming Considerations
number of bytes in an I2C frame so that they fit in a complete number of words. Remember that for this purpose, the slave device address byte does not count as part of the data. In a transmit session, only the transmit path is enabled and the IOSR-to-HRX FIFO transfers are inhibited. When the HTX transfers its valid data word to the IOSR, the HTDE status bit is set and the DSP may write a new data word to HTX with either DSP instructions or DMA transfers. If both IOSR and HTX are empty, the SHI suspends the serial clock until new data is written into HTX (when the SHI proceeds with the transmit session) or HIDLE is set (the SHI reactivates the clock to generate the stop event and terminate the transmit session).
9.7.5
SHI OPERATION DURING DSP STOP
The SHI operation cannot continue when the DSP is in the stop state, because no DSP clocks are active. While the DSP is in the stop state, the SHI remains in the individual reset state. While in the individual reset state the following is true: * * * * Note: If the SHI was operating in the I2C mode, the SHI signals are disabled (high impedance state). If the SHI was operating in the SPI mode, the SHI signals are not affected. The HCSR status bits and the transmit/receive paths are reset to the same state produced by hardware reset or software reset. The HCSR and HCKR control bits are not affected. It is recommended that the SHI be disabled before entering the stop state.
MOTOROLA
DSP56367
9-29
Serial Host Interface SHI Programming Considerations
9-30
DSP56367
MOTOROLA
SECTION
10
ENHANCED SERIAL AUDIO INTERFACE (ESAI)
10.1 INTRODUCTION
The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals which implement the Motorola SPI serial protocol. The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. It is a superset of the 56300 Family ESSI peripheral and of the 56000 Family SAI peripheral. Note: The DSP56367 has two ESAI modules. This section describes the ESAI, and Section 11 describes the ESAI_1. The ESAI and ESAI_1 share 4 data pins. This is described in the ESAI_1 section.
The ESAI block diagram is shown in Figure 10-1. The ESAI is named synchronous because all serial transfers are synchronized to a clock. Additional synchronization signals are used to delineate the word frames. The normal mode of operation is used to transfer data at a periodic rate, one word per period. The network mode is similar in that it is also intended for periodic transfers; however, it supports up to 32 words (time slots) per period. This mode can be used to build time division multiplexed (TDM) networks. In contrast, the on-demand mode is intended for non-periodic transfers of data and to transfer data serially at high speed when the data becomes available. This mode offers a subset of the SPI protocol.
MOTOROLA
DSP56367
10-1
Enhanced Serial Audio Interface (ESAI) Introduction
GDB RSMA RSMB TSMA TSMB
DDB TX0 SDO0 [PC11] Shift Register TX1 SDO1 [PC10] Shift Register
RCCR RCR
TX2 SDO2/SDI3 [PC9] Shift Register
TCCR TCR
RX3 TX3 SDO3/SDI2 [PC8]
SAICR SAISR
Shift Register RX2 TX4
TSR Shift Register RX1 Clock / Frame Sync Generators and Control Logic TX5 RCLK Shift Register TCLK [PC2] HCKR [PC5] HCKT [PC0] SCKR [PC3] SCKT [PC1] FSR [PC4] FST RX0
SDO4/SDI1 [PC7]
SDO5/SDI0 [PC6]
Figure 10-1 ESAI Block Diagram
10-2
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Data and Control Pins
10.2
ESAI DATA AND CONTROL PINS
Three to twelve pins are required for operation, depending on the operating mode selected and the number of transmitters and receivers enabled. The SDO0 and SDO1 pins are used by transmitters 0 and 1 only. The SDO2/SDI3, SDO3/SDI2, SDO4/SDI1, and SDO5/SDI0 pins are shared by transmitters 2 to 5 with receivers 0 to 3. The actual mode of operation is selected under software control. All transmitters operate fully synchronized under control of the same transmitter clock signals. All receivers operate fully synchronized under control of the same receiver clock signals.
10.2.1
SERIAL TRANSMIT 0 DATA PIN (SDO0)
SDO0 is used for transmitting data from the TX0 serial transmit shift register. SDO0 is an output when data is being transmitted from the TX0 shift register. In the on-demand mode with an internally generated bit clock, the SDO0 pin becomes high impedance for a full clock period after the last data bit has been transmitted, assuming another data word does not follow immediately. If a data word follows immediately, there is no high-impedance interval. SDO0 may be programmed as a general-purpose I/O pin (PC11) when the ESAI SDO0 function is not being used.
10.2.2
SERIAL TRANSMIT 1 DATA PIN (SDO1)
SDO1 is used for transmitting data from the TX1 serial transmit shift register. SDO1 is an output when data is being transmitted from the TX1 shift register. In the on-demand mode with an internally generated bit clock, the SDO1 pin becomes high impedance for a full clock period after the last data bit has been transmitted, assuming another data word does not follow immediately. If a data word follows immediately, there is no high-impedance interval. SDO1 may be programmed as a general-purpose I/O pin (PC10) when the ESAI SDO1 function is not being used.
10.2.3
SERIAL TRANSMIT 2/RECEIVE 3 DATA PIN (SDO2/SDI3)
SDO2/SDI3 is used as the SDO2 for transmitting data from the TX2 serial transmit shift register when programmed as a transmitter pin, or as the SDI3 signal for receiving serial data to the RX3 serial receive shift register when programmed as a receiver pin. SDO2/SDI3 is an
MOTOROLA
DSP56367
10-3
Enhanced Serial Audio Interface (ESAI) ESAI Data and Control Pins
input when data is being received by the RX3 shift register. SDO2/SDI3 is an output when data is being transmitted from the TX2 shift register. In the on-demand mode with an internally generated bit clock, the SDO2/SDI3 pin becomes high impedance for a full clock period after the last data bit has been transmitted, assuming another data word does not follow immediately. If a data word follows immediately, there is no high-impedance interval. SDO2/SDI3 may be programmed as a general-purpose I/O pin (PC9) when the ESAI SDO2 and SDI3 functions are not being used.
10.2.4
SERIAL TRANSMIT 3/RECEIVE 2 DATA PIN (SDO3/SDI2)
SDO3/SDI2 is used as the SDO3 signal for transmitting data from the TX3 serial transmit shift register when programmed as a transmitter pin, or as the SDI2 signal for receiving serial data to the RX2 serial receive shift register when programmed as a receiver pin. SDO3/SDI2 is an input when data is being received by the RX2 shift register. SDO3/SDI2 is an output when data is being transmitted from the TX3 shift register. In the on-demand mode with an internally generated bit clock, the SDO3/SDI2 pin becomes high impedance for a full clock period after the last data bit has been transmitted, assuming another data word does not follow immediately. If a data word follows immediately, there is no high-impedance interval. SDO3/SDI2 may be programmed as a general-purpose I/O pin (PC8) when the ESAI SDO3 and SDI2 functions are not being used.
10.2.5
SERIAL TRANSMIT 4/RECEIVE 1 DATA PIN (SDO4/SDI1)
SDO4/SDI1 is used as the SDO4 signal for transmitting data from the TX4 serial transmit shift register when programmed as transmitter pin, or as the SDI1 signal for receiving serial data to the RX1 serial receive shift register when programmed as a receiver pin. SDO4/SDI1 is an input when data is being received by the RX1 shift register. SDO4/SDI1 is an output when data is being transmitted from the TX4 shift register. In the on-demand mode with an internally generated bit clock, the SDO4/SDI1 pin becomes high impedance for a full clock period after the last data bit has been transmitted, assuming another data word does not follow immediately. If a data word follows immediately, there is no high-impedance interval. SDO4/SDI1 may be programmed as a general-purpose I/O pin (PC7) when the ESAI SDO4 and SDI1 functions are not being used.
10-4
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Data and Control Pins
10.2.6
SERIAL TRANSMIT 5/RECEIVE 0 DATA PIN (SDO5/SDI0)
SDO5/SDI0 is used as the SDO5 signal for transmitting data from the TX5 serial transmit shift register when programmed as transmitter pin, or as the SDI0 signal for receiving serial data to the RX0 serial shift register when programmed as a receiver pin. SDO5/SDI0 is an input when data is being received by the RX0 shift register. SDO5/SDI0 is an output when data is being transmitted from the TX5 shift register. In the on-demand mode with an internally generated bit clock, the SDO5/SDI0 pin becomes high impedance for a full clock period after the last data bit has been transmitted, assuming another data word does not follow immediately. If a data word follows immediately, there is no high-impedance interval. SDO5/SDI0 may be programmed as a general-purpose I/O pin (PC6) when the ESAI SDO5 and SDI0 functions are not being used
10.2.7
RECEIVER SERIAL CLOCK (SCKR)
SCKR is a bidirectional pin providing the receivers serial bit clock for the ESAI interface. The direction of this pin is determined by the RCKD bit in the RCCR register.The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin reflects the value of the OF0 bit in the SAICR register, and the data in the OF0 bit shows up at the pin synchronized to the frame sync being used by the transmitter and receiver sections. When this pin is configured as the input flag IF0, the data value at the pin is stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. SCKR may be programmed as a general-purpose I/O pin (PC0) when the ESAI SCKR function is not being used. Note: Although the external ESAI serial clock can be independent of and asynchronous to the DSP system clock, the DSP clock frequency must be at least three times the external ESAI serial clock frequency and each ESAI serial clock phase must exceed the minimum of 1.5 DSP clock periods.
MOTOROLA
DSP56367
10-5
Enhanced Serial Audio Interface (ESAI) ESAI Data and Control Pins
For more information on pin mode and definition, see Table 10-7 and on receiver clock signals see Table 10-1. Table 10-1 Receiver Clock Sources (asynchronous mode only)
Receiver Bit Clock Source SCKR HCKR SCKR HCKR SCKR INT SCKR INT HCKR HCKR HCKR HCKR FSR FSR SCKR SCKR FSR FSR SCKR SCKR
RHCKD
RFSD
RCKD
OUTPUTS
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
10.2.8
TRANSMITTER SERIAL CLOCK (SCKT)
SCKT is a bidirectional pin providing the transmitters serial bit clock for the ESAI interface. The direction of this pin is determined by the TCKD bit in the TCCR register. The SCKT is a clock input or output used by all the enabled transmitters in the asynchronous mode (SYN=0)
10-6
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Data and Control Pins
or by all the enabled transmitters and receivers in the synchronous mode (SYN=1) (see Table 10-2). Table 10-2 Transmitter Clock Sources
THCKD 0 0 0 0 1 1 1 1 TFSD 0 0 1 1 0 0 1 1 TCKD 0 1 0 1 0 1 0 1 Transmitter Bit Clock Source SCKT HCKT SCKT HCKT SCKT INT SCKT INT HCKT HCKT HCKT HCKT FST FST SCKT SCKT FST FST SCKT SCKT OUTPUTS
SCKT may be programmed as a general-purpose I/O pin (PC3) when the ESAI SCKT function is not being used. Note: Although the external ESAI serial clock can be independent of and asynchronous to the DSP system clock, the DSP clock frequency must be at least three times the external ESAI serial clock frequency and each ESAI serial clock phase must exceed the minimum of 1.5 DSP clock periods.
10.2.9
FRAME SYNC FOR RECEIVER (FSR)
FSR is a bidirectional pin providing the receivers frame sync signal for the ESAI interface. The direction of this pin is determined by the RFSD bit in RCR register. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). For further information on pin mode and definition, see Table 10-8 and on receiver clock signals see Table 10-1. When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin reflects the value of the OF1 bit in the SAICR register, and the data in the OF1 bit shows up at the pin synchronized to the frame sync being used by the transmitter and receiver sections. When configured as the
MOTOROLA
DSP56367
10-7
Enhanced Serial Audio Interface (ESAI) ESAI Data and Control Pins
input flag IF1, the data value at the pin is stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. FSR may be programmed as a general-purpose I/O pin (PC1) when the ESAI FSR function is not being used.
10.2.10
FRAME SYNC FOR TRANSMITTER (FST)
FST is a bidirectional pin providing the frame sync for both the transmitters and receivers in the synchronous mode (SYN=1) and for the transmitters only in asynchronous mode (SYN=0) (see Table 10-2). The direction of this pin is determined by the TFSD bit in the TCR register. When configured as an output, this pin is the internally generated frame sync signal. When configured as an input, this pin receives an external frame sync signal for the transmitters (and the receivers in synchronous mode). FST may be programmed as a general-purpose I/O pin (PC4) when the ESAI FST function is not being used.
10.2.11
HIGH FREQUENCY CLOCK FOR TRANSMITTER (HCKT)
HCKT is a bidirectional pin providing the transmitters high frequency clock for the ESAI interface. The direction of this pin is determined by the THCKD bit in the TCCR register. In the asynchronous mode (SYN=0), the HCKT pin operates as the high frequency clock input or output used by all enabled transmitters. In the synchronous mode (SYN=1), it operates as the high frequency clock input or output used by all enabled transmitters and receivers. When programmed as input this pin is used as an alternative high frequency clock source to the ESAI transmitter rather than the DSP main clock. When programmed as output it can serve as a high frequency sample clock (to external DACs for example) or as an additional system clock. See Table 10-2. HCKT may be programmed as a general-purpose I/O pin (PC5) when the ESAI HCKT function is not being used.
10.2.12
HIGH FREQUENCY CLOCK FOR RECEIVER (HCKR)
HCKR is a bidirectional pin providing the receivers high frequency clock for the ESAI interface. The direction of this pin is determined by the RHCKD bit in the RCCR register. In the asynchronous mode (SYN=0), the HCKR pin operates as the high frequency clock input
10-8
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as the serial flag 2 pin. For further information on pin mode and definition, see Table 10-9 and on receiver clock signals see Table 10-1. When this pin is configured as serial flag pin, its direction is determined by the RHCKD bit in the RCCR register. When configured as the output flag OF2, this pin reflects the value of the OF2 bit in the SAICR register, and the data in the OF2 bit shows up at the pin synchronized to the frame sync being used by the transmitter and receiver sections. When configured as the input flag IF2, the data value at the pin is stored in the IF2 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. HCKR may be programmed as a general-purpose I/O pin (PC2) when the ESAI HCKR function is not being used.
10.3
ESAI PROGRAMMING MODEL
The ESAI can be viewed as five control registers, one status register, six transmit data registers, four receive data registers, two transmit slot mask registers, two receive slot mask registers and a special-purpose time slot register. The following paragraphs give detailed descriptions and operations of each bit in the ESAI registers. The ESAI pins can also function as GPIO pins (Port C), described in Section 10.5, "GPIO Pins and Registers".
10.3.1
ESAI TRANSMITTER CLOCK CONTROL REGISTER (TCCR)
The read/write Transmitter Clock Control Register (TCCR) controls the ESAI transmitter clock generator bit and frame sync rates, the bit clock and high frequency clock sources and the directions of the HCKT, FST and SCKT signals. (See Figure 10-2). In the synchronous
MOTOROLA
DSP56367
10-9
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
mode (SYN=1), the bit clock defined for the transmitter determines the receiver bit clock as well. TCCR also controls the number of words per frame for the serial data.
11 X:$FFFFB6 TDC2 10 TDC1 9 TDC0 8 TPSR 7 TPM7 6 TPM6 5 TPM5 4 TPM4 3 TPM3 2 TPM2 1 TPM1 0 TPM0
23
22
21
20
19
18 TCKP
17 TFP3
16 TFP2
15 TFP1
14 TFP0
13 TDC4
12 TDC3
THCKD TFSD
TCKD THCKP TFSP
Figure 10-2 TCCR Register Hardware and software reset clear all the bits of the TCCR register. The TCCR control bits are described in the following paragraphs. 10.3.1.1 TCCR Transmit Prescale Modulus Select (TPM7-TPM0) - Bits 0-7 The TPM7-TPM0 bits specify the divide ratio of the prescale divider in the ESAI transmitter clock generator. A divide ratio from 1 to 256 (TPM[7:0]=$00 to $FF) may be selected. The bit clock output is available at the transmit serial bit clock (SCKT) pin of the DSP. The bit clock output is also available internally for use as the bit clock to shift the transmit and receive shift registers. The ESAI transmit clock generator functional diagram is shown in Figure 10-3.
10-10
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
RHCKD=1 FOSC DIVIDE BY 2 RHCKD=0
PRESCALE DIVIDE BY 1 OR DIVIDE BY 8 DIVIDER DIVIDE BY 1 TO DIVIDE BY 256 DIVIDER DIVIDE BY 1 TO DIVIDE BY 16
RPSR
RPM0 - RPM7
RFP0 - RFP3
HCKR
RHCKD FLAG0 OUT (SYNC MODE) FLAG0 IN (SYNC MODE) INTERNAL BIT CLOCK RSWS4-RSWS0
RX WORD LENGTH DIVIDER SYN=1 SCKR RCLOCK SYN=0 RCKD SYN=1 TSWS4-TSWS0 SYN=0 RX SHIFT REGISTER
RX WORD CLOCK
INTERNAL BIT CLOCK SCKT
TCLOCK
TX WORD LENGTH DIVIDER
TX WORD CLOCK
TCKD TX SHIFT REGISTER THCKD
HCKT
TPSR TPM0 - TPM7 TFP0 - TFP3
THCKD=0 DIVIDE BY 2 THCKD=1
PRESCALE DIVIDE BY 1 OR DIVIDE BY 8 DIVIDER DIVIDE BY 1 TO DIVIDE BY 256 DIVIDER DIVIDE BY 1 TO DIVIDE BY 16
FOSC
Notes: 1. FOSC is the DSP56300 Core internal clock frequency.
Figure 10-3 ESAI Clock Generator Functional Block Diagram
MOTOROLA
DSP56367
10-11
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
10.3.1.2 TCCR Transmit Prescaler Range (TPSR) - Bit 8 The TPSR bit controls a fixed divide-by-eight prescaler in series with the variable prescaler. This bit is used to extend the range of the prescaler for those cases where a slower bit clock is desired. When TPSR is set, the fixed prescaler is bypassed. When TPSR is cleared, the fixed divide-by-eight prescaler is operational (see Figure 10-3). The maximum internally generated bit clock frequency is Fosc/4; the minimum internally generated bit clock frequency is Fosc/(2 x 8 x 256)=Fosc/4096. Note: Do not use the combination TPSR=1 and TPM7-TPM0=$00, which causes synchronization problems when using the internal DSP clock as source (TCKD=1 or THCKD=1).
10.3.1.3 TCCR Tx Frame Rate Divider Control (TDC4-TDC0) - Bits 9-13 The TDC4-TDC0 bits control the divide ratio for the programmable frame rate dividers used to generate the transmitter frame clocks. In network mode, this ratio may be interpreted as the number of words per frame minus one. The divide ratio may range from 2 to 32 (TDC[4:0]=00001 to 11111) for network mode. A divide ratio of one (TDC[4:0]=00000) in network mode is a special case (on-demand mode). In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32 (TDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of 1 (TDC[4:0]=00000) provides continuous periodic data word transfers. A bit-length frame sync (TFSL=1) must be used in this case. The ESAI frame sync generator functional diagram is shown in Figure 10-4.
10-12
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
RDC0 - RDC4 RX WORD CLOCK
RFSL
RECEIVER FRAME RATE DIVIDER
SYNC TYPE
INTERNAL RX FRAME CLOCK RFSD RFSD=1 SYN=0 SYN=0 FSR
RECEIVE CONTROL LOGIC
RECEIVE FRAME SYNC SYN=1 RFSD=0 SYN=1
TDC0 - TDC4 TX WORD CLOCK TRANSMITTER FRAME RATE DIVIDER
TFSL
FLAG1 IN (SYNC MODE)
FLAG1OUT (SYNC MODE) TFSD
SYNC TYPE
INTERNAL TX FRAME CLOCK FST
TRANSMIT CONTROL LOGIC
TRANSMIT FRAME SYNC
Figure 10-4 ESAI Frame Sync Generator Functional Block Diagram 10.3.1.4 TCCR Tx High Frequency Clock Divider (TFP3-TFP0) - Bits 14-17 The TFP3-TFP0 bits control the divide ratio of the transmitter high frequency clock to the transmitter serial bit clock when the source of the high frequency clock and the bit clock is the internal DSP clock. When the HCKT input is being driven from an external high frequency clock, the TFP3-TFP0 bits specify an additional division ratio in the clock divider chain. See Table 10-3 for the specification of the divide ratio. The ESAI high frequency clock generator functional diagram is shown in Figure 10-3.
MOTOROLA
DSP56367
10-13
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
Table 10-3 Transmitter High Frequency Clock Divider
TFP3-TFP0 $0 $1 $2 $3 ... $F Divide Ratio 1 2 3 4 ... 16
10.3.1.5 TCCR Transmit Clock Polarity (TCKP) - Bit 18 The Transmitter Clock Polarity (TCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in. If TCKP is cleared the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the transmit bit clock. If TCKP is set the falling edge of the transmit clock is used to clock the data out and frame sync and the rising edge of the transmit clock is used to latch the data and frame sync in. 10.3.1.6 TCCR Transmit Frame Sync Polarity (TFSP) - Bit 19 The Transmitter Frame Sync Polarity (TFSP) bit determines the polarity of the transmit frame sync signal. When TFSP is cleared, the frame sync signal polarity is positive (i.e the frame start is indicated by a high level on the frame sync pin). When TFSP is set, the frame sync signal polarity is negative (i.e the frame start is indicated by a low level on the frame sync pin). 10.3.1.7 TCCR Transmit High Frequency Clock Polarity (THCKP) - Bit 20 The Transmitter High Frequency Clock Polarity (THCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in. If THCKP is cleared the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the transmit bit clock. If THCKP is set the falling edge of the transmit clock is used to clock the data out and frame sync and the rising edge of the transmit clock is used to latch the data and frame sync in. 10.3.1.8 TCCR Transmit Clock Source Direction (TCKD) - Bit 21 The Transmitter Clock Source Direction (TCKD) bit selects the source of the clock signal used to clock the transmit shift registers in the asynchronous mode (SYN=0) and the transmit shift registers and the receive shift registers in the synchronous mode (SYN=1). When TCKD is set, the internal clock source becomes the bit clock for the transmit shift registers and word length divider and is the output on the SCKT pin. When TCKD is cleared, the clock source is external; the internal clock generator is disconnected from the SCKT pin, and an external clock source may drive this pin. See Table 10-2.
10-14
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
10.3.1.9 TCCR Transmit Frame Sync Signal Direction (TFSD) - Bit 22 TFSD controls the direction of the FST pin. When TFSD is cleared, FST is an input; when TFSD is set, FST is an output. See Table 10-2. 10.3.1.10 TCCR Transmit High Frequency Clock Direction (THCKD) - Bit 23 THCKD controls the direction of the HCKT pin. When THCKD is cleared, HCKT is an input; when THCKD is set, HCKT is an output. See Table 10-2.
10.3.2
ESAI TRANSMIT CONTROL REGISTER (TCR)
The read/write Transmit Control Register (TCR) controls the ESAI transmitter section. Interrupt enable bits for the transmitter section are provided in this control register. Operating modes are also selected in this register. See Figure 10-5.
11 X:$FFFFB5 10 9 8 7 6 5 TE5 4 TE4 3 TE3 2 TE2 1 TE1 0 TE0
TSWS1 TSWS0 TMOD1 TMOD0 TWA TSHFD
23 TLIE
22 TIE
21 TEDIE
20 TEIE
19 TPR
18
17 PADC
16 TFSR
15
14
13
12
TFSL TSWS4 TSWS3 TSWS2
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 10-5 TCR Register Hardware and software reset clear all the bits in the TCR register. The TCR bits are described in the following paragraphs. 10.3.2.1 TCR ESAI Transmit 0 Enable (TE0) - Bit 0 TE0 enables the transfer of data from TX0 to the transmit shift register #0. When TE0 is set and a frame sync is detected, the transmit #0 portion of the ESAI is enabled for that frame. When TE0 is cleared, the transmitter #0 is disabled after completing transmission of data currently in the ESAI transmit shift register. The SDO0 output is tri-stated, and any data present in TX0 is not transmitted (i.e., data can be written to TX0 with TE0 cleared; but data is not transferred to the transmit shift register #0). The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
MOTOROLA
DSP56367
10-15
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
In the network mode, the operation of clearing TE0 and setting it again disables the transmitter #0 after completing transmission of the current data word until the beginning of the next frame. During that time period, the SDO0 pin remains in the high-impedance state.The on-demand mode transmit enable sequence can be the same as the normal mode, or TE0 can be left enabled. 10.3.2.2 TCR ESAI Transmit 1 Enable (TE1) - Bit 1 TE1 enables the transfer of data from TX1 to the transmit shift register #1. When TE1 is set and a frame sync is detected, the transmit #1 portion of the ESAI is enabled for that frame. When TE1 is cleared, the transmitter #1 is disabled after completing transmission of data currently in the ESAI transmit shift register. The SDO1 output is tri-stated, and any data present in TX1 is not transmitted (i.e., data can be written to TX1 with TE1 cleared; but data is not transferred to the transmit shift register #1). The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one. In the network mode, the operation of clearing TE1 and setting it again disables the transmitter #1 after completing transmission of the current data word until the beginning of the next frame. During that time period, the SDO1 pin remains in the high-impedance state. The on-demand mode transmit enable sequence can be the same as the normal mode, or TE1 can be left enabled. 10.3.2.3 TCR ESAI Transmit 2 Enable (TE2) - Bit 2 TE2 enables the transfer of data from TX2 to the transmit shift register #2. When TE2 is set and a frame sync is detected, the transmit #2 portion of the ESAI is enabled for that frame. When TE2 is cleared, the transmitter #2 is disabled after completing transmission of data currently in the ESAI transmit shift register. Data can be written to TX2 when TE2 is cleared but the data is not transferred to the transmit shift register #2. The SDO2/SDI3 pin is the data input pin for RX3 if TE2 is cleared and RE3 in the RCR register is set. If both RE3 and TE2 are cleared the transmitter and receiver are disabled, and the pin is tri-stated. Both RE3 and TE2 should not be set at the same time. The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one. In the network mode, the operation of clearing TE2 and setting it again disables the transmitter #2 after completing transmission of the current data word until the beginning of the next frame. During that time period, the SDO2/SDI3 pin remains in the high-impedance
10-16
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
state. The on-demand mode transmit enable sequence can be the same as the normal mode, or TE2 can be left enabled. 10.3.2.4 TCR ESAI Transmit 3 Enable (TE3) - Bit 3 TE3 enables the transfer of data from TX3 to the transmit shift register #3. When TE3 is set and a frame sync is detected, the transmit #3 portion of the ESAI is enabled for that frame. When TE3 is cleared, the transmitter #3 is disabled after completing transmission of data currently in the ESAI transmit shift register. Data can be written to TX3 when TE3 is cleared but the data is not transferred to the transmit shift register #3. The SDO3/SDI2 pin is the data input pin for RX2 if TE3 is cleared and RE2 in the RCR register is set. If both RE2 and TE3 are cleared the transmitter and receiver are disabled, and the pin is tri-stated. Both RE2 and TE3 should not be set at the same time. The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one. In the network mode, the operation of clearing TE3 and setting it again disables the transmitter #3 after completing transmission of the current data word until the beginning of the next frame. During that time period, the SDO3/SDI2 pin remains in the high-impedance state. The on-demand mode transmit enable sequence can be the same as the normal mode, or TE3 can be left enabled. 10.3.2.5 TCR ESAI Transmit 4 Enable (TE4) - Bit 4 TE4 enables the transfer of data from TX4 to the transmit shift register #4. When TE4 is set and a frame sync is detected, the transmit #4 portion of the ESAI is enabled for that frame. When TE4 is cleared, the transmitter #4 is disabled after completing transmission of data currently in the ESAI transmit shift register. Data can be written to TX4 when TE4 is cleared but the data is not transferred to the transmit shift register #4. The SDO4/SDI1 pin is the data input pin for RX1 if TE4 is cleared and RE1 in the RCR register is set. If both RE1 and TE4 are cleared the transmitter and receiver are disabled, and the pin is tri-stated. Both RE1 and TE4 should not be set at the same time. The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one. In the network mode, the operation of clearing TE4 and setting it again disables the transmitter #4 after completing transmission of the current data word until the beginning of the next frame. During that time period, the SDO4/SDI1 pin remains in the high-impedance
MOTOROLA
DSP56367
10-17
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
state. The on-demand mode transmit enable sequence can be the same as the normal mode, or TE4 can be left enabled. 10.3.2.6 TCR ESAI Transmit 5 Enable (TE5) - Bit 5 TE5 enables the transfer of data from TX5 to the transmit shift register #5. When TE5 is set and a frame sync is detected, the transmit #5 portion of the ESAI is enabled for that frame. When TE5 is cleared, the transmitter #5 is disabled after completing transmission of data currently in the ESAI transmit shift register. Data can be written to TX5 when TE5 is cleared but the data is not transferred to the transmit shift register #5. The SDO5/SDI0 pin is the data input pin for RX0 if TE5 is cleared and RE0 in the RCR register is set. If both RE0 and TE5 are cleared the transmitter and receiver are disabled, and the pin is tri-stated. Both RE0 and TE5 should not be set at the same time. The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one. In the network mode, the operation of clearing TE5 and setting it again disables the transmitter #5 after completing transmission of the current data word until the beginning of the next frame. During that time period, the SDO5/SDI0 pin remains in the high-impedance state. The on-demand mode transmit enable sequence can be the same as the normal mode, or TE5 can be left enabled. 10.3.2.7 TCR Transmit Shift Direction (TSHFD) - Bit 6 The TSHFD bit causes the transmit shift registers to shift data out MSB first when TSHFD equals zero or LSB first when TSHFD equals one (see Figure 10-13 and Figure 10-14). 10.3.2.8 TCR Transmit Word Alignment Control (TWA) - Bit 7 The Transmitter Word Alignment Control (TWA) bit defines the alignment of the data word in relation to the slot. This is relevant for the cases where the word length is shorter than the slot length. If TWA is cleared, the data word is left-aligned in the slot frame during transmission. If TWA is set, the data word is right-aligned in the slot frame during transmission. Since the data word is shorter than the slot length, the data word is extended until achieving the slot length, according to the following rule: 1. If the data word is left-aligned (TWA=0), and zero padding is disabled (PADC=0), then the last data bit is repeated after the data word has been transmitted. If zero padding is enabled (PADC=1), zeroes are transmitted after the data word has been transmitted.
10-18
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
2. If the data word is right-aligned (TWA=1), and zero padding is disabled (PADC=0), then the first data bit is repeated before the transmission of the data word. If zero padding is enabled (PADC=1), zeroes are transmitted before the transmission of the data word. 10.3.2.9 TCR Transmit Network Mode Control (TMOD1-TMOD0) - Bits 8-9 The TMOD1 and TMOD0 bits are used to define the network mode of ESAI transmitters according to Table 10-4. In the normal mode, the frame rate divider determines the word transfer rate - one word is transferred per frame sync during the frame sync time slot, as shown in Figure 10-6. In network mode, it is possible to transfer a word for every time slot, as shown in Figure 10-6. For more details, see Section 10.4, "Operating Modes". In order to comply with AC-97 specifications, TSWS4-TSWS0 should be set to 00011 (20-bit slot, 20-bit word length), TFSL and TFSR should be cleared, and TDC4-TDC0 should be set to $0C (13 words in frame). If TMOD[1:0]=$11 and the above recommendations are followed, the first slot and word will be 16 bits long, and the next 12 slots and words will be 20 bits long, as required by the AC97 protocol. Table 10-4 Transmit Network Mode Selection
TMOD1 0 0 0 1 1 TMOD0 0 1 1 0 1 TDC4-TDC0 $0-$1F $0 $1-$1F X $0C Transmitter Network Mode Normal Mode On-Demand Mode Network Mode Reserved AC97
MOTOROLA
DSP56367
10-19
10-20
SERIAL FRAME SYNC SERIAL DATA DATA NOTE: Interrupts occur and data is transferred once per frame sync.
Normal Mode
ESAI Programming Model
TRANSMITTER INTERRUPT (OR DMA REQUEST) AND FLAGS SET DATA RECEIVER INTERRUPT (OR DMA REQUEST) AND FLAGS SET
Enhanced Serial Audio Interface (ESAI)
Network Mode
SERIAL
Figure 10-6 Normal and Network Operation
DSP56367 MOTOROLA
FRAME SYNC TRANSMITTER INTERRUPTS (OR DMA REQUEST) AND FLAGS SET
SERIAL DATA
SLOT 0
SLOT 1
SLOT 2
SLOT 0
SLOT 1
RECEIVER INTERRUPT (OR DMA REQUEST) AND FLAGS SET NOTE: Interrupts occur and a word may be transferred at every time slot.
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
10.3.2.10 TCR Tx Slot and Word Length Select (TSWS4-TSWS0) - Bits 10-14 The TSWS4-TSWS0 bits are used to select the length of the slot and the length of the data words being transferred via the ESAI. The word length must be equal to or shorter than the slot length. The possible combinations are shown in Table 10-5. See also the ESAI data path programming model in Figure 10-13 and Figure 10-14. Table 10-5 ESAI Transmit Slot and Word Length Selection
TSWS4 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 1 TSWS3 0 0 0 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 TSWS2 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 0 1 1 TSWS1 0 0 0 0 0 1 0 0 1 1 0 0 1 1 1 0 0 1 1 1 TSWS0 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 1 32 24 20 16 SLOT LENGTH 8 12 WORD LENGTH 8 8 12 8 12 16 8 12 16 20 8 12 16 20 24 8 12 16 20 24
MOTOROLA
DSP56367
10-21
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
Table 10-5 ESAI Transmit Slot and Word Length Selection (Continued)
TSWS4 0 0 1 1 1 1 1 1 1 1 1 1 TSWS3 1 1 0 0 0 0 0 1 1 1 1 1 TSWS2 0 1 0 0 1 1 1 0 0 0 1 1 TSWS1 1 1 0 1 0 1 1 0 1 1 0 0 TSWS0 1 0 1 1 0 0 1 1 0 1 0 1 SLOT LENGTH WORD LENGTH
Reserved
10.3.2.11 TCR Transmit Frame Sync Length (TFSL) - Bit 15 The TFSL bit selects the length of frame sync to be generated or recognized. If TFSL is cleared, a word-length frame sync is selected. If TFSL is set, a 1-bit clock period frame sync is selected. See Figure 10-7 for examples of frame length selection.
10-22
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
WORD LENGTH: TFSL=0, RFSL=0
SERIAL CLOCK
RX, TX FRAME SYNC RX, TX SERIAL DATA DATA DATA
NOTE: Frame sync occurs while data is valid. ONE BIT LENGTH: TFSL=1, RFSL=1
SERIAL CLOCK
RX, TX FRAME SYNC RX, TX SERIAL DATA DATA DATA
NOTE: Frame sync occurs for one bit time preceding the data. MIXED FRAME LENGTH: TFSL=1, RFSL=0
SERIAL CLOCK
RX FRAME SYNC RX SERIAL DATA DATA TX FRAME SYNC TX SERIAL DATA DATA DATA DATA
MIXED FRAME LENGTH: TFSL=0, RFSL=1
SERIAL CLOCK
RX FRAME SYNC RX SERIAL DATA DATA DATA
TX FRAME SYNC TX SERIAL DATA DATA DATA
Figure 10-7 Frame Length Selection
MOTOROLA
DSP56367
10-23
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
10.3.2.12 TCR Transmit Frame Sync Relative Timing (TFSR) - Bit 16 TFSR determines the relative timing of the transmit frame sync signal as referred to the serial data lines, for a word length frame sync only (TFSL=0). When TFSR is cleared the word length frame sync occurs together with the first bit of the data word of the first slot. When TFSR is set the word length frame sync starts one serial clock cycle earlier (i.e together with the last bit of the previous data word). 10.3.2.13 TCR Transmit Zero Padding Control (PADC) - Bit 17 When PADC is cleared, zero padding is disabled. When PADC is set, zero padding is enabled. PADC, in conjunction with the TWA control bit, determines the way that padding is done for operating modes where the word length is less than the slot length. See the TWA bit description in Section 10.3.2.8, "TCR Transmit Word Alignment Control (TWA) - Bit 7" for more details. Since the data word is shorter than the slot length, the data word is extended until achieving the slot length, according to the following rule: 1. If the data word is left-aligned (TWA=0), and zero padding is disabled (PADC=0), then the last data bit is repeated after the data word has been transmitted. If zero padding is enabled (PADC=1), zeroes are transmitted after the data word has been transmitted. 2. If the data word is right-aligned (TWA=1), and zero padding is disabled (PADC=0), then the first data bit is repeated before the transmission of the data word. If zero padding is enabled (PADC=1), zeroes are transmitted before the transmission of the data word. 10.3.2.14 TCR Reserved Bit - Bits 18 This bit is reserved. It reads as zero, and it should be written with zero for future compatibility. 10.3.2.15 TCR Transmit Section Personal Reset (TPR) - Bit 19 The TPR control bit is used to put the transmitter section of the ESAI in the personal reset state. The receiver section is not affected. When TPR is cleared, the transmitter section may operate normally. When TPR is set, the transmitter section enters the personal reset state immediately. When in the personal reset state, the status bits are reset to the same state as after hardware reset. The control bits are not affected by the personal reset state. The transmitter data pins are tri-stated while in the personal reset state; if a stable logic level is desired, the transmitter data pins should be defined as GPIO outputs, or external pull-up or pull-down resistors should be used. The transmitter clock outputs drive zeroes while in the personal reset state. Note that to leave the personal reset state by clearing TPR, the procedure described in Section 10.6, "ESAI Initialization Examples" should be followed.
10-24
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
10.3.2.16 TCR Transmit Exception Interrupt Enable (TEIE) - Bit 20 When TEIE is set, the DSP is interrupted when both TDE and TUE in the SAISR status register are set. When TEIE is cleared, this interrupt is disabled. Reading the SAISR status register followed by writing to all the data registers of the enabled transmitters clears TUE, thus clearing the pending interrupt. 10.3.2.17 TCR Transmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21 The TEDIE control bit is used to enable the transmit even slot data interrupts. If TEDIE is set, the transmit even slot data interrupts are enabled. If TEDIE is cleared, the transmit even slot data interrupts are disabled. A transmit even slot data interrupt request is generated if TEDIE is set and the TEDE status flag in the SAISR status register is set. Even time slots are all even-numbered time slots (0, 2, 4, etc.) when operating in network mode. The zero time slot in the frame is marked by the frame sync signal and is considered to be even. Writing data to all the data registers of the enabled transmitters or to TSR clears the TEDE flag, thus servicing the interrupt. Transmit interrupts with exception have higher priority than transmit even slot data interrupts, therefore if exception occurs (TUE is set) and TEIE is set, the ESAI requests an ESAI transmit data with exception interrupt from the interrupt controller. 10.3.2.18 TCR Transmit Interrupt Enable (TIE) - Bit 22 The DSP is interrupted when TIE and the TDE flag in the SAISR status register are set. When TIE is cleared, this interrupt is disabled. Writing data to all the data registers of the enabled transmitters or to TSR clears TDE, thus clearing the interrupt. Transmit interrupts with exception have higher priority than normal transmit data interrupts, therefore if exception occurs (TUE is set) and TEIE is set, the ESAI requests an ESAI transmit data with exception interrupt from the interrupt controller. 10.3.2.19 TCR Transmit Last Slot Interrupt Enable (TLIE) - Bit 23 TLIE enables an interrupt at the beginning of last slot of a frame in network mode. When TLIE is set the DSP is interrupted at the start of the last slot in a frame in network mode regardless of the transmit mask register setting. When TLIE is cleared the transmit last slot interrupt is disabled. TLIE is disabled when TDC[4:0]=$00000 (on-demand mode). The use of the transmit last slot interrupt is described in Section 10.4.3, "ESAI Interrupt Requests".
MOTOROLA
DSP56367
10-25
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
10.3.3
ESAI RECEIVE CLOCK CONTROL REGISTER (RCCR)
The read/write Receive Clock Control Register (RCCR) controls the ESAI receiver clock generator bit and frame sync rates, word length, and number of words per frame for the serial data. The RCCR control bits are described in the following paragraphs (see Figure 10-8).
11 X:$FFFFB8 10 9 8 7 6 5 4 3 2 1 0
RDC2 RDC1 RDC0 RPSR RPM7 RPM6 RPM5 RPM4 RPM3 RPM2 RPM1 RPM0
23
22
21
20
19
18
17
16 RFP2
15 RFP1
14
13
12
RHCK RFSD RCKD RHCKP RFSP RCKP RFP3 D
RFP0 RDC4 RDC3
Figure 10-8 RCCR Register Hardware and software reset clear all the bits of the RCCR register. 10.3.3.1 RCCR Receiver Prescale Modulus Select (RPM7-RPM0) - Bits 7-0 The RPM7-RPM0 bits specify the divide ratio of the prescale divider in the ESAI receiver clock generator. A divide ratio from 1 to 256 (RPM[7:0]=$00 to $FF) may be selected. The bit clock output is available at the receiver serial bit clock (SCKR) pin of the DSP. The bit clock output is also available internally for use as the bit clock to shift the receive shift registers. The ESAI receive clock generator functional diagram is shown in Figure 10-3. 10.3.3.2 RCCR Receiver Prescaler Range (RPSR) - Bit 8 The RPSR controls a fixed divide-by-eight prescaler in series with the variable prescaler. This bit is used to extend the range of the prescaler for those cases where a slower bit clock is desired. When RPSR is set, the fixed prescaler is bypassed. When RPSR is cleared, the fixed divide-by-eight prescaler is operational (see Figure 10-3). The maximum internally generated bit clock frequency is Fosc/4, the minimum internally generated bit clock frequency is Fosc/(2 x 8 x 256)=Fosc/4096. Note: Do not use the combination RPSR=1 and RPM7-RPM0=$00, which causes synchronization problems when using the internal DSP clock as source (RHCKD=1 or RCKD=1).
10.3.3.3 RCCR Rx Frame Rate Divider Control (RDC4-RDC0) - Bits 9-13 The RDC4-RDC0 bits control the divide ratio for the programmable frame rate dividers used to generate the receiver frame clocks.
10-26
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
In network mode, this ratio may be interpreted as the number of words per frame minus one. The divide ratio may range from 2 to 32 (RDC[4:0]=00001 to 11111) for network mode. A divide ratio of one (RDC[4:0]=00000) in network mode is a special case (on-demand mode). In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32 (RDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of one (RDC[4:0]=00000) provides continuous periodic data word transfers. A bit-length frame sync (RFSL=1) must be used in this case. The ESAI frame sync generator functional diagram is shown in Figure 10-4. 10.3.3.4 RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 14-17 The RFP3-RFP0 bits control the divide ratio of the receiver high frequency clock to the receiver serial bit clock when the source of the receiver high frequency clock and the bit clock is the internal DSP clock. When the HCKR input is being driven from an external high frequency clock, the RFP3-RFP0 bits specify an additional division ration in the clock divider chain. See Table 10-6 for the specification of the divide ratio. The ESAI high frequency generator functional diagram is shown in Figure 10-3. Table 10-6 Receiver High Frequency Clock Divider
RFP3-RFP0 $0 $1 $2 $3 ... $F Divide Ratio 1 2 3 4 ... 16
10.3.3.5 RCCR Receiver Clock Polarity (RCKP) - Bit 18 The Receiver Clock Polarity (RCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in. If RCKP is cleared the data and the frame sync are clocked out on the rising edge of the receive bit clock and the frame sync is latched in on the falling edge of the receive bit clock. If RCKP is set the falling edge of the receive clock is used to clock the data and frame sync out and the rising edge of the receive clock is used to latch the frame sync in. 10.3.3.6 RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19 The Receiver Frame Sync Polarity (RFSP) determines the polarity of the receive frame sync signal. When RFSP is cleared the frame sync signal polarity is positive (i.e the frame start is indicated by a high level on the frame sync pin). When RFSP is set the frame sync signal polarity is negative (i.e the frame start is indicated by a low level on the frame sync pin).
MOTOROLA
DSP56367
10-27
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
10.3.3.7 RCCR Receiver High Frequency Clock Polarity (RHCKP) - Bit 20 The Receiver High Frequency Clock Polarity (RHCKP) bit controls on which bit clock edge data and frame sync are clocked out and latched in. If RHCKP is cleared the data and the frame sync are clocked out on the rising edge of the receive bit clock and the frame sync is latched in on the falling edge of the receive bit clock. If RHCKP is set the falling edge of the receive clock is used to clock the data and frame sync out and the rising edge of the receive clock is used to latch the frame sync in. 10.3.3.8 RCCR Receiver Clock Source Direction (RCKD) - Bit 21 The Receiver Clock Source Direction (RCKD) bit selects the source of the clock signal used to clock the receive shift register in the asynchronous mode (SYN=0) and the IF0/OF0 flag direction in the synchronous mode (SYN=1). In the asynchronous mode when RCKD is set, the internal clock source becomes the bit clock for the receive shift registers and word length divider, and is the output on the SCKR pin. In the asynchronous mode when RCKD is cleared, the clock source is external; the internal clock generator is disconnected from the SCKR pin, and an external clock source may drive this pin. In the synchronous mode when RCKD is set, the SCKR pin becomes the OF0 output flag. If RCKD is cleared, then the SCKR pin becomes the IF0 input flag. See Table 10-1 and Table 10-7. Table 10-7 SCKR Pin Definition Table
Control Bits SCKR PIN SYN 0 0 1 1 RCKD 0 1 0 1 SCKR input SCKR output IF0 OF0
10.3.3.9 RCCR Receiver Frame Sync Signal Direction (RFSD) - Bit 22 The Receiver Frame Sync Signal Direction (RFSD) bit selects the source of the receiver frame sync signal when in the asynchronous mode (SYN=0), and the IF1/OF1/Transmitter Buffer Enable flag direction in the synchronous mode (SYN=1). In the asynchronous mode when RFSD is set, the internal clock generator becomes the source of the receiver frame sync, and is the output on the FSR pin. In the asynchronous mode when RFSD is cleared, the receiver frame sync source is external; the internal clock generator is disconnected from the FSR pin, and an external clock source may drive this pin.
10-28
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
In the synchronous mode when RFSD is set, the FSR pin becomes the OF1 output flag or the Transmitter Buffer Enable, according to the TEBE control bit. If RFSD is cleared, then the FSR pin becomes the IF1 input flag. See Table 10-1 and Table 10-8. Table 10-8 FSR Pin Definition Table
Control Bits FSR Pin SYN 0 0 1 1 1 1 TEBE X X 0 0 1 1 RFSD 0 1 0 1 0 1 FSR input FSR output IF1 OF1 reserved Transmitter Buffer Enable
10.3.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23 The Receiver High Frequency Clock Direction (RHCKD) bit selects the source of the receiver high frequency clock when in the asynchronous mode (SYN=0), and the IF2/OF2 flag direction in the synchronous mode (SYN=1). In the asynchronous mode when RHCKD is set, the internal clock generator becomes the source of the receiver high frequency clock, and is the output on the HCKR pin. In the asynchronous mode when RHCKD is cleared, the receiver high frequency clock source is external; the internal clock generator is disconnected from the HCKR pin, and an external clock source may drive this pin. When RHCKD is cleared, HCKR is an input; when RHCKD is set, HCKR is an output. In the synchronous mode when RHCKD is set, the HCKR pin becomes the OF2 output flag. If RHCKD is cleared, then the HCKR pin becomes the IF2 input flag. See Table 10-1 and Table 10-9. Table 10-9 HCKR Pin Definition Table
Control Bits HCKR PIN SYN 0 0 1 1 RHCKD 0 1 0 1 HCKR input HCKR output IF2 OF2
MOTOROLA
DSP56367
10-29
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
10.3.4
ESAI RECEIVE CONTROL REGISTER (RCR)
The read/write Receive Control Register (RCR) controls the ESAI receiver section. Interrupt enable bits for the receivers are provided in this control register. The receivers are enabled in this register (0,1,2 or 3 receivers can be enabled) if the input data pin is not used by a transmitter. Operating modes are also selected in this register.
11 X:$FFFFB7 10 9 8 7 6 RSHFD 5 4 3 RE3 2 RE2 1 RE1 0 RE0
RSWS1 RSWS0 RMOD1 RMOD0 RWA
23 RLIE
22 RIE
21 REDIE
20 REIE
19 RPR
18
17
16 RFSR
15 RFSL
14
13
12
RSWS4 RSWS3 RSWS2
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 10-9 RCR Register Hardware and software reset clear all the bits in the RCR register. The ESAI RCR bits are described in the following paragraphs. 10.3.4.1 RCR ESAI Receiver 0 Enable (RE0) - Bit 0 When RE0 is set and TE5 is cleared, the ESAI receiver 0 is enabled and samples data at the SDO5/SDI0 pin. TX5 and RX0 should not be enabled at the same time (RE0=1 and TE5=1). When RE0 is cleared, receiver 0 is disabled by inhibiting data transfer into RX0. If this bit is cleared while receiving a data word, the remainder of the word is shifted in and transferred to the RX0 data register. If RE0 is set while some of the other receivers are already in operation, the first data word received in RX0 will be invalid and must be discarded. 10.3.4.2 RCR ESAI Receiver 1 Enable (RE1) - Bit 1 When RE1 is set and TE4 is cleared, the ESAI receiver 1 is enabled and samples data at the SDO4/SDI1 pin. TX4 and RX1 should not be enabled at the same time (RE1=1 and TE4=1). When RE1 is cleared, receiver 1 is disabled by inhibiting data transfer into RX1. If this bit is cleared while receiving a data word, the remainder of the word is shifted in and transferred to the RX1 data register. If RE1 is set while some of the other receivers are already in operation, the first data word received in RX1 will be invalid and must be discarded.
10-30
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
10.3.4.3 RCR ESAI Receiver 2 Enable (RE2) - Bit 2 When RE2 is set and TE3 is cleared, the ESAI receiver 2 is enabled and samples data at the SDO3/SDI2 pin. TX3 and RX2 should not be enabled at the same time (RE2=1 and TE3=1). When RE2 is cleared, receiver 2 is disabled by inhibiting data transfer into RX2. If this bit is cleared while receiving a data word, the remainder of the word is shifted in and transferred to the RX2 data register. If RE2 is set while some of the other receivers are already in operation, the first data word received in RX2 will be invalid and must be discarded. 10.3.4.4 RCR ESAI Receiver 3 Enable (RE3) - Bit 3 When RE3 is set and TE2 is cleared, the ESAI receiver 3 is enabled and samples data at the SDO2/SDI3 pin. TX2 and RX3 should not be enabled at the same time (RE3=1 and TE2=1). When RE3 is cleared, receiver 3 is disabled by inhibiting data transfer into RX3. If this bit is cleared while receiving a data word, the remainder of the word is shifted in and transferred to the RX3 data register. If RE3 is set while some of the other receivers are already in operation, the first data word received in RX3 will be invalid and must be discarded. 10.3.4.5 RCR Reserved Bits - Bits 4-5, 17-18 These bits are reserved. They read as zero, and they should be written with zero for future compatibility. 10.3.4.6 RCR Receiver Shift Direction (RSHFD) - Bit 6 The RSHFD bit causes the receiver shift registers to shift data in MSB first when RSHFD is cleared or LSB first when RSHFD is set (see Figure 10-13 and Figure 10-14). 10.3.4.7 RCR Receiver Word Alignment Control (RWA) - Bit 7 The Receiver Word Alignment Control (RWA) bit defines the alignment of the data word in relation to the slot. This is relevant for the cases where the word length is shorter than the slot length. If RWA is cleared, the data word is assumed to be left-aligned in the slot frame. If RWA is set, the data word is assumed to be right-aligned in the slot frame. If the data word is shorter than the slot length, the data bits which are not in the data word field are ignored. For data word lengths of less than 24 bits, the data word is right-extended with zeroes before being stored in the receive data registers. 10.3.4.8 RCR Receiver Network Mode Control (RMOD1-RMOD0) - Bits 8-9 The RMOD1 and RMOD0 bits are used to define the network mode of the ESAI receivers according to Table 10-10. In the normal mode, the frame rate divider determines the word
MOTOROLA
DSP56367
10-31
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
transfer rate - one word is transferred per frame sync during the frame sync time slot, as shown in Figure 10-6. In network mode, it is possible to transfer a word for every time slot, as shown in Figure 10-6. For more details, see Section 10.4, "Operating Modes". In order to comply with AC-97 specifications, RSWS4-RSWS0 should be set to 00011 (20-bit slot, 20-bit word), RFSL and RFSR should be cleared, and RDC4-RDC0 should be set to $0C (13 words in frame). Table 10-10 ESAI Receive Network Mode Selection
RMOD1 0 0 0 1 1 RMOD0 0 1 1 0 1 RDC4-RDC0 $0-$1F $0 $1-$1F X $0C Receiver Network Mode Normal Mode On-Demand Mode Network Mode Reserved AC97
10.3.4.9 RCR Receiver Slot and Word Select (RSWS4-RSWS0) - Bits 10-14 The RSWS4-RSWS0 bits are used to select the length of the slot and the length of the data words being received via the ESAI. The word length must be equal to or shorter than the slot length. The possible combinations are shown in Table 10-11. See also the ESAI data path programming model in Figure 10-13 and Figure 10-14. Table 10-11 ESAI Receive Slot and Word Length Selection
RSWS4 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 RSWS3 0 0 0 1 0 0 1 1 0 0 0 1 1 0 1 RSWS2 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 RSWS1 0 0 0 0 0 1 0 0 1 1 0 0 1 1 1 RSWS0 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 24 20 16 SLOT LENGTH 8 12 WORD LENGTH 8 8 12 8 12 16 8 12 16 20 8 12 16 20 24
10-32
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
Table 10-11 ESAI Receive Slot and Word Length Selection (Continued)
RSWS4 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 RSWS3 1 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 RSWS2 0 1 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 RSWS1 0 0 1 1 1 1 1 0 1 0 1 1 0 1 1 0 0 RSWS0 0 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 Reserved SLOT LENGTH 32 WORD LENGTH 8 12 16 20 24
10.3.4.10 RCR Receiver Frame Sync Length (RFSL) - Bit 15 The RFSL bit selects the length of the receive frame sync to be generated or recognized. If RFSL is cleared, a word-length frame sync is selected. If RFSL is set, a 1-bit clock period frame sync is selected. See Figure 10-7 for examples of frame length selection. 10.3.4.11 RCR Receiver Frame Sync Relative Timing (RFSR) - Bit 16 RFSR determines the relative timing of the receive frame sync signal as referred to the serial data lines, for a word length frame sync only. When RFSR is cleared the word length frame sync occurs together with the first bit of the data word of the first slot. When RFSR is set the word length frame sync starts one serial clock cycle earlier (i.e. together with the last bit of the previous data word). 10.3.4.12 RCR Receiver Section Personal Reset (RPR) - Bit 19 The RPR control bit is used to put the receiver section of the ESAI in the personal reset state. The transmitter section is not affected. When RPR is cleared, the receiver section may operate normally. When RPR is set, the receiver section enters the personal reset state immediately. When in the personal reset state, the status bits are reset to the same state as after hardware reset.The control bits are not affected by the personal reset state.The receiver data pins are disconnected while in the personal reset state. Note that to leave the personal reset state by
MOTOROLA
DSP56367
10-33
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
clearing RPR, the procedure described in Section 10.6, "ESAI Initialization Examples" should be followed. 10.3.4.13 RCR Receive Exception Interrupt Enable (REIE) - Bit 20 When REIE is set, the DSP is interrupted when both RDF and ROE in the SAISR status register are set. When REIE is cleared, this interrupt is disabled. Reading the SAISR status register followed by reading the enabled receivers data registers clears ROE, thus clearing the pending interrupt. 10.3.4.14 RCR Receive Even Slot Data Interrupt Enable (REDIE) - Bit 21 The REDIE control bit is used to enable the receive even slot data interrupts. If REDIE is set, the receive even slot data interrupts are enabled. If REDIE is cleared, the receive even slot data interrupts are disabled. A receive even slot data interrupt request is generated if REDIE is set and the REDF status flag in the SAISR status register is set. Even time slots are all even-numbered time slots (0, 2, 4, etc.) when operating in network mode. The zero time slot is marked by the frame sync signal and is considered to be even. Reading all the data registers of the enabled receivers clears the REDF flag, thus servicing the interrupt. Receive interrupts with exception have higher priority than receive even slot data interrupts, therefore if exception occurs (ROE is set) and REIE is set, the ESAI requests an ESAI receive data with exception interrupt from the interrupt controller. 10.3.4.15 RCR Receive Interrupt Enable (RIE) - Bit 22 The DSP is interrupted when RIE and the RDF flag in the SAISR status register are set. When RIE is cleared, this interrupt is disabled. Reading the receive data registers of the enabled receivers clears RDF, thus clearing the interrupt. Receive interrupts with exception have higher priority than normal receive data interrupts, therefore if exception occurs (ROE is set) and REIE is set, the ESAI requests an ESAI receive data with exception interrupt from the interrupt controller. 10.3.4.16 RCR Receive Last Slot Interrupt Enable (RLIE) - Bit 23 RLIE enables an interrupt after the last slot of a frame ended in network mode only. When RLIE is set the DSP is interrupted after the last slot in a frame ended regardless of the receive mask register setting. When RLIE is cleared the receive last slot interrupt is disabled. Hardware and software reset clear RLIE. RLIE is disabled when RDC[4:0]=00000 (on-demand mode). The use of the receive last slot interrupt is described in Section 10.4.3, "ESAI Interrupt Requests".
10-34
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
10.3.5
ESAI COMMON CONTROL REGISTER (SAICR)
The read/write Common Control Register (SAICR) contains control bits for functions that affect both the receive and transmit sections of the ESAI. See Figure 10-10.
11 X:$FFFFB4 10 9 8 ALC 7 TEBE 6 SYN 5 4 3 2 OF2 1 OF1 0 OF0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 10-10 SAICR Register Hardware and software reset clear all the bits in the SAICR register. 10.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0 The Serial Output Flag 0 (OF0) is a data bit used to hold data to be send to the OF0 pin. When the ESAI is in the synchronous clock mode (SYN=1), the SCKR pin is configured as the ESAI flag 0. If the receiver serial clock direction bit (RCKD) is set, the SCKR pin is the output flag OF0, and data present in the OF0 bit is written to the OF0 pin at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode. 10.3.5.2 SAICR Serial Output Flag 1 (OF1) - Bit 1 The Serial Output Flag 1 (OF1) is a data bit used to hold data to be send to the OF1 pin. When the ESAI is in the synchronous clock mode (SYN=1), the FSR pin is configured as the ESAI flag 1. If the receiver frame sync direction bit (RFSD) is set and the TEBE bit is cleared, the FSR pin is the output flag OF1, and data present in the OF1 bit is written to the OF1 pin at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode. 10.3.5.3 SAICR Serial Output Flag 2 (OF2) - Bit 2 The Serial Output Flag 2 (OF2) is a data bit used to hold data to be send to the OF2 pin. When the ESAI is in the synchronous clock mode (SYN=1), the HCKR pin is configured as the ESAI flag 2. If the receiver high frequency clock direction bit (RHCKD) is set, the HCKR pin is the output flag OF2, and data present in the OF2 bit is written to the OF2 pin at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode.
MOTOROLA
DSP56367
10-35
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
10.3.5.4 SAICR Reserved Bits - Bits 3-5, 9-23 These bits are reserved. They read as zero, and they should be written with zero for future compatibility. 10.3.5.5 SAICR Synchronous Mode Selection (SYN) - Bit 6 The Synchronous Mode Selection (SYN) bit controls whether the receiver and transmitter sections of the ESAI operate synchronously or asynchronously with respect to each other (see Figure 10-11). When SYN is cleared, the asynchronous mode is chosen and independent clock and frame sync signals are used for the transmit and receive sections. When SYN is set, the synchronous mode is chosen and the transmit and receive sections use common clock and frame sync signals. When in the synchronous mode (SYN=1), the transmit and receive sections use the transmitter section clock generator as the source of the clock and frame sync for both sections. Also, the receiver clock pins SCKR, FSR and HCKR now operate as I/O flags. See Table 10-7, Table 10-8 and Table 10-9 for the effects of SYN on the receiver clock pins. 10.3.5.6 SAICR Transmit External Buffer Enable (TEBE) - Bit 7 The Transmitter External Buffer Enable (TEBE) bit controls the function of the FSR pin when in the synchronous mode. If the ESAI is configured for operation in the synchronous mode (SYN=1), and TEBE is set while FSR pin is configured as an output (RFSD=1), the FSR pin functions as the transmitter external buffer enable control, to enable the use of an external buffers on the transmitter outputs. If TEBE is cleared then the FSR pin functions as the serial I/O flag 1. See Table 10-8 for a summary of the effects of TEBE on the FSR pin. 10.3.5.7 SAICR Alignment Control (ALC) - Bit 8 The ESAI is designed for 24-bit fractional data, thus shorter data words are left aligned to the MSB (bit 23). Some applications use 16-bit fractional data. In those cases, shorter data words may be left aligned to bit 15. The Alignment Control (ALC) bit supports these applications. If ALC is set, transmitted and received words are left aligned to bit 15 in the transmit and receive shift registers. If ALC is cleared, transmitted and received word are left aligned to bit 23 in the transmit and receive shift registers. Note: While ALC is set, 20-bit and 24-bit words may not be used, and word length control should specify 8-, 12- or 16-bit words, otherwise results are unpredictable.
10-36
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
ASYNCHRONOUS (SYN=0) TRANSMITTER SDO CLOCK EXTERNAL TRANSMIT CLOCK SCKT ESAI BIT CLOCK SCKR CLOCK FRAME SYNC SDI RECEIVER INTERNAL CLOCK INTERNAL FRAME SYNC FRAME SYNC EXTERNAL TRANSMIT FRAME SYNC FST
EXTERNAL RECEIVE CLOCK
EXTERNAL RECEIVE FRAME SYNC FSR
NOTE: Transmitter and receiver may have different clocks and frame syncs.
SYNCHRONOUS (SYN=1) TRANSMITTER SDO CLOCK EXTERNAL CLOCK SCKT ESAI BIT CLOCK INTERNAL CLOCK FRAME SYNC EXTERNAL FRAME SYNC FST INTERNAL FRAME SYNC
CLOCK
FRAME SYNC SDI RECEIVER
NOTE: Transmitter and receiver have the same clocks and frame syncs.
Figure 10-11 SAICR SYN Bit Operation
MOTOROLA
DSP56367
10-37
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
10.3.6
ESAI STATUS REGISTER (SAISR)
The Status Register (SAISR) is a read-only status register used by the DSP to read the status and serial input flags of the ESAI. See Figure 10-12. The status bits are described in the following paragraphs.
11 X:$FFFFB3 10 9 8 RDF 7 ROE 6 RFS 5 4 3 2 IF2 1 IF1 0 IF0
RODF REDF
23
22
21
20
19
18
17
16
15 TDE
14 TUE
13 TFS
12
TODE TEDE
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 10-12 SAISR Register 10.3.6.1 SAISR Serial Input Flag 0 (IF0) - Bit 0 The IF0 bit is enabled only when the SCKR pin is defined as ESAI in the Port Control Register, SYN=1 and RCKD=0, indicating that SCKR is an input flag and the synchronous mode is selected. Data present on the SCKR pin is latched during reception of the first received data bit after frame sync is detected. The IF0 bit is updated with this data when the receiver shift registers are transferred into the receiver data registers. IF0 reads as a zero when it is not enabled. Hardware, software, ESAI individual, and STOP reset clear IF0. 10.3.6.2 SAISR Serial Input Flag 1 (IF1) - Bit 1 The IF1 bit is enabled only when the FSR pin is defined as ESAI in the Port Control Register, SYN =1, RFSD=0 and TEBE=0, indicating that FSR is an input flag and the synchronous mode is selected. Data present on the FSR pin is latched during reception of the first received data bit after frame sync is detected. The IF1 bit is updated with this data when the receiver shift registers are transferred into the receiver data registers. IF1 reads as a zero when it is not enabled. Hardware, software, ESAI individual, and STOP reset clear IF1. 10.3.6.3 SAISR Serial Input Flag 2 (IF2) - Bit 2 The IF2 bit is enabled only when the HCKR pin is defined as ESAI in the Port Control Register, SYN=1 and RHCKD=0, indicating that HCKR is an input flag and the synchronous mode is selected. Data present on the HCKR pin is latched during reception of the first received data bit after frame sync is detected. The IF2 bit is updated with this data when the receive shift registers are transferred into the receiver data registers. IF2 reads as a zero when it is not enabled. Hardware, software, ESAI individual, and STOP reset clear IF2.
10-38
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
10.3.6.4 SAISR Reserved Bits - Bits 3-5, 11-12, 18-23 These bits are reserved for future use. They read as zero. 10.3.6.5 SAISR Receive Frame Sync Flag (RFS) - Bit 6 When set, RFS indicates that a receive frame sync occurred during reception of the words in the receiver data registers. This indicates that the data words are from the first slot in the frame. When RFS is clear and a word is received, it indicates (only in the network mode) that the frame sync did not occur during reception of that word. RFS is cleared by hardware, software, ESAI individual, or STOP reset. RFS is valid only if at least one of the receivers is enabled (REx=1). Note: In normal mode, RFS always reads as a one when reading data because there is only one time slot per frame - the "frame sync" time slot.
10.3.6.6 SAISR Receiver Overrun Error Flag (ROE) - Bit 7 The ROE flag is set when the serial receive shift register of an enabled receiver is full and ready to transfer to its receiver data register (RXx) and the register is already full (RDF=1). If REIE is set, an ESAI receive data with exception (overrun error) interrupt request is issued when ROE is set. Hardware, software, ESAI individual, and STOP reset clear ROE. ROE is also cleared by reading the SAISR with ROE set, followed by reading all the enabled receive data registers. 10.3.6.7 SAISR Receive Data Register Full (RDF) - Bit 8 RDF is set when the contents of the receive shift register of an enabled receiver is transferred to the respective receive data register. RDF is cleared when the DSP reads the receive data register of all enabled receivers or cleared by hardware, software, ESAI individual, or STOP reset. If RIE is set, an ESAI receive data interrupt request is issued when RDF is set. 10.3.6.8 SAISR Receive Even-Data Register Full (REDF) - Bit 9 When set, REDF indicates that the received data in the receive data registers of the enabled receivers have arrived during an even time slot when operating in the network mode. Even time slots are all even-numbered slots (0, 2, 4, 6, etc.). Time slots are numbered from zero to N-1, where N is the number of time slots in the frame. The zero time slot is considered even. REDF is set when the contents of the receive shift registers are transferred to the receive data registers. REDF is cleared when the DSP reads all the enabled receive data registers or cleared by hardware, software, ESAI individual, or STOP resets. If REDIE is set, an ESAI receive even slot data interrupt request is issued when REDF is set. 10.3.6.9 SAISR Receive Odd-Data Register Full (RODF) - Bit 10 When set, RODF indicates that the received data in the receive data registers of the enabled receivers have arrived during an odd time slot when operating in the network mode. Odd time slots are all odd-numbered slots (1, 3, 5, etc.). Time slots are numbered from zero to N-1, where N is the number of time slots in the frame. RODF is set when the contents of the receive
MOTOROLA
DSP56367
10-39
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
shift registers are transferred to the receive data registers. RODF is cleared when the DSP reads all the enabled receive data registers or cleared by hardware, software, ESAI individual, or STOP resets. 10.3.6.10 SAISR Transmit Frame Sync Flag (TFS) - Bit 13 When set, TFS indicates that a transmit frame sync occurred in the current time slot. TFS is set at the start of the first time slot in the frame and cleared during all other time slots. Data written to a transmit data register during the time slot when TFS is set is transmitted (in network mode), if the transmitter is enabled, during the second time slot in the frame. TFS is useful in network mode to identify the start of a frame. TFS is cleared by hardware, software, ESAI individual, or STOP reset. TFS is valid only if at least one transmitter is enabled (i.e. one or more of TE0, TE1, TE2, TE3, TE4 and TE5 are set). Note: In normal mode, TFS always reads as a one when transmitting data because there is only one time slot per frame - the "frame sync" time slot.
10.3.6.11 SAISR Transmit Underrun Error Flag (TUE) - Bit 14 TUE is set when at least one of the enabled serial transmit shift registers is empty (no new data to be transmitted) and a transmit time slot occurs. When a transmit underrun error occurs, the previous data (which is still present in the TX registers that were not written) is retransmitted. If TEIE is set, an ESAI transmit data with exception (underrun error) interrupt request is issued when TUE is set. Hardware, software, ESAI individual, and STOP reset clear TUE. TUE is also cleared by reading the SAISR with TUE set, followed by writing to all the enabled transmit data registers or to TSR. 10.3.6.12 SAISR Transmit Data Register Empty (TDE) - Bit 15 TDE is set when the contents of the transmit data register of all the enabled transmitters are transferred to the transmit shift registers; it is also set for a TSR disabled time slot period in network mode (as if data were being transmitted after the TSR was written). When set, TDE indicates that data should be written to all the TX registers of the enabled transmitters or to the time slot register (TSR). TDE is cleared when the DSP writes to all the transmit data registers of the enabled transmitters, or when the DSP writes to the TSR to disable transmission of the next time slot. If TIE is set, an ESAI transmit data interrupt request is issued when TDE is set. Hardware, software, ESAI individual, and STOP reset clear TDE. 10.3.6.13 SAISR Transmit Even-Data Register Empty (TEDE) - Bit 16 When set, TEDE indicates that the enabled transmitter data registers became empty at the beginning of an even time slot. Even time slots are all even-numbered slots (0, 2, 4, 6, etc.). Time slots are numbered from zero to N-1, where N is the number of time slots in the frame. The zero time slot is considered even. This flag is set when the contents of the transmit data register of all the enabled transmitters are transferred to the transmit shift registers; it is also set for a TSR disabled time slot period in network mode (as if data were being transmitted after the TSR was written). When set, TEDE indicates that data should be written to all the TX
10-40
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
registers of the enabled transmitters or to the time slot register (TSR). TEDE is cleared when the DSP writes to all the transmit data registers of the enabled transmitters, or when the DSP writes to the TSR to disable transmission of the next time slot. If TIE is set, an ESAI transmit data interrupt request is issued when TEDE is set. Hardware, software, ESAI individual, and STOP reset clear TEDE. 10.3.6.14 SAISR Transmit Odd-Data Register Empty (TODE) - Bit 17 When set, TODE indicates that the enabled transmitter data registers became empty at the beginning of an odd time slot. Odd time slots are all odd-numbered slots (1, 3, 5, etc.). Time slots are numbered from zero to N-1, where N is the number of time slots in the frame. This flag is set when the contents of the transmit data register of all the enabled transmitters are transferred to the transmit shift registers; it is also set for a TSR disabled time slot period in network mode (as if data were being transmitted after the TSR was written). When set, TODE indicates that data should be written to all the TX registers of the enabled transmitters or to the time slot register (TSR). TODE is cleared when the DSP writes to all the transmit data registers of the enabled transmitters, or when the DSP writes to the TSR to disable transmission of the next time slot. If TIE is set, an ESAI transmit data interrupt request is issued when TODE is set. Hardware, software, ESAI individual, and STOP reset clear TODE.
MOTOROLA
DSP56367
10-41
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
23 RECEIVE HIGH BYTE 7 23 SERIAL RECEIVE SHIFT REGISTER RECEIVE HIGH BYTE 7
16 15 RECEIVE MIDDLE BYTE 0 7
87 RECEIVE LOW BYTE 07 87 RECEIVE MIDDLE BYTE RECEIVE LOW BYTE 07 20 BIT 16 BIT 12 BIT 8 BIT
0 ESAI RECEIVE DATA REGISTER (READ ONLY) 0 0
16 15
0
7
0
24 BIT
SDI
MSB 8-BIT DATA MSB
LSB 0 LSB LSB 16-BIT DATA LSB LSB 24-BIT DATA 0 0 0
RSWS4RSWS0 LEAST SIGNIFICANT ZERO FILL
12-BIT DATA MSB MSB MSB
20-BIT DATA
(a) Receive Registers
23 TRANSMIT HIGH BYTE 7 23 SDO 7 MSB 8-BIT DATA MSB 12-BIT DATA MSB 16-BIT DATA MSB MSB 24-BIT DATA 20-BIT DATA LSB TRANSMIT HIGH BYTE 0 LSB * LSB LSB * * 7 0 7 16 15 TRANSMIT MIDDLE BYTE 07 87 TRANSMIT MIDDLE BYTE 07 87
NOTES: 1. Data is received MSB first if RSHFD=0. 2. 24-bit fractional format (ALC=0). 3. 32-bit mode is not shown. 0 TRANSMIT LOW BYTE 0 0 TRANSMIT LOW BYTE 0 * * - LEAST SIGNIFICANT BIT FILL ESAI TRANSMIT SHIFT REGISTER ESAI TRANSMIT DATA REGISTER (WRITE ONLY)
16 15
LSB NOTES: 1. Data is sent MSB first if TSHFD=0. 2. 24-bit fractional format (ALC=0). 3. 32-bit mode is not shown. 4. Data word is left-aligned (TWA=0,PADC=0).
(b) Transmit Registers
Figure 10-13 ESAI Data Path Programming Model ([R/T]SHFD=0)
10-42
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
23 RECEIVE HIGH BYTE 7 23 SDI 7 MSB 8-BIT DATA MSB RECEIVE HIGH BYTE
16 15 RECEIVE MIDDLE BYTE 0 7
87 RECEIVE LOW BYTE 07 87 RECEIVE MIDDLE BYTE RECEIVE LOW BYTE 07
0 ESAI RECEIVE DATA REGISTER (READ ONLY) 0 0 ESAI RECEIVE SHIFT REGISTER 0 LEAST SIGNIFICANT ZERO FILL
16 15
0 LSB
7
0 LSB
0
0
0
12-BIT DATA MSB 16-BIT DATA MSB MSB
LSB LSB LSB 24-BIT DATA NOTES: 1. Data is received LSB first if RSHFD=1. 2. 24-bit fractional format (ALC=0). 3. 32-bit mode is not shown. 16 15 87 TRANSMIT MIDDLE BYTE 0 7 07 87 TRANSMIT MIDDLE BYTE 0 7 07 20 BIT 16 BIT 12 BIT 8 BIT SDO TRANSMIT LOW BYTE TRANSMIT LOW BYTE 0 ESAI TRANSMIT DATA 0 REGISTER (WRITE ONLY) ESAI TRANSMIT SHIFT REGISTER 0 24 BIT 0
20-BIT DATA
(a) Receive Registers
23 TRANSMIT HIGH BYTE 7 23 TRANSMIT HIGH BYTE 7
16 15
MSB 8-BIT DATA MSB
LSB 0 LSB 12-BIT DATA LSB 16-BIT DATA 0 0 0
TSWS4TSWS0
MSB
MSB MSB
20-BIT DATA 24-BIT DATA
LSB LSB NOTES: 1. Data is sent LSB first if TSHFD=1. 2. 24-bit fractional format (ALC=0). 3. 32-bit mode is not shown. 4. Data word is left aligned (TWA=0,PADC=1).
(b) Transmit Registers
Figure 10-14 ESAI Data Path Programming Model ([R/T]SHFD=1)
MOTOROLA
DSP56367
10-43
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
10.3.7
ESAI RECEIVE SHIFT REGISTERS
The receive shift registers (see Figure 10-13 and Figure 10-14) receive the incoming data from the serial receive data pins. Data is shifted in by the selected (internal/external) bit clock when the associated frame sync I/O is asserted. Data is assumed to be received MSB first if RSHFD=0 and LSB first if RSHFD=1. Data is transferred to the ESAI receive data registers after 8, 12, 16, 20, 24, or 32 serial clock cycles were counted, depending on the slot length control bits in the RCR register.
10.3.8
ESAI RECEIVE DATA REGISTERS (RX3, RX2, RX1, RX0)
RX3, RX2, RX1 and RX0 are 24-bit read-only registers that accept data from the receive shift registers when they become full (see Figure 10-13 and Figure 10-14). The data occupies the most significant portion of the receive data registers, according to the ALC control bit setting. The unused bits (least significant portion, and 8 most significant bits when ALC=1) read as zeros. The DSP is interrupted whenever RXx becomes full if the associated interrupt is enabled.
10.3.9
ESAI TRANSMIT SHIFT REGISTERS
The transmit shift registers contain the data being transmitted (see Figure 10-13 and Figure 10-14). Data is shifted out to the serial transmit data pins by the selected (internal/external) bit clock when the associated frame sync I/O is asserted. The number of bits shifted out before the shift registers are considered empty and may be written to again can be 8, 12, 16, 20, 24 or 32 bits (determined by the slot length control bits in the TCR register). Data is shifted out of these registers MSB first if TSHFD=0 and LSB first if TSHFD=1.
10.3.10
ESAI TRANSMIT DATA REGISTERS (TX5, TX4, TX3, TX2,TX1,TX0)
TX5, TX4, TX3, TX2, TX1 and TX0 are 24-bit write-only registers. Data to be transmitted is written into these registers and is automatically transferred to the transmit shift registers (see Figure 10-13 and Figure 10-14). The data written (8, 12, 16, 20 or 24 bits) should occupy the most significant portion of the TXx according to the ALC control bit setting. The unused bits (least significant portion, and the 8 most significant bits when ALC=1) of the TXx are don't care bits. The DSP is interrupted whenever the TXx becomes empty if the transmit data register empty interrupt has been enabled.
10-44
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
10.3.11
ESAI TIME SLOT REGISTER (TSR)
The write-only Time Slot Register (TSR) is effectively a null data register that is used when the data is not to be transmitted in the available transmit time slot. The transmit data pins of all the enabled transmitters are in the high-impedance state for the respective time slot where TSR has been written. The Transmitter External Buffer Enable pin (FSR pin when SYN=1, TEBE=1, RFSD=1) disables the external buffers during the slot when the TSR register has been written.
10.3.12
TRANSMIT SLOT MASK REGISTERS (TSMA, TSMB)
The Transmit Slot Mask Registers (TSMA and TSMB) are two read/write registers used by the transmitters in network mode to determine for each slot whether to transmit a data word and generate a transmitter empty condition (TDE=1), or to tri-state the transmitter data pins. TSMA and TSMB should each be considered as containing half a 32-bit register TSM. See Figure 10-15 and Figure 10-16. Bit number N in TSM (TS**) is the enable/disable control bit for transmission in slot number N.
11 X:$FFFFB9 TS11 10 TS10 9 TS9 8 TS8 7 TS7 6 TS6 5 TS5 4 TS4 3 TS3 2 TS2 1 TS1 0 TS0
23
22
21
20
19
18
17
16
15 TS15
14 TS14
13 TS13
12 TS12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 10-15 TSMA Register
11 X:$FFFFBA TS27 10 TS26 9 TS25 8 TS24 7 TS23 6 TS22 5 TS21 4 TS20 3 TS19 2 TS18 1 TS17 0 TS16
23
22
21
20
19
18
17
16
15 TS31
14 TS30
13 TS29
12 TS28
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 10-16 TSMB Register
MOTOROLA
DSP56367
10-45
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
When bit number N in TSM is cleared, all the transmit data pins of the enabled transmitters are tri-stated during transmit time slot number N. The data is still transferred from the transmit data registers to the transmit shift registers but neither the TDE nor the TUE flags are set. This means that during a disabled slot, no transmitter empty interrupt is generated. The DSP is interrupted only for enabled slots. Data that is written to the transmit data registers when servicing this request is transmitted in the next enabled transmit time slot. When bit number N in TSM register is set, the transmit sequence is as usual: data is transferred from the TX registers to the shift registers, transmitted during slot number N, and the TDE flag is set. Using the slot mask in TSM does not conflict with using TSR. Even if a slot is enabled in TSM, the user may chose to write to TSR instead of writing to the transmit data registers TXx. This causes all the transmit data pins of the enabled transmitters to be tri-stated during the next slot. Data written to the TSM affects the next frame transmission. The frame being transmitted is not affected by this data and would comply to the last TSM setting. Data read from TSM returns the last written data. After hardware or software reset, the TSM register is preset to $FFFFFFFF, which means that all 32 possible slots are enabled for data transmission. Note: When operating in normal mode, bit 0 of the mask register must be set, otherwise no output is generated.
10.3.13
RECEIVE SLOT MASK REGISTERS (RSMA, RSMB)
The Receive Slot Mask Registers (RSMA and RSMB) are two read/write registers used by the receiver in network mode to determine for each slot whether to receive a data word and generate a receiver full condition (RDF=1), or to ignore the received data. RSMA and RSMB should be considered as each containing half of a 32-bit register RSM. See Table 10-17 and
10-46
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Programming Model
Table 10-18. Bit number N in RSM (RS**) is an enable/disable control bit for receiving data in slot number N.
11 X:$FFFFBB RS11 10 RS10 9 RS9 8 RS8 7 RS7 6 RS6 5 RS5 4 RS4 3 RS3 2 RS2 1 RS1 0 RS0
23
22
21
20
19
18
17
16
15 RS15
14 RS14
13 RS13
12 RS12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 10-17 RSMA Register
11 X:$FFFFBC RS27
10 RS26
9 RS25
8 RS24
7 RS23
6 RS22
5 RS21
4 RS20
3 RS19
2 RS18
1 RS17
0 RS16
23
22
21
20
19
18
17
16
15 RS31
14 RS30
13 RS29
12 RS28
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 10-18 RSMB Register When bit number N in the RSM register is cleared, the data from the enabled receivers input pins are shifted into their receive shift registers during slot number N. The data is not transferred from the receive shift registers to the receive data registers, and neither the RDF nor the ROE flags are set. This means that during a disabled slot, no receiver full interrupt is generated. The DSP is interrupted only for enabled slots. When bit number N in the RSM is set, the receive sequence is as usual: data which is shifted into the enabled receivers shift registers is transferred to the receive data registers and the RDF flag is set. Data written to the RSM affects the next received frame. The frame being received is not affected by this data and would comply to the last RSM setting. Data read from RSM returns the last written data.
MOTOROLA
DSP56367
10-47
Enhanced Serial Audio Interface (ESAI) Operating Modes
After hardware or software reset, the RSM register is preset to $FFFFFFFF, which means that all 32 possible slots are enabled for data reception. Note: When operating in normal mode, bit 0 of the mask register must be set to one, otherwise no input is received.
10.4
OPERATING MODES
ESAI operating mode are selected by the ESAI control registers (TCCR, TCR, RCCR, RCR and SAICR). The main operating mode are described in the following paragraphs.
10.4.1
ESAI AFTER RESET
Hardware or software reset clears the port control register bits and the port direction control register bits, which configure all ESAI I/O pins as disconnected. The ESAI is in the individual reset state while all ESAI pins are programmed as GPIO or disconnected, and is active only if at least one of the ESAI I/O pins is programmed as an ESAI pin.
10.4.2
ESAI INITIALIZATION
The correct way to initialize the ESAI is as follows: 1. Hardware, software, ESAI individual, or STOP reset. 2. Program ESAI control and time slot registers. 3. Write data to all the enabled transmitters. 4. Configure at least one pin as ESAI pin. During program execution, all ESAI pins may be defined as GPIO or disconnected, causing the ESAI to stop serial activity and enter the individual reset state. All status bits of the interface are set to their reset state; however, the control bits are not affected. This procedure allows the DSP programmer to reset the ESAI separately from the other internal peripherals. During individual reset, internal DMA accesses to the data registers of the ESAI are not valid and data read is undefined. The DSP programmer must use an individual ESAI reset when changing the ESAI control registers (except for TEIE, REIE, TLIE, RLIE, TIE, RIE, TE0-TE5, RE0-RE3) to ensure proper operation of the interface.
10-48
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) Operating Modes
Note:
If the ESAI receiver section is already operating with some of the receivers, enabling additional receivers on the fly (i.e. without first putting the ESAI receiver in the personal reset state) by setting their REx control bits will result in erroneous data being received as the first data word for the newly enabled receivers.
10.4.3
ESAI INTERRUPT REQUESTS
The ESAI can generate eight different interrupt requests (ordered from the highest to the lowest priority): 1. ESAI Receive Data with Exception Status. Occurs when the receive exception interrupt is enabled (REIE=1 in the RCR register), at least one of the enabled receive data registers is full (RDF=1), and a receiver overrun error has occurred (ROE=1 in the SAISR register). ROE is cleared by first reading the SAISR and then reading all the enabled receive data registers. 2. ESAI Receive Even Data Occurs when the receive even slot data interrupt is enabled (REDIE=1), at least one of the enabled receive data registers is full (RDF=1), the data is from an even slot (REDF=1), and no exception has occurred (ROE=0 or REIE=0). Reading all enabled receiver data registers clears RDF and REDF. 3. ESAI Receive Data Occurs when the receive interrupt is enabled (RIE=1), at least one of the enabled receive data registers is full (RDF=1), no exception has occurred (ROE=0 or REIE=0), and no even slot interrupt has occurred (REDF=0 or REDIE=0). Reading all enabled receiver data registers clears RDF. 4. ESAI Receive Last Slot Interrupt Occurs, if enabled (RLIE=1), after the last slot of the frame ended (in network mode only) regardless of the receive mask register setting. The receive last slot interrupt may be used for resetting the receive mask slot register, reconfiguring the DMA channels and reassigning data memory pointers. Using the receive last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame is serviced with the new setting without synchronization problems. Note that the maximum receive last slot interrupt service time should not exceed N-1 ESAI bits service time (where N is the number of bits in a slot). 5. ESAI Transmit Data with Exception Status Occurs when the transmit exception interrupt is enabled (TEIE=1), at least one transmit data register of the enabled transmitters is empty (TDE=1), and a transmitter underrun error has occurred (TUE=1). TUE is cleared by first reading the SAISR and then writing to all the enabled transmit data registers, or to the TSR register.
MOTOROLA
DSP56367
10-49
Enhanced Serial Audio Interface (ESAI) Operating Modes
6. ESAI Transmit Last Slot Interrupt Occurs, if enabled (TLIE=1), at the start of the last slot of the frame in network mode regardless of the transmit mask register setting. The transmit last slot interrupt may be used for resetting the transmit mask slot register, reconfiguring the DMA channels and reassigning data memory pointers. Using the transmit last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame is serviced with the new setting without synchronization problems. Note that the maximum transmit last slot interrupt service time should not exceed N-1 ESAI bits service time (where N is the number of bits in a slot). 7. ESAI Transmit Even Data Occurs when the transmit even slot data interrupt is enabled (TEDIE=1), at least one of the enabled transmit data registers is empty (TDE=1), the slot is an even slot (TEDE=1), and no exception has occurred (TUE=0 or TEIE=0). Writing to all the TX registers of the enabled transmitters or to TSR clears this interrupt request. 8. ESAI Transmit Data Occurs when the transmit interrupt is enabled (TIE=1), at least one of the enabled transmit data registers is empty (TDE=1), no exception has occurred (TUE=0 or TEIE=0), and no even slot interrupt has occurred (TEDE=0 or TEDIE=0). Writing to all the TX registers of the enabled transmitters, or to the TSR clears this interrupt request.
10.4.4
OPERATING MODES - NORMAL, NETWORK, AND ON-DEMAND
The ESAI has three basic operating modes and many data/operation formats. 10.4.4.1 Normal/Network/On-Demand Mode Selection Selecting between the normal mode and network mode is accomplished by clearing or setting the TMOD0-TMOD1 bits in the TCR register for the transmitter section, and in the RMOD0-RMOD1 bits in the RCR register for the receiver section. For normal mode, the ESAI functions with one data word of I/O per frame (per enabled transmitter or receiver). The normal mode is typically used to transfer data to/from a single device. For the network mode, 2 to 32 time slots per frame may be selected. During each frame, 0 to 32 data words of I/O may be received/transmitted. In either case, the transfers are periodic. The frame sync signal indicates the first time slot in the frame. Network mode is typically
10-50
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) Operating Modes
used in time division multiplexed (TDM) networks of codecs, DSPs with multiple words per frame, or multi-channel devices. Selecting the network mode and setting the frame rate divider to zero (DC=00000) selects the on-demand mode. This special case does not generate a periodic frame sync. A frame sync pulse is generated only when data is available to transmit. The on-demand mode requires that the transmit frame sync be internal (output) and the receive frame sync be external (input). Therefore, for simplex operation, the synchronous mode could be used; however, for full-duplex operation, the asynchronous mode must be used. Data transmission that is data driven is enabled by writing data into each TX. Although the ESAI is double buffered, only one word can be written to each TX, even if the transmit shift register is empty. The receive and transmit interrupts function as usual using TDE and RDF; however, transmit underruns are impossible for on-demand transmission and are disabled. 10.4.4.2 Synchronous/Asynchronous Operating Modes The transmit and receive sections of the ESAI may be synchronous or asynchronous - i.e., the transmitter and receiver sections may use common clock and synchronization signals (synchronous operating mode), or they may have their own separate clock and sync signals (asynchronous operating mode). The SYN bit in the SAICR register selects synchronous or asynchronous operation. Since the ESAI is designed to operate either synchronously or asynchronously, separate receive and transmit interrupts are provided. When SYN is cleared, the ESAI transmitter and receiver clocks and frame sync sources are independent. If SYN is set, the ESAI transmitter and receiver clocks and frame sync come from the transmitter section (either external or internal sources). Data clock and frame sync signals can be generated internally by the DSP or may be obtained from external sources. If internally generated, the ESAI clock generator is used to derive high frequency clock, bit clock and frame sync signals from the DSP internal system clock. 10.4.4.3 Frame Sync Selection The frame sync can be either a bit-long or word-long signal. The transmitter frame format is defined by the TFSL bit in the TCR register. The receiver frame format is defined by the RFSL bit in the RCR register. 1. In the word-long frame sync format, the frame sync signal is asserted during the entire word data transfer period. This frame sync length is compatible with Motorola codecs, SPI serial peripherals, serial A/D and D/A converters, shift registers, and telecommunication PCM serial I/O. 2. In the bit-long frame sync format, the frame sync signal is asserted for one bit clock immediately before the data transfer period. This frame sync length is compatible with Intel and National components, codecs, and telecommunication PCM serial I/O.
MOTOROLA
DSP56367
10-51
Enhanced Serial Audio Interface (ESAI) Operating Modes
The relative timing of the word length frame sync as referred to the data word is specified by the TFSR bit in the TCR register for the transmitter section, and by the RFSR bit in the RCR register for the receive section. The word length frame sync may be generated (or expected) with the first bit of the data word, or with the last bit of the previous word. TFSR and RFSR are ignored when a bit length frame sync is selected. Polarity of the frame sync signal may be defined as positive (asserted high) or negative (asserted low). The TFSP bit in the TCCR register specifies the polarity of the frame sync for the transmitter section. The RFSP bit in the RCCR register specifies the polarity of the frame sync for the receiver section. The ESAI receiver looks for a receive frame sync leading edge (trailing edge if RFSP is set) only when the previous frame is completed. If the frame sync goes high before the frame is completed (or before the last bit of the frame is received in the case of a bit frame sync or a word length frame sync with RFSR set), the current frame sync is not recognized, and the receiver is internally disabled until the next frame sync. Frames do not have to be adjacent - i.e., a new frame sync does not have to immediately follow the previous frame. Gaps of arbitrary periods can occur between frames. Enabled transmitters are tri-stated during these gaps. When operating in the synchronous mode (SYN=1), all clocks including the frame sync are generated by the transmitter section. 10.4.4.4 Shift Direction Selection Some data formats, such as those used by codecs, specify MSB first while other data formats, such as the AES-EBU digital audio interface, specify LSB first. The MSB/LSB first selection is made by programming RSHFD bit in the RCR register for the receiver section, and by programming the TSHFD bit in the TCR register for the transmitter section.
10.4.5
SERIAL I/O FLAGS
Three ESAI pins (FSR, SCKR and HCKR) are available as serial I/O flags when the ESAI is operating in the synchronous mode (SYN=1). Their operation is controlled by RCKD, RFSD, TEBE bits in the RCR, RCCR and SAICR registers.The output data bits (OF2, OF1 and OF0) and the input data bits (IF2, IF1 and IF0) are double buffered to/from the HCKR, FSR and SCKR pins. Double buffering the flags keeps them in sync with the TX and RX data lines. Each flag can be separately programmed. Flag 0 (SCKR pin) direction is selected by RCKD, RCKD=1 for output and RCKD=0 for input. Flag 1 (FSR pin) is enabled when the pin is not configured as external transmitter buffer enable (TEBE=0) and its direction is selected by RFSD, RFSD=1 for output and RFSD=0 for input. Flag 2 (HCKR pin) direction is selected by RHCKD, RHCKD=1 for output and RHCKD=0 for input.
10-52
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) GPIO - Pins and Registers
When programmed as input flags, the SCKR, FSR and HCKR logic values, respectively, are latched at the same time as the first bit of the receive data word is sampled. Because the input was latched, the signal on the input flag pin (SCKR, FSR or HCKR) can change without affecting the input flag until the first bit of the next receive data word. When the received data words are transferred to the receive data registers, the input flag latched values are then transferred to the IF0, IF1 and IF2 bits in the SAISR register, where they may be read by software. When programmed as output flags, the SCKR, FSR and HCKR logic values are driven by the contents of the OF0, OF1 and OF2 bits in the SAICR register respectively, and are driven when the transmit data registers are transferred to the transmit shift registers. The value on SCKR, FSR and HCKR is stable from the time the first bit of the transmit data word is transmitted until the first bit of the next transmit data word is transmitted. Software may change the OF0-OF2 values thus controlling the SCKR, FSR and HCKR pin values for each transmitted word. The normal sequence for setting output flags when transmitting data is as follows: wait for TDE (transmitter empty) to be set, first write the flags, and then write the transmit data to the transmit registers. OF0, OF1 and OF2 are double buffered so that the flag states appear on the pins when the transmit data is transferred to the transmit shift register (i.e., the flags are synchronous with the data).
10.5
GPIO - PINS AND REGISTERS
The GPIO functionality of the ESAI port is controlled by three registers: Port C control register (PCRC), Port C direction register (PRRC) and Port C data register (PDRC).
10.5.1
PORT C CONTROL REGISTER (PCRC)
The read/write 24-bit Port C Control Register (PCRC) in conjunction with the Port C Direction Register (PRRC) controls the functionality of the ESAI GPIO pins. Each of the PC(11:0) bits controls the functionality of the corresponding port pin. See Table 10-12 for the port pin configurations. Hardware and software reset clear all PCRC bits.
MOTOROLA
DSP56367
10-53
Enhanced Serial Audio Interface (ESAI) GPIO - Pins and Registers
10.5.2
PORT C DIRECTION REGISTER (PRRC)
The read/write 24-bit Port C Direction Register (PRRC) in conjunction with the Port C Control Register (PCRC) controls the functionality of the ESAI GPIO pins. Table 10-12 describes the port pin configurations. Hardware and software reset clear all PRRC bits. Table 10-12 PCRC and PRRC Bits Functionality
PDC[i] 0 0 1 1 PC[i] 0 1 0 1 Port Pin[i] Function disconnected GPIO input GPIO output ESAI
11 X:$FFFFBF PC11
10 PC10
9 PC9
8 PC8
7 PC7
6 PC6
5 PC5
4 PC4
3 PC3
2 PC2
1 PC1
0 PC0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 10-19 PCRC Register
11 X:$FFFFBE PDC11
10 PDC10
9 PDC9
8 PDC8
7 PDC7
6 PDC6
5 PDC5
4 PDC4
3 PDC3
2 PDC2
1 PDC1
0 PDC0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 10-20 PRRC Register
10-54
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) GPIO - Pins and Registers
10.5.3
PORT C DATA REGISTER (PDRC)
The read/write 24-bit Port C Data Register (see Figure 10-21) is used to read or write data to/from ESAI GPIO pins. Bits PD(11:0) are used to read or write data from/to the corresponding port pins if they are configured as GPIO. If a port pin [i] is configured as a GPIO input, then the corresponding PD[i] bit reflects the value present on this pin. If a port pin [i] is configured as a GPIO output, then the value written into the corresponding PD[i] bit is reflected on this pin. If a port pin [i] is configured as disconnected, the corresponding PD[i] bit is not reset and contains undefined data.
11 X:$FFFFBD PD11 10 PD10 9 PD9 8 PD8 7 PD7 6 PD6 5 PD5 4 PD4 3 PD3 2 PD2 1 PD1 0 PD0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 10-21 PDRC Register
MOTOROLA
DSP56367
10-55
Enhanced Serial Audio Interface (ESAI) ESAI Initialization Examples
10.6
ESAI INITIALIZATION EXAMPLES
10.6.1
*
INITIALIZING THE ESAI USING INDIVIDUAL RESET
The ESAI should be in its individual reset state (PCRC = $000 and PRRC = $000). In the individual reset state, both the transmitter and receiver sections of the ESAI are simultaneously reset. The TPR bit in the TCR register may be used to reset just the transmitter section. The RPR bit in the RCR register may be used to reset just the receiver section. Configure the control registers (TCCR, TCR, RCCR, RCR) according to the operating mode, but do not enable transmitters (TE5-TE0 = $0) or receivers (RE3-RE0 = $0). It is possible to set the interrupt enable bits which are in use during the operation (no interrupt occurs). Enable the ESAI by setting the PCRC register and PRRC register bits according to pins which are in use during operation. Write the first data to be transmitted to the transmitters which are in use during operation. This step is needed even if DMA is used to service the transmitters. Enable the transmitters and receivers. From now on ESAI can be serviced either by polling, interrupts, or DMA.
*
* *
* *
Operation proceeds as follows: * * * For internally generated clock and frame sync, these signals are active immediately after ESAI is enabled (step 3 above). Data is received only when one of the receive enable (REx) bits is set and after the occurrence of frame sync signal (either internally or externally generated). Data is transmitted only when the transmitter enable (TEx) bit is set and after the occurrence of frame sync signal (either internally or externally generated). The transmitter outputs remain tri-stated after TEx bit is set until the frame sync occurs.
10.6.2
* *
INITIALIZING JUST THE ESAI TRANSMITTER SECTION
It is assumed that the ESAI is operational; that is, at least one pin is defined as an ESAI pin. The transmitter section should be in its personal reset state (TPR = 1).
10-56
DSP56367
MOTOROLA
Enhanced Serial Audio Interface (ESAI) ESAI Initialization Examples
* * * * *
Configure the control registers TCCR and TCR according to the operating mode, making sure to clear the transmitter enable bits (TE0 - TE5). TPR must remain set. Take the transmitter section out of the personal reset state by clearing TPR. Write first data to the transmitters which will be used during operation. This step is needed even if DMA is used to service the transmitters. Enable the transmitters by setting their TE bits. Data is transmitted only when the transmitter enable (TEx) bit is set and after the occurrence of frame sync signal (either internally or externally generated). The transmitter outputs remain tri-stated after TEx bit is set until the frame sync occurs. From now on the transmitters are operating and can be serviced either by polling, interrupts, or DMA.
*
10.6.3
* * * * * *
INITIALIZING JUST THE ESAI RECEIVER SECTION
It is assumed that the ESAI is operational; that is, at least one pin is defined as an ESAI pin. The receiver section should be in its personal reset state (RPR = 1). Configure the control registers RCCR and RCR according to the operating mode, making sure to clear the receiver enable bits (RE0 - RE3). RPR must remain set. Take the receiver section out of the personal reset state by clearing RPR. Enable the receivers by setting their RE bits. From now on the receivers are operating and can be serviced either by polling, interrupts, or DMA.
MOTOROLA
DSP56367
10-57
Enhanced Serial Audio Interface (ESAI) ESAI Initialization Examples
10-58
DSP56367
MOTOROLA
SECTION
11
ENHANCED SERIAL AUDIO INTERFACE 1 (ESAI_1)
11.1 INTRODUCTION
The Enhanced Serial Audio Interface I (ESAI_1) is the second ESAI peripheral in the DSP56367. It is functionally identical to the ESAI peripheral described in Section 10 except for minor differences described in this section. Refer to the ESAI section for functional information about the ESAI_1, in addition to using the information in this section. The ESAI_1 block diagram is shown in Figure 11-1. The ESAI_1 shares 4 pins with the ESAI. The ESAI_1 does not have the two high frequency clock pins but otherwise it is identical to the ESAI.
MOTOROLA
DSP56367
11-1
Enhanced Serial Audio Interface 1 (ESAI_1) Introduction
GDB RSMA_1 RSMB_1 TSMA_1 TSMB_1
DDB TX0_1 Shift Register TX1_1 Shift Register SDO0_1 [PE11] (shared with SDO0 [PC11])
SDO1_1 [PE10] (shared with SDO1 [PC10])
RCCR_1 RCR_1
TX2_1 Shift Register
SDO2_1/SDI3_1 [PE9] (shared with SDO2/SDI3 [PC9])
TCCR_1 TCR_1
RX3_1 TX3_1
SDO3_1/SDI2_1 [PE8] (shared with SDO3/SDI2 [PC8])
SAICR_1 SAISR_1
Shift Register RX2_1 TX4_1
TSR_1 Shift Register RX1_1 TX5_1 RCLK Shift Register TCLK [PE0] SCKR_1 [PE3] SCKT_1 [PE1] FSR_1 [PE4] FST_1 RX0_1
SDO4_1/SDI1_1 [PE7]
Clock / Frame Sync Generators and Control Logic
SDO5_1/SDI0_1 [PE6]
Figure 11-1 ESAI_1 Block Diagram
11-2
DSP56367
MOTOROLA
Enhanced Serial Audio Interface 1 (ESAI_1) ESAI_1 Data and Control Pins
11.2
ESAI_1 DATA AND CONTROL PINS
The ESAI_1 has 6 dedicated pins and shares 4 pins with the ESAI. The pins are described in the following sections.
11.2.1
SERIAL TRANSMIT 0 DATA PIN (SDO0_1)
SDO0_1 transmits data from the TX0_1 serial transmit shift register. It is shared with the ESAI SDO0 signal. The pin may be used as SDO0_1 if it is not defined as ESAI SDO0. The pin may be used as GPIO PE11 if not used by the ESAI or ESAI_1. The ESAI_1 Multiplex Control Register (EMUXR) defines if the pin belongs to the ESAI or to the ESAI_1.
11.2.2
SERIAL TRANSMIT 1 DATA PIN (SDO1_1)
SDO1_1 transmits data from the TX1_1 serial transmit shift register. It is shared with the ESAI SDO1 signal. The pin may be used as SDO1_1 if it is not defined as ESAI SDO1. The pin may be used as GPIO PE10 if not used by the ESAI or ESAI_1. The ESAI_1 Multiplex Control Register (EMUXR) defines if the pin belongs to the ESAI or to the ESAI_1.
11.2.3
SERIAL TRANSMIT 2/RECEIVE 3 DATA PIN (SDO2_1/SDI3_1)
SDO2_1/SDI3_1 transmits data from the TX2_1 serial transmit shift register when programmed as a transmitter pin, or receives serial data to the RX3_1 serial receive shift register when programmed as a receiver pin. It is shared with the ESAI SDO2/SDI3 signal. The pin may be used as SDO2_1/SDI3_1 if it is not defined as ESA I SDO2/SDI3. The pin may be used as GPIO PE9 if not used by the ESAI or ESAI_1. The ESAI_1 Multiplex Control Register (EMUXR) defines if the pin belongs to the ESAI or to the ESAI_1.
11.2.4
SERIAL TRANSMIT 3/RECEIVE 2 DATA PIN (SDO3_1/SDI2_1)
SDO3_1/SDI2_1 transmits data from the TX3_1 serial transmit shift register when programmed as a transmitter pin, or receives serial data to the RX2_1 serial receive shift register when programmed as a receiver pin. It is shared with the ESAI SDO3/SDI2 signal.
MOTOROLA
DSP56367
11-3
Enhanced Serial Audio Interface 1 (ESAI_1) ESAI_1 Data and Control Pins
The pin may be used as SDO3_1/SDI2_1 if it is not defined as ESAI SDO3/SDI2. The pin may be used as GPIO PE8 if not used by the ESAI or ESAI_1. The ESAI_1 Multiplex Control Register (EMUXR) defines if the pin belongs to the ESAI or to the ESAI_1.
11.2.5
SERIAL TRANSMIT 4/RECEIVE 1 DATA PIN (SDO4_1/SDI1_1)
SDO4_1/SDI1_1 transmits data from the TX4_1 serial transmit shift register when programmed as a transmitter pin, or receives serial data to the RX1_1 serial receive shift register when programmed as a receiver pin. SDO4_1/SDI1_1 may be programmed as a general-purpose pin (PE7) when the ESAI_1 SDO4_1 and SDI1_1 functions are not being used.
11.2.6
SERIAL TRANSMIT 5/RECEIVE 0 DATA PIN (SDO5_1/SDI0_1)
SDO5_1/SDI0_1 transmits data from the TX5_1 serial transmit shift register when programmed as transmitter pin, or receives serial data to the RX0_1 serial shift register when programmed as a receiver pin. SDO5_1/SDI0_1 may be programmed as a general-purpose pin (PE6) when the ESAI_1 SDO5_1 and SDI0_1 functions are not being used.
11.2.7
RECEIVER SERIAL CLOCK (SCKR_1)
SCKR_1 is a bidirectional pin that provides the receivers serial bit clock for the ESAI_1 interface. SCKR_1 may be programmed as a general-purpose I/O pin (PE0) when the ESAI_1 SCKR_1 function is not being used.
11.2.8
TRANSMITTER SERIAL CLOCK (SCKT_1)
SCKT_1 is a bidirectional pin that provides the transmitters serial bit clock for the ESAI_1 interface. SCKT_1 may be programmed as a general-purpose I/O pin (PE3) when the ESAI_1 SCKT_1 function is not being used.
11-4
DSP56367
MOTOROLA
Enhanced Serial Audio Interface 1 (ESAI_1) ESAI_1 Programming Model
11.2.9
FRAME SYNC FOR RECEIVER (FSR_1)
The FSR_1 pin is a bidirectional pin that provides the receivers frame sync signal for the ESAI_1 interface. FSR_1 may be programmed as a general-purpose I/O pin (PE1) when the ESAI_1 FSR_1 function is not being used.
11.2.10
FRAME SYNC FOR TRANSMITTER (FST_1)
The FST_1 pin is a bidirectional pin that provides the transmitters frame sync signal for the ESAI_1 interface. FST_1 may be programmed as a general-purpose I/O pin (PE4) when the ESAI_1 FST_1 function is not being used.
11.3
ESAI_1 PROGRAMMING MODEL
The ESAI_1 has the following registers: * * * * * * * * One multiplex control register Five control registers One status register Six transmit data registers Four receive data registers Two transmit slot mask registers Two receive slot mask registers One special-purpose time slot register
The ESAI_1 also contains the GPIO Port E functionality, described in Section 11.5, "GPIO Pins and Registers". The following paragraphs give detailed descriptions of bits in the ESAI_1 registers that differ in functionality from their descriptions in the ESAI Programming Model.
MOTOROLA
DSP56367
11-5
Enhanced Serial Audio Interface 1 (ESAI_1) ESAI_1 Programming Model
11.3.1
ESAI_1 MULTIPLEX CONTROL REGISTER (EMUXR)
The read/write ESAI_1 Multiplex Control Register (EMUXR) controls which peripheral (ESAI or ESAI_1) is using the shared pins.
11 Y:$FFFFAF 10 9 8 7 6 5 4 3 2 1 0
EMUX3 EMUX2 EMUX1 EMUX0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 11-2 EMUXR Register Hardware and software reset clear all the bits of the EMUXR register. The selection of ESAI/ESAI_1 pins is shown in Table 11-1. Table 11-1 EMUXR ESAI/ESAI_1 Pin Selection
EMUXR bit EMUX0 EMUX0 EMUX1 EMUX1 EMUX2 EMUX2 EMUX3 EMUX3 0 1 0 1 0 1 0 1 ESAI pin SDO0 [PC11] disconnected SDO1[PC10] disconnected SDO2/SDI3 [PC9] disconnected SDO3/SDI2 [PC8] disconnected ESAI_1 pin disconnected SDO0_1 [PE11] disconnected SDO1_1 [PE10] disconnected SDO2_1/SDI3_1 [PE9] disconnected SDO3_1/SDI2_1 [PE8]
11.3.2
ESAI_1 TRANSMITTER CLOCK CONTROL REGISTER (TCCR_1)
The read/write Transmitter Clock Control Register (TCCR_1) controls the ESAI_1 transmitter clock generator bit and frame sync rates, the bit rate and high frequency clock sources and the directions of the FST_1 and SCKT_1 signals. In synchronous mode, the bit clock defined for the transmitter determines the receiver bit clock as well. TCCR_1 also controls the number of words per frame for the serial data.
11-6
DSP56367
MOTOROLA
Enhanced Serial Audio Interface 1 (ESAI_1) ESAI_1 Programming Model
Hardware and software reset clear all the bits of the TCCR_1 register.
11 Y:$FFFF96 TDC2 10 TDC1 9 TDC0 8 TPSR 7 TPM7 6 TPM6 5 TPM5 4 TPM4 3 TPM3 2 TPM2 1 TPM1 0 TPM0
23 THCKD
22 TFSD
21 TCKD
20 THCKP
19 TFSP
18 TCKP
17 TFP3
16 TFP2
15 TFP1
14 TFP0
13 TDC4
12 TDC3
Figure 11-3 TCCR_1 Register 11.3.2.1 TCCR_1 Tx High Freq. Clock Divider (TFP3-TFP0) - Bits 14-17 Since the ESAI_1 does not have the transmitter high frequency clock pin, the TFP3-TFP0 bits simply specify an additional division ratio in the clock divider chain. See Figure 11-4. 11.3.2.2 TCCR_1 Tx High Freq. Clock Polarity (THCKP) - Bit 20 The ESAI_1 does not have the transmitter high frequency clock pin. It it recommended that THCKP should be kept cleared. 11.3.2.3 TCCR_1 Tx High Freq. Clock Direction (THCKD) - Bit 23 The ESAI_1 does not have the transmitter high frequency clock pin. THCKD must be set for proper ESAI_1 transmitter section operation. Table 11-2 Transmitter Clock Sources
THCKD 0 1 1 1 1 TFSD X 0 0 1 1 TCKD X 0 1 0 1 SCKT_1 INT SCKT_1 INT FST_1 FST_1 SCKT_1 SCKT_1 Transmitter Bit Clock Source Reserved OUTPUTS
MOTOROLA
DSP56367
11-7
Enhanced Serial Audio Interface 1 (ESAI_1) ESAI_1 Programming Model
RHCKD=1 FOSC DIVIDE BY 2
PRESCALE DIVIDE BY 1 OR DIVIDE BY 8 DIVIDER DIVIDE BY 1 TO DIVIDE BY 256 DIVIDER DIVIDE BY 1 TO DIVIDE BY 16
RPSR
RPM0 - RPM7
RFP0 - RFP3
FLAG0 OUT (SYNC MODE)
FLAG0 IN (SYNC MODE)
INTERNAL BIT CLOCK RSWS4-RSWS0
RX WORD LENGTH DIVIDER SYN=1 SCKR_1 RCLOCK SYN=0 RCKD SYN=1 TSWS4-TSWS0 SYN=0 RX SHIFT REGISTER
RX WORD CLOCK
INTERNAL BIT CLOCK SCKT_1
TCLOCK
TX WORD LENGTH DIVIDER
TX WORD CLOCK
TCKD TX SHIFT REGISTER
TPSR
TPM0 - TPM7
TFP0 - TFP3
FOSC THCKD=1
DIVIDE BY 2
PRESCALE DIVIDE BY 1 OR DIVIDE BY 8
DIVIDER DIVIDE BY 1 TO DIVIDE BY 256
DIVIDER DIVIDE BY 1 TO DIVIDE BY 16
Notes: 1. FOSC is the DSP56300 Core internal clock frequency.
Figure 11-4 ESAI_1 Clock Generator Functional Block Diagram
11-8
DSP56367
MOTOROLA
Enhanced Serial Audio Interface 1 (ESAI_1) ESAI_1 Programming Model
RDC0 - RDC4 RX WORD CLOCK
RFSL
RECEIVER FRAME RATE DIVIDER
SYNC TYPE
INTERNAL RX FRAME CLOCK RFSD RFSD=1 SYN=0 SYN=0 FSR_1
RECEIVE CONTROL LOGIC
RECEIVE FRAME SYNC SYN=1 RFSD=0 SYN=1
TDC0 - TDC4 TX WORD CLOCK TRANSMITTER FRAME RATE DIVIDER
TFSL
FLAG1 IN (SYNC MODE)
FLAG1OUT (SYNC MODE) TFSD
SYNC TYPE
INTERNAL TX FRAME CLOCK FST_1
TRANSMIT CONTROL LOGIC
TRANSMIT FRAME SYNC
Figure 11-5 ESAI_1 Frame Sync Generator Functional Block Diagram
MOTOROLA
DSP56367
11-9
Enhanced Serial Audio Interface 1 (ESAI_1) ESAI_1 Programming Model
11.3.3
ESAI_1 TRANSMIT CONTROL REGISTER (TCR_1)
The read/write Transmit Control Register (TCR_1) controls the ESAI_1 transmitter section. Interrupt enable bits for the transmitter section are provided in this control register. Operating modes are also selected in this register.
11 Y:$FFFF95 10 9 8 7 6 TSHFD 5 TE5 4 TE4 3 TE3 2 TE2 1 TE1 0 TE0
TSWS1 TSWS0 TMOD1 TMOD0 TWA
23 TLIE
22 TIE
21 TEDIE
20 TEIE
19 TPR
18
17 PADC
16 TFSR
15 TFSL
14
13
12
TSWS4 TSWS3 TSWS2
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 11-6 TCR_1 Register Hardware and software reset clear all the bits in the TCR_1 register.
11.3.4
ESAI_1 RECEIVE CLOCK CONTROL REGISTER (RCCR_1)
The read/write Receive Clock Control Register (RCCR_1) controls the ESAI_1 receiver clock generator bit and frame sync rates, word length, and number of words per frame for the serial data.
11 Y:$FFFF98 RDC2 10 RDC1 9 RDC0 8 RPSR 7 RPM7 6 RPM6 5 RPM5 4 RPM4 3 RPM3 2 RPM2 1 RPM1 0 RPM0
23
22
21
20
19 RFSP
18 RCKP
17 RFP3
16 RFP2
15 RFP1
14 RFP0
13 RDC4
12 RDC3
RHCKD RFSD
RCKD RHCKP
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 11-7 RCCR_1 Register Hardware and software reset clear all the bits of the RCCR_1 register.
11-10
DSP56367
MOTOROLA
Enhanced Serial Audio Interface 1 (ESAI_1) ESAI_1 Programming Model
11.3.4.1 RCCR_1 Rx High Freq. Clock Divider (RFP3-RFP0) - Bits 14-17 Since the ESAI_1 does not have the receiver high frequency clock pin, the RFP3-RFP0 bits simply specify an additional division ratio in the clock divider chain. See Figure 11-4. 11.3.4.2 RCCR_1 Rx High Freq. Clock Polarity (RHCKP) - Bit 20 The ESAI_1 does not have the receiver high frequency clock pin. It it recommended that RHCKP should be kept cleared. 11.3.4.3 RCCR_1 Rx High Freq. Clock Direction (RHCKD) - Bit 23 The ESAI_1 does not have the receiver high frequency clock pin. RHCKD must be set for proper ESAI_1 receiver section operation. Table 11-3 Receiver Clock Sources (asynchronous mode only)
RHCKD 0 1 1 1 1 RFSD X 0 0 1 1 RCKD X 0 1 0 1 SCKR_1 INT SCKR_1 INT FSR_1 FSR_1 SCKR_1 SCKR_1 Receiver Bit Clock Source Reserved OUTPUTS
11.3.5
ESAI_1 RECEIVE CONTROL REGISTER (RCR_1)
The read/write Receive Control Register (RCR_1) controls the ESAI_1 receiver section.
11 Y:$FFFF97 10 9 8 7 6 RSHFD 5 4 3 RE3 2 RE2 1 RE1 0 RE0
RSWS1 RSWS0 RMOD1 RMOD0 RWA
23 RLIE
22 RIE
21 REDIE
20 REIE
19 RPR
18
17
16 RFSR
15 RFSL
14
13
12
RSWS4 RSWS3 RSWS2
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 11-8 RCR_1 Register Hardware and software reset clear all the bits in the RCR_1 register.
MOTOROLA
DSP56367
11-11
Enhanced Serial Audio Interface 1 (ESAI_1) ESAI_1 Programming Model
11.3.6
ESAI_1 COMMON CONTROL REGISTER (SAICR_1)
The read/write Common Control Register (SAICR_1) contains control bits for functions that use both the receive and transmit sections of the ESAI_1.
11 Y:$FFFF94 10 9 8 ALC 7 TEBE 6 SYN 5 4 3 2 OF2 1 OF1 0 OF0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 11-9 SAICR_1 Register Hardware and software reset clear all the bits in the SAICR_1 register.
11.3.7
ESAI_1 STATUS REGISTER (SAISR_1)
The Status Register (SAISR_1) is a read-only status register used by the DSP to read the status and serial input flags of the ESAI_1.
11 Y:$FFFF93 10 9 8 RDF 7 ROE 6 RFS 5 4 3 2 IF2 1 IF1 0 IF0
RODF REDF
23
22
21
20
19
18
17
16
15 TDE
14 TUE
13 TFS
12
TODE TEDE
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 11-10 SAISR_1 Register
11-12
DSP56367
MOTOROLA
Enhanced Serial Audio Interface 1 (ESAI_1) ESAI_1 Programming Model
11.3.8
ESAI_1 RECEIVE SHIFT REGISTERS
The receive shift registers receive the incoming data from the serial receive data pins. Data is shifted in by the selected (internal/external) bit clock when the associated frame sync I/O is asserted. Data is assumed to be received MSB first if RSHFD=0 and LSB first if RSHFD=1. Data is transferred to the ESAI_1 receive data registers after 8, 12, 16, 20, 24, or 32 serial clock cycles were counted, depending on the slot length control bits in the RCR_1 register.
11.3.9
ESAI_1 RECEIVE DATA REGISTERS
The Receive Data Registers RX3_1, RX2_1, RX1_1, and RX0_1 are 24-bit read-only registers that accept data from the receive shift registers when they become full. The data occupies the most significant portion of the receive data registers, according to the ALC control bit setting. The unused bits (least significant portion, and 8 most significant bits when ALC=1) read as zeros. The DSP is interrupted whenever RXx_1 becomes full if the associated interrupt is enabled.
11.3.10
ESAI_1 TRANSMIT SHIFT REGISTERS
The Transmit Shift Registers contain the data being transmitted. Data is shifted out to the serial transmit data pins by the selected (internal/external) bit clock when the associated frame sync I/O is asserted. The number of bits shifted out before the shift registers are considered empty and may be written to again can be 8, 12, 16, 20, 24 or 32 bits (determined by the slot length control bits in the TCR_1 register). Data is shifted out of these registers MSB first if TSHFD=0 and LSB first if TSHFD=1.
11.3.11
ESAI_1 TRANSMIT DATA REGISTERS
The Transmit Data registers TX5_1, TX4_1, TX3_1, TX2_1, TX1_1, and TX0_1 are 24-bit write-only registers. Data to be transmitted is written into these registers and is automatically transferred to the transmit shift registers. The data written (8, 12, 16, 20 or 24 bits) should occupy the most significant portion of the TXx_1 according to the ALC control bit setting. The unused bits (least significant portion, and the 8 most significant bits when ALC=1) of the TXx_1 are don't care bits. The DSP is interrupted whenever the TXx_1 becomes empty if the transmit data register empty interrupt has been enabled.
MOTOROLA
DSP56367
11-13
Enhanced Serial Audio Interface 1 (ESAI_1) ESAI_1 Programming Model
11.3.12
ESAI_1 TIME SLOT REGISTER (TSR_1)
The write-only Time Slot Register (TSR_1) is effectively a null data register that is used when the data is not to be transmitted in the available transmit time slot. The transmit data pins of all the enabled transmitters are in the high-impedance state for the respective time slot where TSR_1 has been written. The Transmitter External Buffer Enable pin (FSR_1 pin when SYN=1, TEBE=1, RFSD=1) disables the external buffers during the slot when the TSR_1 register has been written.
11.3.13
TRANSMIT SLOT MASK REGISTERS (TSMA_1, TSMB_1)
The Transmit Slot Mask Registers (TSMA_1 and TSMB_1) are two read/write registers used by the transmitters in network mode to determine for each slot whether to transmit a data word and generate a transmitter empty condition (TDE=1), or to tri-state the transmitter data pins. TSMA_1 and TSMB_1 should each be considered as containing half a 32-bit register TSM_1. See Figure 11-11 and Figure 11-12. Bit number N in TSM_1 (TS**) is the enable/disable control bit for transmission in slot number N.
11 Y:$FFFF99 TS11 10 TS10 9 TS9 8 TS8 7 TS7 6 TS6 5 TS5 4 TS4 3 TS3 2 TS2 1 TS1 0 TS0
23
22
21
20
19
18
17
16
15 TS15
14 TS14
13 TS13
12 TS12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 11-11 TSMA_1 Register
11 Y:$FFFF9A TS27 10 TS26 9 TS25 8 TS24 7 TS23 6 TS22 5 TS21 4 TS20 3 TS19 2 TS18 1 TS17 0 TS16
23
22
21
20
19
18
17
16
15 TS31
14 TS30
13 TS29
12 TS28
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 11-12 TSMB_1 Register
11-14
DSP56367
MOTOROLA
Enhanced Serial Audio Interface 1 (ESAI_1) ESAI_1 Programming Model
11.3.14
RECEIVE SLOT MASK REGISTERS (RSMA_1, RSMB_1)
The Receive Slot Mask Registers (RSMA_1 and RSMB_1) are two read/write registers used by the receiver in network mode to determine for each slot whether to receive a data word and generate a receiver full condition (RDF=1), or to ignore the received data. RSMA_1 and RSMB_1 should be considered as each containing half of a 32-bit register RSM_1. See Table 11-13 and Table 11-14. Bit number N in RSM_1 (RS**) is an enable/disable control bit for receiving data in slot number N.
11 Y:$FFFF9B RS11 10 RS10 9 RS9 8 RS8 7 RS7 6 RS6 5 RS5 4 RS4 3 RS3 2 RS2 1 RS1 0 RS0
23
22
21
20
19
18
17
16
15 RS15
14 RS14
13 RS13
12 RS12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 11-13 RSMA_1 Register
11 Y:$FFFF9C RS27
10 RS26
9 RS25
8 RS24
7 RS23
6 RS22
5 RS21
4 RS20
3 RS19
2 RS18
1 RS17
0 RS16
23
22
21
20
19
18
17
16
15 RS31
14 RS30
13 RS29
12 RS28
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 11-14 RSMB_1 Register
MOTOROLA
DSP56367
11-15
Enhanced Serial Audio Interface 1 (ESAI_1) Operating Modes
11.4
OPERATING MODES
11.4.1
ESAI_1 AFTER RESET
Hardware or software reset clears the EMUXR register, the port E control register bits and the port E direction control register bits, which configure all 6 ESAI_1 dedicated I/O pins as disconnected, and all 4 shared pins as belonging to the ESAI. The ESAI_1 is in the individual reset state while all ESAI_1 signals are programmed as general-purpose I/O or disconnected, and is active only if at least one of the ESAI_1 I/O pins is programmed as belonging to the ESAI_1.
11.5
GPIO - PINS AND REGISTERS
The GPIO functionality of the ESAI_1 port is controlled by three registers: Port E Control register (PCRE), Port E Direction register (PRRE) and Port E Data register (PDRE).
11.5.1
PORT E CONTROL REGISTER (PCRE)
The read/write 24-bit Port E Control Register (PCRE) in conjunction with the Port E Direction Register (PRRE) controls the functionality of the ESAI_1 GPIO pins. Each of the PE(11:0) bits controls the functionality of the corresponding port pin. See Table 11-4 for the port pin configurations. Hardware and software reset clear all PCRE bits.
11-16
DSP56367
MOTOROLA
Enhanced Serial Audio Interface 1 (ESAI_1) GPIO - Pins and Registers
11.5.2
PORT E DIRECTION REGISTER (PRRE)
The read/write 24-bit Port E Direction Register (PRRE) in conjunction with the Port E Control Register (PCRE) controls the functionality of the ESAI_1 GPIO pins. Table 11-4 describes the port pin configurations. Hardware and software reset clear all PRRE bits. Table 11-4 PCRE and PRRE Bits Functionality
PDE[i] 0 0 1 1 PE[i] 0 1 0 1 Port Pin[i] Function disconnected GPIO input GPIO output ESAI_1
11 Y:$FFFF9F PE11
10 PE10
9 PE9
8 PE8
7 PE7
6 PE6
5
4 PE4
3 PE3
2
1 PE1
0 PE0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 11-15 PCRE Register
11 Y:$FFFF9E
10
9 PDE9
8 PDE8
7 PDE7
6 PDE6
5
4 PDE4
3 PDE3
2
1 PDE1
0 PDE0
PDE11 PDE10
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 11-16 PRRE Register
MOTOROLA
DSP56367
11-17
Enhanced Serial Audio Interface 1 (ESAI_1) GPIO - Pins and Registers
11.5.3
PORT E DATA REGISTER (PDRE)
The read/write 24-bit Port E Data Register (see Figure 11-17) is used to read or write data to/from ESAI_1 GPIO pins. Bits PD(11:0) are used to read or write data from/to the corresponding port pins if they are configured as GPIO. If a port pin [i] is configured as a GPIO input, then the corresponding PD[i] bit will reflect the value present on this pin. If a port pin [i] is configured as a GPIO output, then the value written into the corresponding PD[i] bit will be reflected on this pin. If a port pin [i] is configured as disconnected, the corresponding PD[i] bit is not reset and contains undefined data.
11 Y:$FFFF9D PD11 10 PD10 9 PD9 8 PD8 7 PD7 6 PD6 5 4 PD4 3 PD3 2 1 PD1 0 PD0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 11-17 PDRE Register
11-18
DSP56367
MOTOROLA
SECTION
12
DIGITAL AUDIO TRANSMITTER
12.1 INTRODUCTION
The Digital Audio Transmitter (DAX) is a serial audio interface module that outputs digital audio data in the AES/EBU, CP-340 and IEC958 formats. Some of the key features of the DAX are listed below. * * Operates on a frame basis--The DAX can handle one frame (consisting of two subframes) of audio and non-audio data at a time. Double-buffered audio and non-audio data--The DAX data path is double-buffered so the next frame data can be stored in the DAX without affecting the frame currently being transmitted. Direct Memory Access--Audio data and non-audio data can be written to the DAX using DMA. Programmable clock source--Users can select the DAX clock source, and this selection configures the DAX to operate in slave or master mode. Supports both master mode and slave mode in a digital audio network--If the user selects a divided DSP core clock, the DAX will operate in the master mode. If the user selects an external clock source, the DAX will operate in the slave mode. GPIO--Each of the two DAX pins can be configured as either GPIO or as specific DAX pin. Each pin is independent of the other. However, at least one of the two pins must be selected as a DAX pin to release the DAX from reset.
* * *
*
The accessible DAX registers are all mapped in the X I/O memory space. This allows programmers to access the DAX using standard instructions and addressing modes. Interrupts generated by the DAX can be handled with a fast interrupt for cases in which the non-audio data does not change from frame to frame. When the DAX interrupts are disabled, they can still be served by DMA or by a "polling" technique. A block diagram of the DAX is shown in Figure 12-1.
MOTOROLA
DSP56367
12-1
Note:
23
The shaded registers in Figure 12-1 are directly accessible by DSP instructions.
Global Data Bus
0 23 0 23 0
DMA Bus
23
0
XSTR
XNADR
XADR
XCTR
XADBUFA
26 23
XADBUFB
0
XNADBUF
MUX
PRTYG
Preamble Generator
MUX
Upload
MUX
C-U-V
XADSR
Biphase Encoder
ADO
ACI DAX State Machine Control Signals DAX Clocks DAX Clock MUX
DSP Core Clock
Figure 12-1 Digital Audio Transmitter (DAX) Block Diagram
12.2
DAX SIGNALS
The DAX has two signal lines: * DAX Digital Audio Output (ADO/PD1)--The ADO pin sends audio and non-audio data in the AES/EBU, CP340, and IEC958 formats in a biphase mark format. The ADO pin may also be used as a GPIO pin PD1 if the DAX is not operational. DAX Clock Input (ACI/PD0)--When the DAX clock is configured to be supplied externally, the external clock is applied to the ACI pin. The frequency of the external clock must be 256 times, 384 times, or 512 times the audio sampling frequency (256 x Fs, 384 x Fs, or 512 x Fs). The ACI pin may also be used as a GPIO pin PD0 when the DAX is disabled or when operating from the internal DSP clock.
*
MOTOROLA
DSP56367
12-2
12.3
DAX FUNCTIONAL OVERVIEW
The DAX consists of the following: * * * * * * * * * * * * Audio data register (XADR) Two audio data buffers (XADBUFA and XADBUFB) Non-audio data register (XNADR) Non-audio data buffer (XNADBUF) Audio and non-audio data shift register (XADSR) Control register (XCTR) Status register (XSTR) Parity generator (PRTYG) Preamble generator Biphase encoder Clock multiplexer Control state machine
XADR, XADBUFA, XADBUFB and XADSR creates a FIFO-like data path. Channel A is written to XADR and moves to XADBUFA. Then channel B is written to XADR, and when XADBUFB empties XADR moves into it. XADBUFA moves to the shift register XADSR when XADSR has shifted out its last bit. After channel A audio and non-audio data has been shifted out, XADBUFB moves into XADSR, and channel B audio and non audio shift begins. The frame non-audio data (stored in XNADR) is transferred to the XADSR (for channel A) and to the XNADBUF registers (for channel B) at the beginning of a frame transmission. This is called an "upload." The DAX audio data register empty (XADE) flag is set when XADR and XADBUFA are empty, and, if the audio data register empty interrupt is enabled (XDIE=1), an interrupt request is sent to the DSP core. The interrupt handling routine then sends the non-audio data bits to XNADR and the next frame of audio data to XADR (two subframes). At the beginning of a frame transmission, one of the 8-bit channel A preambles (Z-preamble for the first subframe in a block, or X-preamble otherwise) is generated in the preamble generator, and then shifted out to the ADO pin in the first eight time slots. The preamble is generated in biphase mark format. The twenty-four audio and three non-audio data bits in the XADSR are shifted out to the biphase encoder, which shifts them out through the ADO pin in the biphase mark format in the next 54 time slots. The parity generator calculates an even parity over the 27 bits of audio and non-audio data, and then outputs the result through the
MOTOROLA
DSP56367
12-3
Digital Audio Transmitter DAX Programming Model
biphase encoder to the ADO pin at the last two time slots. This is the end of the first (channel A) subframe transmission. The second subframe transmission (channel B) starts with the preamble generator generating the channel B preamble (Y-preamble). At the same time, channel B audio and non-audio data is transferred to the XADSR shift-register from the XADBUFB and XNADBUF registers. The generated Y-preamble is output immediately after the channel A parity and is followed by the audio and non-audio data in the XADSR, which is in turn followed by the calculated parity for channel B. This completes a frame transmission. When the channel B parity is sent, the audio data for the next frame, stored in XADBUFA and the non-audio data bits from the XNADR, are uploaded to XADSR.
12.4
DAX PROGRAMMING MODEL
The programmer-accessible DAX registers are shown in Figure 12-2. The registers are described in the following subsections. The Interrupt Vector table for the DAX is shown in Table 12-1. The internal interrupt priority is shown in Table 12-2. Table 12-1 DAX Interrupt Vectors
Condition XAUR XADE & XBLK XADE Address VBA:$28 VBA:$2A VBA:$2E Description DAX transmit underrun error DAX block transferred DAX audio data register empty
Table 12-2 DAX Interrupt Priority
Priority highest DAX transmit underrun error DAX block transferred lowest DAX audio data register empty Interrupt
12-4
DSP56367
MOTOROLA
Digital Audio Transmitter DAX Internal Architecture
12.5
DAX INTERNAL ARCHITECTURE
Hardware components shown in Figure 12-1 are described in the following sections. The DAX programming model is illustrated in Figure 12-2.
XCTR - Control Register - X:$FFFFD0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XSB XCS1 XCS0 XBIE XUIE XDIE
XNADR - Non-Audio Data Register - X:$FFFFD1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XCB XUB XVB XCA XUA XVA
XADRA - Audio Data Register A - X:$FFFFD2 and XADRB - Audio Data Register B -X:$FFFFD3 23 0
XSTR - Status Register - X:$FFFFD4 23 22 21 20 19 18 17 16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
XBLK XAURXADE
Reserved bit
Figure 12-2 DAX Programming Model
12.5.1
DAX AUDIO DATA REGISTER (XADR)
XADR is a 24-bit write-only register. One frame of audio data, which is to be transmitted in the next frame slot, is transferred to this register. Successive write accesses to this register will store channel A and channel B alternately in XADBUFA and in XADBUFB respectively. When XADR and XADBUFA are empty, XADE bit in the XSTR is set, and, if the audio data register empty interrupt is enabled (XDIE=1), an interrupt request is sent to the DSP core. When channel B is transferred to XADR, the XADE bit in the XSTR is cleared. XADR can also be accessed by DMA. When XADR and XADBUFA are empty, the DAX sends a DMA request to the core. The DMA first transfers non-audio data bits to XNADR (optional), then transfers channel A and channel B to XADR. The XADR can be accessed with two different successive addresses. This feature supports sending non-audio data bits, channel A and channel B to the DAX in three successive DMA transfers.
MOTOROLA
DSP56367
12-5
Digital Audio Transmitter DAX Internal Architecture
12.5.2
DAX AUDIO DATA BUFFERS (XADBUFA / XADBUFB)
XADBUFA and XADBUFB are 24-bit registers that buffer XADR from XADSR, creating a FIFO-like data path. These registers hold the next two subframes of audio data to be transmitted. Channel A audio data is transferred from XADR to XADBUFA if XADBUFA is empty. Channel B audio data is transferred from XADR to XADBUFB if XADBUFB is empty. Audio data is transferred from XADBUFA and XADBUFB alternately to XADSR provided that XADSR shifted out all the audio and non-audio bits of the currently transmitted channel. This buffering mechanism provides more cycles for writing the next audio data to XADR. These registers are not directly accessible by DSP instructions.
12.5.3
DAX AUDIO DATA SHIFT REGISTER (XADSR)
The XADSR is a 27-bit shift register that shifts the 24-bit audio data and the 3-bit non-audio data for one subframe. The contents of XADBUFA or XADBUFB are directly transferred to the XADSR at the beginning of the subframe transmission. The channel A subframe is transferred to XADSR at the same time that the three bits of non-audio data (V-bit, U-bit and C-bit) for channel A in the DAX non-audio data register (XNADR) are transferred to the three highest-order bits of the XADSR. At the beginning of the channel B transmission, audio and non-audio data for channel B are transferred from the XADBUFB and the XNADBUF to the XADSR for shifting. The data in the XADSR is shifted toward the lowest-order bit at the fifth to thirty-first bit slot of each subframe transmission. This register is not directly accessible by DSP instructions.
12.5.4
DAX NON-AUDIO DATA REGISTER (XNADR)
The XNADR is a 24-bit write-only register. It holds the three bits of non-audio data for each subframe. XNADR can be accessed by core instructions or by DMA. The contents of the XNADR are shown in Figure 12-2. XNADR is not affected by any of the DAX reset states. The XNADR bits are described in the following paragraphs. 12.5.4.1 DAX Channel A Validity (XVA)--Bit 10 The value of the XVA bit is transmitted as the twenty-ninth bit (Bit 28) of channel A subframe in the next frame. 12.5.4.2 DAX Channel A User Data (XUA)--Bit 11 The value of the XUA bit is transmitted as the thirtieth bit (Bit 29) of the channel A subframe in the next frame.
12-6
DSP56367
MOTOROLA
Digital Audio Transmitter DAX Internal Architecture
12.5.4.3 DAX Channel A Channel Status (XCA)--Bit 12 The value of the XCA bit is transmitted as the thirty-first bit (Bit 30) of the channel A subframe in the next frame. 12.5.4.4 DAX Channel B Validity (XVB)--Bit 13 The value of the XVB bit is transmitted as the twenty-ninth bit (Bit 28) of the channel B subframe in the next frame. 12.5.4.5 DAX Channel B User Data (XUB)--Bit 14 The value of the XUB bit is transmitted as the thirtieth bit (Bit 29) of the channel B subframe in the next frame. 12.5.4.6 DAX Channel B Channel Status (XCB)--Bit 15 The value of the XCB bit is transmitted as the thirty-first bit (Bit 30) of the channel B subframe in the next frame. 12.5.4.7 XNADR Reserved Bits--Bits 0-9, 16-23 These XNADR bits are reserved. They read as 0, and should be written with 0 to ensure compatibility with future device versions.
12.5.5
DAX NON-AUDIO DATA BUFFER (XNADBUF)
The XNADBUF is a 3-bit register that temporarily holds channel B non-audio data (XVB, XUB and XCB) for the current transmission while the channel A data is being transmitted. This mechanism provides programmers more instruction cycles to store the next frame's non-audio data to the XCB, XUB, XVB, XCA, XUA and XVA bits in the XNADR. The data in the XNADBUF register is transferred to the XADSR along with the contents of the XADBUF register at the beginning of channel B transmission. Note: The XNADBUF register is not directly accessible by DSP instructions.
12.5.6
DAX CONTROL REGISTER (XCTR)
The XCTR is a 24-bit read/write register that controls the DAX operation. The contents of the XCTR are shown in Figure 12-2. XCTR is cleared by software reset and hardware reset. The XCTR bits are described in the following paragraphs.
MOTOROLA
DSP56367
12-7
Digital Audio Transmitter DAX Internal Architecture
12.5.6.1 Audio Data Register Empty Interrupt Enable (XDIE)--Bit 0 When the XDIE bit is set, the audio data register empty interrupt is enabled and sends an interrupt request signal to the DSP if the XADE status bit is set. When XDIE bit is cleared, this interrupt is disabled. 12.5.6.2 Underrun Error Interrupt Enable (XUIE)--Bit 1 When the XUIE bit is set, the underrun error interrupt is enabled and sends an interrupt request signal to the DSP if the XAUR status bit is set. When XUIE bit is cleared, this interrupt is disabled. 12.5.6.3 Block Transferred Interrupt Enable (XBIE)--Bit 2 When the XBIE bit is set, the block transferred interrupt is enabled and sends an interrupt request signal to the DSP if the XBLK and XADE status bits are set. When XBIE bit is cleared, this interrupt is disabled. 12.5.6.4 DAX Clock Input Select (XCS[1:0])--Bits 3-4 The XCS[1:0] bits select the source of the DAX clock and/or its frequency. Table 12-3 shows the configurations selected by these bits. These bits should be changed only when the DAX is disabled. Table 12-3 Clock Source Selection
XCS1 0 0 1 1 XCS0 0 1 0 1 DAX Clock Source DSP Core Clock (f = 1024 x fs) ACI Pin, f = 256 x fs ACI Pin, f = 384 x fs ACI Pin, f = 512 x fs
12.5.6.5 DAX Start Block (XSB)--Bit 5 The XSB bit forces the DAX to start a new block. When this bit is set, the next frame will start with "Z" preamble and will start a new block even though the current block was not finished. This bit is cleared when the new block starts. 12.5.6.6 XCTR Reserved Bits--Bits 6-23 These XCTR bits are reserved. They read as 0 and should be written with 0 for future compatibility.
12-8
DSP56367
MOTOROLA
Digital Audio Transmitter DAX Internal Architecture
12.5.7
DAX STATUS REGISTER (XSTR)
The XSTR is a 24-bit read-only register that contains the DAX status flags. The contents of the XSTR are shown in Figure 12-2. XSTR is cleared by software reset, hardware reset an by the stop state. The XSTR bits are described in the following paragraphs. 12.5.7.1 DAX Audio Data Register Empty (XADE)--Bit 0 The XADE status flag indicates that the DAX audio data register XADR and the audio data buffer XADBUFA are empty (and ready to receive the next frame's audio data). This bit is set at the beginning of every frame transmission (more precisely, when channel A audio data is transferred from XADBUFA to XADSR). When XADE is set and the interrupt is enabled (XDIE = 1), an audio data register empty interrupt request is sent to the DSP core. XADE is cleared by writing two channels of audio data to XADR. 12.5.7.2 DAX Transmit Underrun Error Flag (XAUR)--Bit 1 The XAUR status flag is set when the DAX audio data buffers XADBUFA or XADBUFB are empty and the respective audio data upload occurs. When a DAX underrun error occurs, the previous frame data will be retransmitted in both channels. When XAUR is set and the interrupt is enabled (XUIE = 1), an underrun error interrupt request is sent to the DSP core. This allows programmers to write an exception handling routine for this special case. The XAUR bit is cleared by reading the XSTR register with XAUR set, followed by writing two channels of audio data to XADR. 12.5.7.3 DAX Block Transfer Flag (XBLK)--Bit 2 The XBLK flag indicates that the frame being transmitted is the last frame in a block. This bit is set at the beginning of the transmission of the last frame (the 191st frame). This bit does not cause any interrupt. However, if XBIE=1 it causes a change in the interrupt vector sent to DSP core in the event of an audio data register empty interrupt, so that a different interrupt routine can be called (providing the next non-audio data structures for the next block as well as storing audio data for the next frame). Writing two channels of audio data to XADR clears this bit. The relative timing of transmit frames and XADE and XBLK flags is shown in Figure 12-3.
MOTOROLA
DSP56367
12-9
Digital Audio Transmitter DAX Internal Architecture
Frame XADE XBLK Frame XADE XBLK
#000 #001 #002 #003 #004 #005 #006 #007 #008 #009 #010 #011 #012 #013 #014 #015 #016 #017 #018 #019 #020 #021 #022 #023
#024 #025 #026 #027 #028 #029 #030 #031 #032 #033 #034 #035 #036 #037 #038 #039 #040 #041 #042 #043 #044 #045 #046 #047
Frame XADE XBLK
#168 #169 #170 #171 #172 #173 #174 #175 #176 #177 #178 #179 #180 #181 #182 #183 #184 #185 #186 #187 #188 #189 #190 #191
AA0608
Figure 12-3 DAX Relative Timing 12.5.7.4 XSTR Reserved Bits--Bits 3-23 These XSTR bits are reserved. They read as 0, and should be written with 0 to ensure compatibility with future device versions.
12.5.8
DAX PARITY GENERATOR (PRTYG)
The PRTYG generates the parity bit for the subframe being transmitted. The generated parity bit ensures that subframe bits four to thirty-one will carry an even number of ones and zeroes.
12.5.9
DAX BIPHASE ENCODER
The DAX biphase encoder encodes each audio and non-audio bit into its biphase mark format and shifts this encoded data out to the ADO output pin synchronously to the biphase clock.
12.5.10
DAX PREAMBLE GENERATOR
The DAX preamble generator automatically generates one of three preambles in the 8-bit preamble shift register at the beginning of each subframe transmission, and shifts it out. The generated preambles always start with "0". Bit patterns of preambles generated in the
12-10
DSP56367
MOTOROLA
Digital Audio Transmitter DAX Internal Architecture
preamble generator are shown in Table 12-4. The preamble bits are already in the biphase mark format. Table 12-4 Preamble Bit Patterns
Preamble X Y Z Bit Pattern 00011101 00011011 00010111 Channel A B A (first in block)
There is no programmable control for the preamble selection. The first subframe to be transmitted (immediately after the DAX is enabled) is the beginning of a block, and therefore it has a "Z" preamble. This is followed by the second subframe, which has an "Y" preamble. After that, "X" and "Y" preambles are transmitted alternately until the end of the block transfer (192 frames transmitted). See Figure 12-4 for an illustration of the preamble sequence.
DAX Enabled Here
Z
Y
X
Y
X
Y
X
Y
Z
Y
X
Y
First Block (384 subframes)
Second Block
AA0609k
Figure 12-4 Preamble sequence
12.5.11
DAX CLOCK MULTIPLEXER
The DAX clock multiplexer selects one of the clock sources and generates the biphase clock (128 x Fs) and shift clock (64 x Fs). The clock source can be selected from the following options (see also Section 12.5.6.4, "DAX Clock Input Select (XCS[1:0])--Bits 3-4"). * * * * The internal DSP core clock--assumes 1024 x Fs DAX clock input pin (ACI)--512 x Fs DAX clock input pin (ACI)--384 x Fs DAX clock input pin (ACI)--256 x Fs
MOTOROLA
DSP56367
12-11
Digital Audio Transmitter DAX Programming Considerations
Figure 12-5 shows how each clock is divided to generate the biphase and bit shift clocks
DSP Core Clock (1024 x Fs) ACI Pin {256,384,512} x Fs 1/2 2/3 0 1
1/4 MUX 1 0 MUX 0 MUX 1 (XCS1 or XCS0) XCS1 XCS0 1/2 Biphase Clock (128 x Fs) Bit Shift Clock (64 x Fs)
AA0610
1/2
Figure 12-5 Clock Multiplexer Diagram Note: For proper operation of the DAX, the DSP core clock frequency must be at least five times higher than the DAX bit shift clock frequency (64 x Fs).
12.5.12
DAX STATE MACHINE
The DAX state machine generates a set of sequencing signals used in the DAX.
12.6
DAX PROGRAMMING CONSIDERATIONS
The following sections describe programming considerations for the DAX.
12.6.1
INITIATING A TRANSMIT SESSION
To initiate the DAX operation, follow this procedure: 1. Ensure that the DAX is disabled (PC1 and PC0 bits of port control register PCR are cleared) 2. Write the non-audio data to the corresponding bits in the XNADR register 3. Write the channel A and channel B audio data in the XADR register 4. Write the transmit mode to the XCTR register
12-12
DSP56367
MOTOROLA
Digital Audio Transmitter DAX Programming Considerations
5. Enable DAX by setting PC1 bit (and by setting PC0 bit if in slave mode) in the port control register (PCR); transmission begins.
12.6.2
AUDIO DATA REGISTER EMPTY INTERRUPT HANDLING
When the XDIE bit is set and the DAX is active, an audio data register empty interrupt (XADE = 1) is generated once at the beginning of every frame transmission. Typically, within an XADE interrupt, the non-audio data bits of the next frame are stored in XNADR and one frame of audio data to be transmitted in the next frame is stored in the FIFO by two consecutive MOVEP instructions to XADR. If the non-audio bits are not changed from frame to frame, this procedure can be handled within a fast interrupt routine. Storing the next frame's audio data in the FIFO clears the XADE bit in the XSTR.
12.6.3
BLOCK TRANSFERRED INTERRUPT HANDLING
An interrupt with the XBLK vector indicates the end of a block transmission and may require some computation to provide the next non-audio data structures that are to be transmitted within the next block. Within the routine, the next audio data can be stored in the FIFO by two consecutive MOVEP instructions to XADR, and the next non-audio data can be stored in the XNADR. The XBLK interrupt occurs only if the XBIE bit in XCTR is set. If XBIE is cleared, a XADE interrupt vector will take place.
12.6.4
DAX OPERATION WITH DMA
During DMA transfers, the XDIE bit of the XCTR must be cleared to avoid XADE interrupt services by the DSP core. The initialization appearing in Section 12.6.1 is relevant for DMA
MOTOROLA
DSP56367
12-13
Digital Audio Transmitter DAX Programming Considerations
operation. DMA transfers can be performed with or without changing non-audio bits from frame to frame. Table 12-5 describes two examples of DMA configuration. Table 12-5 Examples of DMA configuration
Register DCR2 Non-audio data bits change DE=1; Enable DMA channel. DIE=1; Enable DMA interrupt. DTM[2:0]=010; Line transfer mode. D3D=0; Not 3D. DAM[5:3]=000; 2D mode. DAM[2:0]=101; post increment by 1. DDS[1:0]=00; X memory space. DRS[4:0]=01010; DAX is DMA request source. Other bits are application dependent. DCOH=number of frames in block - 1 DCOL=$002; 3 destination registers first memory address of the block XNADR address (base address + $1) $FFFFFE; offset=-2 Non-audio data bits do not change DE=1; Enable DMA channel. DIE=1; Enable DMA interrupt. DTM[2:0]=010; Line transfer mode. D3D=0; Not 3D. DAM[5:3]=000; 2D mode. DAM[2:0]=101; post increment by 1. DDS[1:0]=00; X memory space. DRS[4:0]=01010; DAX is DMA request source. Other bits are application dependent. DCOH=number of frames in block - 1 DCOL=$001; 2 destination registers first memory address of the block XADR address (base address + $2) $FFFFFF; offset=-1
DCO2
DSR2 DDR2 DOR0
The memory organization employed for DMA transfers depends on whether or not non-audio data changes from frame to frame as shown in Figure 12-6.
12-14
DSP56367
MOTOROLA
Digital Audio Transmitter GPIO (PORT D) - Pins and Registers
Channel B Channel A Non-Audio Data Channel B Channel A Non-Audio Data Channel B Channel A Non-Audio Data Channel B Channel A Non-Audio Data
$00000B $00000A $000009 $000008 $000007 $000006 $000005 $000004 $000003 $000002 $000001
Channel B Channel A Channel B Channel A Channel B Channel A Channel B Channel A Channel B Channel A
$00000B $00000A $000009 $000008 $000007 $000006 $000005 $000004 $000003 $000002
$000000 Non-audio data bits change from frame to frame
$000001 Channel B $000000 Channel A Non-audio data bits do not change from frame to frame
Figure 12-6 Examples of data organization in memory
12.6.5
DAX OPERATION DURING STOP
The DAX operation cannot continue when the DSP is in the stop state since no DSP clocks are active. While the DSP is in the stop state, the DAX will remain in the individual reset state and the status flags are initialized as described for resets. No DAX control bits are affected. The DAX should be disabled before the DSP enters the stop state.
12.7
GPIO (PORT D) - PINS AND REGISTERS
The Port D GPIO functionality of the DAX is controlled by three registers: Port D Control Register (PCRD), Port D Direction Register (PRRD) and Port D Data Register (PDRD).
MOTOROLA
DSP56367
12-15
Digital Audio Transmitter GPIO (PORT D) - Pins and Registers
12.7.1
PORT D CONTROL REGISTER (PCRD)
The read/write 24-bit DAX Port D Control Register controls the functionality of the DAX GPIO pins. Each of the PC[1:0] bits controls the functionality of the corresponding port pin. When a PC[i] bit is set, the corresponding port pin is configured as a DAX pin. When a PC[i] bit is cleared, the corresponding port pin is configured as GPIO pin. If both PC1 and PC0 are cleared, the DAX is disabled. Hardware and software reset clear all PCRD bits.
PCRD -Port D Control Register - X:$FFFFD7 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC1 PC0
read as zero, should be written with zero for future compatibility
Figure 12-7 Port D Control Register (PCRD)
12.7.2
PORT D DIRECTION REGISTER (PRRD)
The read/write 24-bit Port D Direction Register controls the direction of the DAX GPIO pins. When port pin[i] is configured as GPIO, PDC[i] controls the port pin direction. When PDC[i] is set, the GPIO port pin[i] is configured as output. When PDC[i] is cleared the GPIO port pin[i] is configured as input. Hardware and software reset clear all PRRD bits. Table 12-6 describes the port pin configurations.
PRRD - Port D Direction Register - X:$FFFFD6 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDC1 PDC0
read as zero, should be written with zero for future compatibility
Figure 12-8 Port D Direction Register (PRRD)
12-16
DSP56367
MOTOROLA
Digital Audio Transmitter GPIO (PORT D) - Pins and Registers
Table 12-6 DAX Port GPIO Control Register Functionality
PDC1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PC1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ADO/PD1 pin Disconnected Disconnected Disconnected Disconnected PD1 Input PD1 Input PD1 Input PD1 Input PD1 Output PD1 Output PD1 Output PD1 Output ADO ADO ADO ADO PDC0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ACI/PD0 pin Disconnected PD0 Input PD0 Output ACI Disconnected PD0 Input PD0 Output ACI Disconnected PD0 Input PD0 Output ACI Disconnected PD0 Input PD0 Output ACI DAX state Personal Reset Personal Reset Personal Reset Enabled Personal Reset Personal Reset Personal Reset Enabled Personal Reset Personal Reset Personal Reset Enabled Enabled Enabled Enabled Enabled
12.7.3
PORT D DATA REGISTER (PDRD)
The read/write 24-bit Port D Data Register is used to read or write data to/from the DAX GPIO pins. Bits PD[1:0] are used to read or write data from/to the corresponding port pins if they are configured as GPIO. If a port pin [i] is configured as a GPIO input, then the corresponding PD[i] bit will reflect the value present on this pin. If a port pin [i] is configured as a GPIO output, then the value written into the corresponding PD[i] bit will be reflected on the this pin. Hardware and software reset clear all PDRD bits.
MOTOROLA
DSP56367
12-17
Digital Audio Transmitter GPIO (PORT D) - Pins and Registers
PDRD - Port D Data Register - X:$FFFFD5 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD1 PD0
read as zero, should be written with zero for future compatibility
Figure 12-9 Port D Data Register (PDRD)
12-18
DSP56367
MOTOROLA
SECTION
13
TIMER/ EVENT COUNTER
13.1 INTRODUCTION
This section describes the internal timer/event counter in the DSP56367. Each of the three timers (timer 0, 1 and 2) can use internal clocking to interrupt the DSP56367 or trigger DMA transfers after a specified number of events (clocks). In addition, timer 0 provides external access via the bidirectional signal TIO0. When the TIO0 pin is configured as an input, timer 0 can count or capture events, or measure the width or period of an external signal. When TIO0 is configured as an output, timer 0 can function as a timer, a watchdog timer, or a pulse width modulator. TIO0 can also function as a GPIO signal.
13.2
TIMER/EVENT COUNTER ARCHITECTURE
The timer module is composed of a common 21-bit prescaler and three independent general purpose 24-bit timer/event counters, each having its own register set.
13.2.1
TIMER/EVENT COUNTER BLOCK DIAGRAM
Figure 13-1 shows a block diagram of the timer/event counter. This module includes a 24-bit timer prescaler load register (TPLR), a 24-bit timer prescaler count register (TPCR), a 21-bit prescaler clock counter, and three timers. Each of the three timers may use the prescaler clock as its clock source.
MOTOROLA
DSP56367
13-1
Timer/ Event Counter Timer/Event Counter Architecture
GDB 24 TPLR Timer Prescaler Load Register 24 TPCR
24
24 Timer Prescaler Count Register
Timer 0
21-bit Prescaler Counter
Timer 1
Timer 2
CLK/2
TIO0
AA0673
Figure 13-1 Timer/Event Counter Block Diagram
13.2.2
INDIVIDUAL TIMER BLOCK DIAGRAM
Figure 13-2 shows the structure of an individual timer module. The three timers are identical in structure, but only timer 0 is externally accessible. Each timer includes a 24-bit counter, a 24-bit read/write timer control and status register (TCSR), a 24-bit read-only timer count register (TCR), a 24-bit write-only timer load register (TLR), a 24-bit read/write timer compare register (TCPR), and logic for clock selection and interrupt/DMA trigger generation. The timer mode is controlled by the TC[3:0] bits of the timer control/status register (TCSR). Timer modes are described in Section 13.4.
13-2
DSP56367
MOTOROLA
Timer/ Event Counter Timer/Event Counter Programming Model
GDB
24
24 TCSR Control/Status Register
24 TLR Load Register
24 TCR Count Register
24 TCPR Compare Register
9 2
24
24 24
24
Timer Control Logic
Counter
=
Timer interrupt/ DMA request TIO CLK/2 (Timer 0 only) prescaler CLK
AA0676
Figure 13-2 Timer Block Diagram
13.3
TIMER/EVENT COUNTER PROGRAMMING MODEL
The DSP56367 views each timer as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data memory space. Either standard polled or interrupt programming techniques can be used to service the timers. The timer programming model is shown in Figure 13-3.
MOTOROLA
DSP56367
13-3
Timer/ Event Counter Timer/Event Counter Programming Model
23
0 Timer Prescaler Load Register (TPLR) TPLR = $FFFF83
23
0 Timer Prescaler Count Register (TPCR) TPLR = $FFFF82
7
TC3 15 PCE 23
6
5
4
TC0 12 DI 20
3
2
1
0
TE 8 Timer Control/Status Register (TCSR) TCSR0 = $FFFF8F TCSR1 = $FFFF8B TCSR2 = $FFFF87
TC2 TC1 14 13 DO 22 21
TCIE TOIE 11 DIR 19 18 10 9
TRM INV 17 16
TCF TOF
23
0 Timer Load Register (TLR) TLR0 = $FFFF8E TLR1 = $FFFF8A TLR2 = $FFFF86
23
0 Timer Compare Register (TCPR) TCPR0 = $FFFF8D TCPR1 = $FFFF89 TCPR2 = $FFFF85
23
0 Timer Count Register (TCR) TCR0 = $FFFF8C TCR1 = $FFFF88 TCR2 = $FFFF84
- reserved, read as 0, should be written with 0 for future compatibility
Figure 13-3 Timer Module Programmer's Model
13-4
DSP56367
MOTOROLA
Timer/ Event Counter Timer/Event Counter Programming Model
13.3.1
PRESCALER COUNTER
The prescaler counter is a 21-bit counter that is decremented on the rising edge of the prescaler input clock. The counter is enabled when at least one of the three timers is enabled (i.e., one or more of the timer enable (TE) bits are set) and is using the prescaler output as its source (i.e., one or more of the PCE bits are set).
13.3.2
TIMER PRESCALER LOAD REGISTER (TPLR)
The TPLR is a 24-bit read/write register that controls the prescaler divide factor (i.e., the number that the prescaler counter will load and begin counting from) and the source for the prescaler input clock. See Figure 13-4.
23 11 PL11 22 PS1 10 PL10 21 PS0 9 PL9 20 PL20 8 PL8 19 PL19 7 PL7 18 PL18 6 PL6 17 PL17 5 PL5 16 PL16 4 PL4 15 PL15 3 PL3 14 PL14 2 PL2 13 PL13 1 PL1 12 PL12 0 PL0
-- reserved, read as 0, should be written with 0 for future compatibility
Figure 13-4 Timer Prescaler Load Register (TPLR) 13.3.2.1 TPLR Prescaler Preload Value PL[20:0] Bits 20-0 These 21 bits contain the prescaler preload value. This value is loaded into the prescaler counter when the counter value reaches zero or the counter switches state from disabled to enabled. If PL[20:0] = N, then the prescaler counts N + 1 source clock cycles before generating a prescaler clock pulse. Therefore, the prescaler divide factor = (preload value) + 1. The PL[20:0] bits are cleared by the hardware RESET signal or the software RESET instruction.
13.3.2.2 TPLR Prescaler Source PS[1:0] Bits 22-21 The two prescaler source (PS) bits control the source of the prescaler clock. Table 13-1 summarizes PS bit functionality. The prescaler's use of the TIO0 signal is not affected by the TCSR settings of timer 0. If the prescaler source clock is external, the prescaler counter is incremented by signal transitions on the TIO0 signal. The external clock is internally synchronized to the internal clock. The external clock frequency must be lower than the DSP56367 internal operating frequency divided by 4 (CLK/4).
MOTOROLA
DSP56367
13-5
Timer/ Event Counter Timer/Event Counter Programming Model
The PS[1:0] bits are cleared by the hardware RESET signal or the software RESET instruction. Note: To ensure proper operation, change the PS[1:0] bits only when the prescaler counter is disabled. Disable the prescaler counter by clearing the TE bit in the TCSR of each of three timers. Table 13-1 Prescaler Source Selection
PS1 0 0 1 1 PS0 0 1 0 1 PRESCALER CLOCK SOURCE Internal CLK/2 TIO0 Reserved Reserved
13.3.2.3 TPLR Reserved Bit 23 This reserved bit is read as zero and should be written with zero for future compatibility.
13.3.3
TIMER PRESCALER COUNT REGISTER (TPCR)
The TPCR is a 24-bit read-only register that reflects the current value in the prescaler counter. See Figure 13-5.
23 11 PC11 22 10 PC10 21 9 PC9 20 PC20 8 PC8 19 PC19 7 PC7 18 PC18 6 PC6 17 PC17 5 PC5 16 PC16 4 PC4 15 PC15 3 PC3 14 PC14 2 PC2 13 PC13 1 PC1 12 PC12 0 PC0
-- reserved, read as 0, should be written with 0 for future compatibility
Figure 13-5 Timer Prescaler Count Register (TPCR) 13.3.3.1 TPCR Prescaler Counter Value PC[20:0] Bits 20-0 These 21 bits contain the current value of the prescaler counter. 13.3.3.2 TPCR Reserved Bits 23-21 These reserved bits are read as zero and should be written with zero for future compatibility.
13-6
DSP56367
MOTOROLA
Timer/ Event Counter Timer/Event Counter Programming Model
13.3.4
TIMER CONTROL/STATUS REGISTER (TCSR)
The TCSR is a 24-bit read/write register controlling the timer and reflecting its status. 13.3.4.1 TCSR Timer Enable (TE) Bit 0 The timer enable (TE) bit is used to enable or disable the timer. Setting TE enables the timer and clears the timer counter. The counter starts counting according to the mode selected by the timer control (TC[3:0]) bit values. Clearing the TE bit disables the timer. The TE bit is cleared by the hardware RESET signal or the software RESET instruction. Note: When timer 0 is disabled and TIO0 is not in GPIO mode, the pin is tri-stated. To prevent undesired spikes on TIO0 when Timer 0 is switched from tri-state to an active state, TIO0 should be tied to the power supply with a pullup or pulldown resistor.
13.3.4.2 TCSR Timer Overflow Interrupt Enable (TOIE) Bit 1 The TOIE bit is used to enable the timer overflow interrupts. Setting TOIE enables overflow interrupt generation. The timer counter can hold a maximum value of $FFFFFF. When the counter value is at the maximum value and a new event causes the counter to be incremented to $000000, the timer generates an overflow interrupt. Clearing the TOIE bit disables overflow interrupt generation. The TOIE bit is cleared by the hardware RESET signal or the software RESET instruction. 13.3.4.3 TCSR Timer Compare Interrupt Enable (TCIE) Bit 2 The Timer Compare Interrupt Enable (TCIE) bit is used to enable or disable the timer compare interrupts. Setting TCIE enables the compare interrupts. In the timer, PWM, or watchdog modes, a compare interrupt is generated after the counter value matches the value of the TCPR. The counter will start counting up from the number loaded from the TLR and if the TCPR value is N, an interrupt occurs after (N - M + 1) events, where M is the value of TLR. Clearing the TCIE bit disables the compare interrupts. The TCIE bit is cleared by the hardware RESET signal or the software RESET instruction. 13.3.4.4 TCSR Timer Control (TC[3:0]) Bits 4-7 The four TC bits control the source of the timer clock, the behavior of the TIO0 signal, and the timer mode of operation. Table 13-2 summarizes the TC bit functionality. A detailed description of the timer operating modes is given in Section 13.4. The TC bits are cleared by the hardware RESET signal or the software RESET instruction.
MOTOROLA
DSP56367
13-7
Timer/ Event Counter Timer/Event Counter Programming Model
Notes:
1.
If the clock is external, the counter is incremented by the transitions on the TIO0 signal. The external clock is internally synchronized to the internal clock, and its frequency should be lower than the internal operating frequency divided by 4 (CLK/4).
2. To ensure proper operation, the TC[3:0] bits should be changed only when the timer is disabled (when the TE bit in the TCSR has been cleared). Table 13-2 Timer Control Bits for Timer 0
Bit Settings Mode Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode Characteristics
TC3
TC2
TC1
TC0
Mode Function
TIO0
Clock
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Timer and GPIO Timer pulse Timer toggle Event counter Input width measurement Input period measurement Capture event Pulse width modulation Reserved Watchdog pulse Watchdog toggle Reserved Reserved Reserved Reserved Reserved
GPIO* Output Output Input Input Input Input Output -- Output Output -- -- -- -- --
Internal Internal Internal External Internal Internal Internal Internal -- Internal Internal -- -- -- -- --
Note:
The GPIO function is enabled only if all of the TC[3:0] bits are zero.
13-8
DSP56367
MOTOROLA
Timer/ Event Counter Timer/Event Counter Programming Model
Table 13-3 Timer Control Bits for Timers 1 and 2
TC3 0 0 0 0 1 TC2 0 0 0 1 X TC1 0 0 1 X X TC0 0 1 X X X Clock Internal -- -- -- -- Mode Timer Reserved Reserved Reserved Reserved
13.3.4.5 TCSR Inverter (INV) Bit 8 The INV bit affects the polarity of the incoming signal on the TIO0 input signal and the polarity of the output pulse generated on the TIO0 output signal. The effects of the INV bit are summarized in Table 13-4. This bit is not in use for timers 1 and 2. It should be left cleared.
Table 13-4 Inverse Bit
TIO0 Programmed as Input Mode INV = 0 0 GPIO signal on the TIO0 signal read directly INV = 1 GPIO signal on the TIO0 signal inverted INV = 0 Bit written to GPIO put on TIO0 signal directly INV = 1 Bit written to GPIO TIO0 Programmed as Output
inverted and put on
TIO0 signal --
1
Counter is incremented on the rising edge of the signal from the TIO0 signal Counter is incremented on the rising edge of the signal from the TIO0 signal Counter is incremented on the rising edge of the signal from the TIO0 signal Width of the high input pulse is measured. Period is measured between the rising edges of the input signal.
Counter is incremented on the falling edge of the signal from the TIO0 signal Counter is incremented on the falling edge of the signal from the TIO0 signal Counter is incremented on the falling edge of the signal from the TIO0 signal Width of the low input pulse is measured. Period is measured between the falling edges of the input signal.
--
2
TCRx output put on TIO0 signal directly
TCRx output inverted and put on TIO0 signal
3
--
--
4
--
--
5
--
--
MOTOROLA
DSP56367
13-9
Timer/ Event Counter Timer/Event Counter Programming Model
Table 13-4 Inverse Bit
TIO0 Programmed as Input Mode INV = 0 6 Event is captured on the rising edge of the signal from the TIO0 signal -- INV = 1 Event is captured on the falling edge of the signal from the TIO0 signal -- INV = 0 -- INV = 1 -- TIO0 Programmed as Output
7
Pulse generated by the timer has positive polarity Pulse generated by the timer has positive polarity Pulse generated by the timer has positive polarity
Pulse generated by the timer has negative polarity Pulse generated by the timer has negative polarity Pulse generated by the timer has negative polarity
9
--
--
10
--
--
The INV bit is cleared by the hardware RESET signal or the software RESET instruction. Note: The INV bit affects both the timer and GPIO modes of operation. To ensure correct operation, this bit should be changed only when one or both of the following conditions is true: * * The timer has been disabled by clearing the TE bit in the TCSR. The timer is in GPIO mode.
The INV bit does not affect the polarity of the prescaler source when TIO0 is used as input to the prescaler. 13.3.4.6 TCSR Timer Reload Mode (TRM) Bit 9 The TRM bit controls the counter preload operation. In timer (0-3) and watchdog (9-10) modes, the counter is preloaded with the TLR value after the TE bit is set and the first internal or external clock signal is received. If the TRM bit is set, the counter is reloaded each time after it reaches the value contained by the TCR. In PWM mode (7), the counter is reloaded each time counter overflow occurs. In measurement (4-5) modes, if the TRM and the TE bits are set, the counter is preloaded with the TLR value on each appropriate edge of the input signal. If the TRM bit is cleared, the counter operates as a free-running counter and is incremented on each incoming event. The TRM bit is cleared by the hardware RESET signal or the software RESET instruction. 13.3.4.7 TCSR Direction (DIR) Bit 11 The DIR bit determines the behavior of the TIO0 signal when it is used as a GPIO pin. When the DIR bit is set, the TIO0 signal is an output; when the DIR bit is cleared, the TIO0 signal is
13-10
DSP56367
MOTOROLA
Timer/ Event Counter Timer/Event Counter Programming Model
an input. The TIO0 signal can be used as a GPIO only when the TC[3:0] bits are all cleared. If any of the TC[3:0] bits are set, then the GPIO mode is disabled and the DIR bit has no effect. The DIR bit is cleared by the hardware RESET signal or the software RESET instruction. This bit is not in use for timers 1 and 2. It should be left cleared. 13.3.4.8 TCSR Data Input (DI) Bit 12 The DI bit reflects the value of the TIO0 signal. If the INV bit is set, the value of the TIO0 signal is inverted before it is written to the DI bit. If the INV bit is cleared, the value of the TIO0 signal is written directly to the DI bit. DI is cleared by the hardware RESET signal or the software RESET instruction. 13.3.4.9 TCSR Data Output (DO) Bit 13 The DO bit is the source of the TIO0 value when it is a data output signal. The TIO0 signal is data output when the GPIO mode is enabled and DIR is set. A value written to the DO bit is written to the TIO0 signal. If the INV bit is set, the value of the DO bit is inverted when written to the TIO0 signal. When the INV bit is cleared, the value of the DO bit is written directly to the TIO0 signal. When GPIO mode is disabled, writing the DO bit has no effect. The DO bit is cleared by the hardware RESET signal or the software RESET instruction. This bit is not in use for timers 1 and 2. It should be left cleared. 13.3.4.10 TCSR Prescaler Clock Enable (PCE) Bit 15 The PCE bit is used to select the prescaler clock as the timer source clock. When the PCE bit is cleared, the timer uses either an internal (CLK/2) signal or an external signal (TIO0) as its source clock. When the PCE bit is set, the prescaler output is used as the timer source clock for the counter regardless of the timer operating mode. To ensure proper operation, the PCE bit should be changed only when the timer is disabled (when the TE bit is cleared). Which source clock is used for the prescaler is determined by the PS[1:0] bits of the TPLR. Timers 1 and 2 can be clocked by the prescaler clock derived from TIO0. 13.3.4.11 TCSR Timer Overflow Flag (TOF) Bit 20 The TOF bit is set to indicate that counter overflow has occurred. This bit is cleared by writing a 1 to the TOF bit. Writing a 0 to the TOF bit has no effect. The bit is also cleared when the timer overflow interrupt is serviced. The TOF bit is cleared by the hardware RESET signal, the software RESET instruction, the STOP instruction, or by clearing the TE bit to disable the timer.
MOTOROLA
DSP56367
13-11
Timer/ Event Counter Timer/Event Counter Programming Model
13.3.4.12 TCSR Timer Compare Flag (TCF) Bit 21 The TCF bit is set to indicate that the event count is complete. In the timer, PWM, and watchdog modes, the TCF bit is set when (N - M + 1) events have been counted (N is the value in the compare register and M is the TLR value). In the measurement modes, the TCF bit is set when the measurement has been completed. The TCF bit is cleared by writing a one into the TCF bit. Writing a zero into the TCF bit has no effect. The bit is also cleared when the timer compare interrupt is serviced. The TCF bit is cleared by the hardware RESET signal, the software RESET instruction, the STOP instruction, or by clearing the TE bit to disable the timer. Note: The TOF and TCF bits are cleared by writing a one to the specific bit. In order to assure that only the desired bit is cleared, do not use the BSET command. The proper way to clear these bits is to write (using a MOVEP instruction) a one to the flag to be cleared and a zero to the other flag.
13.3.4.13 TCSR Reserved Bits (Bits 3, 10, 14, 16-19, 22, 23) These reserved bits are read as zero and should be written with zero for future compatibility.
13.3.5
TIMER LOAD REGISTER (TLR)
The TLR is a 24-bit write-only register. In all modes, the counter is preloaded with the TLR value after the TE bit in the TCSR is set and a first event occurs. The programmer must initialize the TLR to ensure correct operation in the appropriate timer operating modes. * In timer modes, if the timer reload mode (TRM) bit in the TCSR is set, the counter is reloaded each time after it has reached the value contained by the timer compare register (TCR) and the new event occurs. In measurement modes, if the TRM bit in the TCSR is set and the TE bit in the TCSR is set, the counter is reloaded with the value in the TLR on each appropriate edge of the input signal. In PWM modes, if the TRM bit in the TCSR is set, the counter is reloaded each time after it has overflowed and the new event occurs. In watchdog modes, if the TRM bit in the TCSR is set, the counter is reloaded each time after it has reached the value contained by the TCR and the new event occurs. In this mode, the counter is also reloaded whenever the TLR is written with a new value while the TE bit in the TCSR is set. In all modes, if the TRM bit in the TCSR is cleared (TRM = 0), the counter operates as a free-running counter.
*
* *
*
13-12
DSP56367
MOTOROLA
Timer/ Event Counter Timer Modes of Operation
13.3.6
TIMER COMPARE REGISTER (TCPR)
The TCPR is a 24-bit read/write register that contains the value to be compared to the counter value. These two values are compared every timer clock after the TE bit in the TCSR is set. When the values match, the timer compare flag (TCF) bit is set and an interrupt is generated if interrupts are enabled (if the timer compare interrupt enable (TCIE) bit in the TCSR is set). The programmer must initialize the TCPR to ensure correct operation in the appropriate timer operating modes. The TCPR is ignored in measurement modes.
13.3.7
TIMER COUNT REGISTER (TCR)
The TCR is a 24-bit read-only register. In timer and watchdog modes, the counter's contents can be read at any time by reading the TCR register. In measurement modes, the TCR is loaded with the current value of the counter on the appropriate edge of the input signal, and its value can be read to determine the width, period, or delay of the leading edge of the input signal. When the timer is in measurement modes, the TIO0 signal is used for the input signal.
13.4
TIMER MODES OF OPERATION
Each timer has various operational modes that meet a variety of system requirements. These modes are as follows: * Timer - - - GPIO, mode 0: Internal timer interrupt generated by the internal clock Pulse, mode 1: External timer pulse generated by the internal clock Toggle, mode 2: Output timing signal toggled by the internal clock
- Event counter, mode 3: Internal timer interrupt generated by an external clock * Measurement - - - * * Input width, mode 4: Input pulse width measurement Input pulse, mode 5: Input signal period measurement Capture, mode 6: Capture external signal
PWM, mode 7: Pulse Width Modulation Watchdog - Pulse, mode 9: Output pulse, internal clock
MOTOROLA
DSP56367
13-13
Timer/ Event Counter Timer Modes of Operation
-
Toggle, mode 10: Output toggle, internal clock
These modes are described in detail below. Timer modes are selected by setting the TC[3:0] bits in the TCSR. Table 13-2 and Table 13-3 show how the different timer modes are selected by setting the bits in the TCSR. Table 13-2 also shows the TIO0 signal direction and the clock source for each timer mode. Note: To ensure proper operation, the TC[3:0] bits should be changed only when the timer is disabled (i.e., when the TE bit in the TCSR is cleared).
13.4.1
13.4.1.1
TIMER MODES
Timer GPIO (Mode 0)
Bit Settings TC3 0 TC2 0 TC1 0 TC0 0 TIO0 GPIO Clock Internal
Mode Characteristics # 0 KIND Timer NAME GPIO
In this mode, the timer generates an internal interrupt when a counter value is reached (if the timer compare interrupt is enabled). Note that any of the three timers can be placed in GPIO mode to generate internal interrupts, but only timer 0 provides actual external GPIO access on the TIO0 signal. Set the TE bit to clear the counter and enable the timer. Load the value the timer is to count into the TCPR. The counter is loaded with the TLR value when the first timer clock signal is received. The timer clock can be taken from either the DSP56367 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter. When the counter equals the TCPR value, the TCF bit in TCSR is set, and a compare interrupt is generated if the TCIE bit is set. If the TRM bit in the TCSR is set, the counter is reloaded with the TLR value at the next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock signal. This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR.
13-14
DSP56367
MOTOROLA
Timer/ Event Counter Timer Modes of Operation
13.4.1.2
Timer Pulse (Mode 1)
Bit Settings Mode Characteristics TC0 1 TIO0 Output Clock Internal # 1 KIND Timer NAME Pulse
TC3 0
TC2 0
TC1 0
In this mode, the timer generates a compare interrupt when the timer count reaches a preset value. In addition, timer 0 provides an external pulse on its TIO0 signal. Set the TE bit to clear the counter and enable the timer. The value to which the timer is to count is loaded into the TCPR. The counter is loaded with the TLR value when the first timer clock signal is received. The TIO0 signal is loaded with the value of the INV bit. The timer clock signal can be taken from either the DSP56367 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter. When the counter matches the TCPR value, the TCF bit in TCSR is set and a compare interrupt is generated if the TCIE bit is set. The polarity of the TIO0 signal is inverted for one timer clock period. If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock. This process is repeated until the TE bit is cleared (disabling the timer). The value of the TLR sets the delay between starting the timer and the generation of the output pulse. To generate successive output pulses with a delay of X clocks between signals, the TLR value should be set to X/2 and the TRM bit should be set. This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR.
MOTOROLA
DSP56367
13-15
Timer/ Event Counter Timer Modes of Operation
13.4.1.3
Timer Toggle (Mode 2)
Bit Settings Mode Characteristics TC0 0 TIO0 Output Clock Internal # 0 KIND Timer NAME Toggle
TC3 0
TC2 0
TC1 1
In this mode, the timer generates a periodic interrupt; timer 0 also toggles the polarity of the TIO0 signal. Set the TE bit in the TCR to clear the counter and enable the timer. The value the timer is to count is loaded into the TPCR. The counter is loaded with the TLR value when the first timer clock signal is received. The TIO0 signal is loaded with the value of the INV bit. The timer clock signal can be taken from either the DSP56367 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter. When the counter value matches the value in the TCPR, the polarity of the TIO0 output signal is inverted. The TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set. If the TRM bit is set, the counter is loaded with the value of the TLR when the next timer clock is received, and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock. This process is repeated until the TE bit is cleared, disabling the timer. The TLR value in the TCPR sets the delay between starting the timer and toggling the TIO0 signal. To generate output signals with a delay of X clock cycles between toggles, the TLR value should be set to X/2 and the TRM bit should be set. This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR.
13-16
DSP56367
MOTOROLA
Timer/ Event Counter Timer Modes of Operation
13.4.1.4
Timer Event Counter (Mode 3)
Bit Settings Mode Characteristics TC0 1 TIO0 Input Clock External # 3 KIND Timer NAME Event Counter
TC3 0
TC2 0
TC1 1
In this mode, the timer counts internal events and issues an interrupt when a preset number of events is counted. Timer 0 can also count external events. Set the TE bit to clear the counter and enable the timer. The number of events the timer is to count is loaded into the TPCR. The counter is loaded with the TLR value when the first timer clock signal is received. The timer clock signal is provided by the prescaler clock output. Timer 0 can be also be clocked from the TIO0 input signal. Each subsequent clock signal increments the counter. If an external clock is used, it must be internally synchronized to the internal clock and its frequency must be less than the DSP56367 internal operating frequency divided by 4. The value of the INV bit in the TCSR determines whether low-to-high (0 to 1) transitions or high-to-low (1 to 0) transitions increment the counter. If the INV bit is set, high-to-low transitions increment the counter. If the INV bit is cleared, low-to-high transitions increment the counter. When the counter matches the value contained in the TCPR, the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set. If the TRM bit is set, the counter is loaded with the value of the TLR when the next timer clock is received, and the count is resumed. If TRM bit is cleared, the counter continues to be incremented on each timer clock. This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR.
13.4.2
SIGNAL MEASUREMENT MODES
The following signal measurement modes are provided: * * * Measurement input width Measurement input period Measurement capture
MOTOROLA
DSP56367
13-17
Timer/ Event Counter Timer Modes of Operation
These functions are available only on timer 0. 13.4.2.1 Measurement Accuracy The external signal is synchronized with the internal clock used to increment the counter. This synchronization process can cause the number of clocks measured for the selected signal value to vary from the actual signal value by plus or minus one counter clock cycle. 13.4.2.2 Measurement Input Width (Mode 4)
Bit Settings TC3 0 TC2 1 TC1 0 TC0 0 Mode 4 Name Input Width Mode Characteristics Kind Measurement TIO0 Input Clock Internal
In this mode, the timer 0 counts the number of clocks that occur between opposite edges of an input signal. Set the TE bit to clear the counter and enable the timer. Load the timer's count value into the TLR. After the first appropriate transition (as determined by the INV bit) occurs on the TIO0 input pin, the counter is loaded with the TLR value on the first timer clock signal received either from the DSP56367 clock divided by two (CLK/2) or from the prescaler clock input. Each subsequent clock signal increments the counter. If the INV bit is set, the timer starts on the first high-to-low (1 to 0) signal transition on the TIO0 signal. If the INV bit is cleared, the timer starts on the first low-to-high (0 to 1) transition on the TIO0 signal. When the first transition opposite in polarity to the INV bit setting occurs on the TIO0 signal, the counter stops. The TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set. The value of the counter (which measures the width of the TIO0 pulse) is loaded into the TCR. The TCR can be read to determine the external signal pulse width. If the TRM bit is set, the counter is loaded with the TLR value on the first timer clock received following the next valid transition occurring on the TIO0 input pin and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock. This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR.
13-18
DSP56367
MOTOROLA
Timer/ Event Counter Timer Modes of Operation
13.4.2.3
Measurement Input Period (Mode 5)
Bit Settings Mode Characteristics TC0 1 Mode 5 Name Input Period Kind Measurement TIO0 Input Clock Internal
TC3 0
TC2 1
TC1 0
In this mode, the timer counts the period between the reception of signal edges of the same polarity across the TIO0 signal. Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the TLR. The value of the INV bit determines whether the period is measured between consecutive low-to-high (0 to 1) transitions of TIO0 or between consecutive high-to-low (1 to 0) transitions of TIO0. If INV is set, high-to-low signal transitions are selected. If INV is cleared, low-to-high signal transitions are selected. After the first appropriate transition occurs on the TIO0 input pin, the counter is loaded with the TLR value on the first timer clock signal received from either the DSP56367 clock divided by two (CLK/2) or the prescaler clock output. Each subsequent clock signal increments the counter. On the next signal transition of the same polarity that occurs on TIO0, the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set. The contents of the counter are loaded into the TCR. The TCR then contains the value of the time that elapsed between the two signal transitions on the TIO0 signal. After the second signal transition, if the TRM bit is set, the TE bit is set to clear the counter and enable the timer. The counter is repeatedly loaded and incremented until the timer is disabled. If the TRM bit is cleared, the counter continues to be incremented until it overflows. This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR.
MOTOROLA
DSP56367
13-19
Timer/ Event Counter Timer Modes of Operation
13.4.2.4
Measurement Capture (Mode 6)
Bit Settings Mode Characteristics TC0 0 Mode 6 Name Capture Kind Measurement TIO0 Input Clock Internal
TC3 0
TC2 1
TC1 1
In this mode, the timer counts the number of clocks that elapse between starting the timer and receiving an external signal. Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the TLR. When the first timer clock signal is received, the counter is loaded with the TLR value. The timer clock signal can be taken from either the DSP56367 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal increments the counter. At the first appropriate transition of the external clock detected on the TIO0 signal, the TCF bit in the TCSR is set and, if the TCIE bit is set, a compare interrupt is generated. The counter halts. The contents of the counter are loaded into the TCR. The value of the TCR represents the delay between the setting of the TE bit and the detection of the first clock edge signal on the TIO0 signal. If the INV bit is set, a high-to-low transition signals the end of the timing period. If INV is cleared, a low-to-high transition signals the end of the timing period. If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents can be read at any time by reading the TCR.
13-20
DSP56367
MOTOROLA
Timer/ Event Counter Timer Modes of Operation
13.4.3
PULSE WIDTH MODULATION (PWM, MODE 7)
Bit Settings TC3 0 TC2 1 TC1 1 TC0 1 Mode 7 Name
Mode Characteristics Kind PWM TIO0 Output Clock Internal
Pulse Width Modulation
In this mode, the timer generates periodic pulses of a preset width. This function is available only on timer 0. Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the TPCR. When first timer clock is received from either the DSP56367 internal clock divided by two (CLK/2) or the prescaler clock output, the counter is loaded with the TLR value. Each subsequent timer clock increments the counter. When the counter equals the value in the TCPR, the TIO0 output pin is toggled and the TCF bit in the TCSR is set. The contents of the counter are placed into the TCR. If the TCIE bit is set, a compare interrupt is generated. The counter continues to be incremented on each timer clock. If counter overflow has occurred, the TIO0 output pin is toggled, the TOF bit in TCSR is set, and an overflow interrupt is generated if the TOIE bit is set. If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock. This process is repeated until the timer is disabled by clearing the TE bit. TIO0 signal polarity is determined by the value of the INV bit. When the counter is started by setting the TE bit, the TIO0 signal assumes the value of the INV bit. On each subsequent toggling of the TIO0 signal, the polarity of the TIO0 signal is reversed. For example, if the INV bit is set, the TIO0 signal generates the following signal: 1010. If the INV bit is cleared, the TIO0 signal generates the following signal: 0101. The counter contents can be read at any time by reading the TCR. The value of the TLR determines the output period ($FFFFFF - TLR + 1). The timer counter increments the initial TLR value and toggles the TIO0 signal when the counter value exceeds $FFFFFF. The duty cycle of the TIO0 signal is determined by the value in the TCPR. When the value in the TLR is incremented to a value equal to the value in the TCPR, the TIO0 signal is toggled.
MOTOROLA
DSP56367
13-21
Timer/ Event Counter Timer Modes of Operation
The duty cycle is equal to ($FFFFFF - TCPR) divided by ($FFFFFF - TLR + 1). For a 50% duty cycle, the value of TCPR is equal to ($FFFFFF + TLR + 1) / 2. Note: The value in TCPR must be greater than the value in TLR.
13.4.4
13.4.4.1
WATCHDOG MODES
Watchdog Pulse (Mode 9)
Bit Settings Mode Characteristics TC0 1 Mode 9 Name Pulse Kind Watchdog TIO0 Output Clock Internal
TC3 1
TC2 0
TC1 0
In this mode, the timer generates an interrupt at a preset rate. Timer 0 also generates pulse on TIO0. The signal period is equal to the period of one timer clock. Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the TCPR. The counter is loaded with the TLR value on the first timer clock received from either the DSP56367 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer clock increments the counter. When the counter matches the value of the TCPR, the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is also set. If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each subsequent timer clock. This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. Timer 0 also generates an output pulse on the TIO0 signal with a pulse width equal to the timer clock period. The pulse polarity is determined by the value of the INV bit. If the INV bit is set, the pulse polarity is high (logical 1). If the INV bit is cleared, the pulse polarity is low (logical 0). The counter contents can be read at any time by reading the TCR. The counter is reloaded whenever the TLR is written with a new value while the TE bit is set.
13-22
DSP56367
MOTOROLA
Timer/ Event Counter Timer Modes of Operation
Note:
In this mode, internal logic preserves the TIO0 value and direction for an additional 2.5 internal clock cycles after the DSP56367 hardware RESET signal is asserted. This ensures that a valid RESET signal is generated when the TIO0 signal is used to reset the DSP56367. Watchdog Toggle (Mode 10)
Bit Settings Mode Characteristics TC0 0 Mode 10 NAME Toggle Kind Watchdog TIO0 Output Clock Internal
13.4.4.2
TC3 1
TC2 0
TC1 1
In this mode, the timer generates an interrupt at a preset rate. Timer 0 also toggles the output on TIO0. Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the TPCR. The counter is loaded with the TLR value on the first timer clock received from either the DSP56367 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer clock increments the counter. The TIO0 signal is set to the value of the INV bit. When the counter equals the value in the TCPR, the TCF bit in the TCSR is set, and a compare interrupt is generated if the TCIE bit is also set. If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each subsequent timer clock When counter overflow has occurred, the polarity of the TIO0 output pin is inverted, the TOF bit in the TCSR is set, and an overflow interrupt is generated if the TOIE bit is also set. The TIO0 polarity is determined by the INV bit. The counter is reloaded whenever the TLR is written with a new value while the TE bit is set. This process is repeated until the timer is disabled by clearing the TE bit. The counter contents can be read at any time by reading the TCR register. Note: In this mode, internal logic preserves the TIO0 value and direction for an additional 2.5 internal clock cycles after the DSP56367 hardware RESET signal is asserted. This ensures that a valid RESET signal is generated when the TIO0 signal is used to reset the DSP56367.
MOTOROLA
DSP56367
13-23
Timer/ Event Counter Timer Modes of Operation
13.4.5
RESERVED MODES
Modes 8, 11, 12, 13, 14, and 15 are reserved.
13.4.6
SPECIAL CASES
The following special cases apply during wait and stop state. 13.4.6.1 Timer Behavior during Wait Timer clocks are active during the execution of the WAIT instruction and timer activity is undisturbed. If a timer interrupt is generated, the DSP56367 leaves the wait state and services the interrupt. 13.4.6.2 Timer Behavior during Stop During the execution of the STOP instruction, the timer clocks are disabled, timer activity is stopped, and the TIO0 signal is disconnected. Any external changes that happen to the TIO0 signal is ignored when the DSP56367 is the stop state. To ensure correct operation, the timers should be disabled before the DSP56367 is placed into the stop state.
13.4.7
DMA TRIGGER
Each timer can also be used to trigger DMA transfers. For this to occur, a DMA channel must be programmed to be triggered by a timer event. The timer issues a DMA trigger on every event in all modes of operation. The DMA channel does not have the capability to save multiple DMA triggers generated by the timer. To ensure that all DMA triggers are serviced, the user must provide for the preceding DMA trigger to be serviced before the next trigger is received by the DMA channel.
13-24
DSP56367
MOTOROLA
SECTION PACKAGING
14.1
14
PIN-OUT AND PACKAGE INFORMATION
This section provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated for the package. The DSP56367 is available in a 144-pin LQFP package. Table 14-1and Table 14-2 show the pin/name assignments for the packages.
14.1.1
LQFP PACKAGE DESCRIPTION
Top view of the 144-pin LQFP package is shown in Figure 14-1 with its pin-outs. The package drawing is shown in Figure 14-2.
MOTOROLA
DSP56367
14-1
Packaging Pin-out and Package Information
SCK/SCL SS#/HA2 HREQ# SDO0/SDO0_1 SDO1/SDO1_1 SDO2/SDI3/SDO2_1/SDI3_1 SDO3/SDI2/SDO3_1/SDI2_1 VCCS GNDS SDO4/SDI1 SDO5/SDI0 FST FSR SCKT SCKR HCKT HCKR VCCQL GNDQ VCCQH HDS/HWR HRW/HRD HACK/HRRQ HOREQ/HTRQ VCCS GNDS ADO ACI TIO0 HCS/HA10 HA9/HA2 HA8/HA1 HAS/HA0 HAD7 HAD6 HAD5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 38 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
MISO/SDA MOSI/HA0 TMS TCK TDI TDO SDO4_1/SDI1_1 MODA/IRQA# MODB/IRQB# MODCIRQC# MODD/IRQD# D23 D22 D21 GNDD VCCD D20 GNDQ VCCQL D19 D18 D17 D16 D15 GNDD VCCD D14 D13 D12 D11 D10 D9 GNDD VCCD D8 D7
D6 D5 D4 D3 GNDD VCCD D2 D1 D0 A17 A16 A15 GNDA VCCQH A14 A13 A12 VCCQL GNDQ A11 A10 GNDA VCCA A9 A8 A7 A6 GNDA VCCA A5 A4 A3 A2 GNDA VCCA A1
14-2
HAD4 VCCH GNDH HAD3 HAD2 HAD1 HAD0 RESET# VCCP PCAP GNDP SDO5_1/SDI0_1 VCCQH FST_1 AA2 CAS# SCKT_1 GNDQ EXTAL VCCQL VCCC GNDC FSR_1 SCKR_1 PINIT/NMI# TA# BR# BB# VCCC GNDC WR# RD# AA1 AA0 BG# A0
Figure 14-1 144-pin package
DSP56367
MOTOROLA
Packaging Pin-out and Package Information
Table 14-1 Signal Identification by Name
Signal Name
A0 A1 A2
Pin No.
72 73 76 D9
Signal Name
Pin No.
113 114 115
Signal Name
GNDS GNDS HA8/HA1
Pin No.
9 26 32
Signal Name
SDO0/SDO0_1 SDO1/SDO1_1 SDO2/SDI3/SDO2_1 /SDI3_1 SDO3/SDI2/SDO3_1 /SDI2_1 SDO4/SDI1 SDO4_1/SDI1_1 SDO5/SDI0 SDO5_1/SDI0_1 SS#/HA2 TA# TCK TDI TDO TIO0 TMS VCCA VCCA VCCA VCCC VCCC VCCD VCCD VCCD VCCD VCCH VCCQH VCCQH
Pin No.
4 5 6
D10 D11
A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 AA0 AA1 AA2 ACI ADO BB# BG# BR# CAS#
77 78 79 82 83 84 85 88 89 92 93 94 97 98 99 70 69 51 28 27 64 71 63 52
D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 EXTAL FSR FSR_1 FST FST_1 GNDA GNDA GNDA GNDA GNDC GNDC GNDD
116 117 118 121 122 123 124 125 128 131 132 133 55 13 59 12 50 75 81 87 96 58 66 104
HA9/HA2 HACK/HRRQ HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAS/HA0 HCKR HCKT HCS/HA10 HDS/HWR HOREQ/HTRQ HREQ# HRW/HRD MODA/IRQA# MODB/IRQB# MODC/IRQC# MODD/IRQD# MISO/SDA MOSI/HA0
31 23 43 42 41 40 37 36 35 34 33 17 16 30 21 24 3 22 137 136 135 134 144 143
7 10 138 11 48 2 62 141 140 139 29 142 74 80 86 57 65 103 111 119 129 38 20 95
MOTOROLA
DSP56367
14-3
Packaging Pin-out and Package Information
Table 14-1 Signal Identification by Name (Continued)
Signal Name
D0 D1 D2 D3 D4 D5 D6 D7 D8
Pin No.
100 101 102 105 106 107 108 109 110
Signal Name
GNDD GNDD GNDD GNDH GNDP GNDQ GNDQ GNDQ GNDQ
Pin No.
112 120 130 39 47 19 54 90 127
Signal Name
PCAP PINIT/NMI# RD# RESET# SCK/SCL SCKR SCKR_1 SCKT SCKT_1
Pin No.
46 61 68 44 1 15 60 14 53
Signal Name
VCCQH VCCQL VCCQL VCCQL VCCQL VCCP VCCS VCCS WR#
Pin No.
49 18 56 91 126 45 8 25 67
14-4
DSP56367
MOTOROLA
Packaging Pin-out and Package Information
Table 14-2
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Signal Identification by Pin Number
Signal Name Pin No.
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 A1 VCCA GNDA A2 A3 A4 A5 VCCA GNDA A6 A7 A8 A9 VCCA GNDA A10 A11 GNDQ VCCQL A12 A13 A14 VCCQH GNDA A15 A16 A17 D0 D1 D2 VCCD GNDD D3 D4
Signal Name
SCK/SCL SS#/HA2 HREQ# SDO0/SDO0_1 SDO1/SDO1_1 SDO2/SDI3/SDO2_1/SD I3_1 SDO3/SDI2/SDO3_1/SD I2_1 VCCS GNDS SDO4/SDI1 SDO5/SDI0 FST FSR SCKT SCKR HCKT HCKR VCCQL GNDQ VCCQH HDS/HWR HRW/HRD HACK/HRRQ HOREQ/HTRQ VCCS GNDS ADO ACI TIO0 HCS/HA10 HA9/HA2 HA8/HA1 HAS/HA0 HAD7
Pin No.
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
Signal Name
Pin No.
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 D7 D8
Signal Name
HAD4 VCCH GNDH HAD3 HAD2 HAD1 HAD0 RESET# VCCP PCAP GNDP SDO5_1/SDI0_1 VCCQH FST_1 AA2 CAS# SCKT_1 GNDQ EXTAL VCCQL VCCC GNDC FSR_1 SCKR_1 PINIT/NMI# TA# BR# BB# VCCC GNDC WR# RD# AA1 AA0
VCCD GNDD D9 D10 D11 D12 D13 D14 VCCD GNDD D15 D16 D17 D18 D19 VCCQL GNDQ D20 VCCD GNDD D21 D22 D23 MODD/IRQD# MODC/IRQC# MODB/IRQB# MODA/IRQA# SDO4_1/SDI1_1 TDO TDI TCK TMS
MOTOROLA
DSP56367
14-5
Packaging Pin-out and Package Information
Table 14-2
35 36 HAD6 HAD5
Signal Identification by Pin Number (Continued)
71 72 BG# A0 107 108 D5 D6 143 144 MOSI/HA0 MISO/SDA
14-6
DSP56367
MOTOROLA
Packaging Pin-out and Package Information
14.1.2
LQFP PACKAGE MECHANICAL DRAWING
Figure 14-2 DSP56367 144-pin LQFP Package (1 of 3)
MOTOROLA
DSP56367
14-7
Packaging Pin-out and Package Information
Figure 14-3 DSP56367 144-pin LQFP Package (2 of 3)
14-8
DSP56367
MOTOROLA
Packaging Pin-out and Package Information
Figure 14-4 DSP56367 144-pin LQFP Package (3 of 3)
MOTOROLA
DSP56367
14-9
Packaging Ordering Drawings
14.2
ORDERING DRAWINGS
The detailed package drawing is available on the Motorola web page at: http://www.mot-sps.com/cgi-bin/cases.pl Use package 918-03 for the search.
14-10
DSP56367
MOTOROLA
APPENDIX
A
BOOTSTRAP ROM CONTENTS
A.1 DSP56367 BOOTSTRAP PROGRAM
; BOOTSTRAP CODE FOR DSP56367 Rev. 0 silicon ; (C) Copyright 1999, 2000, 2001 Motorola Inc. ; ; ; Revision 0.0 1999/JAN/26 - Modified from 56362_RevA_regular_boot_rev01.asm: ; - Change the length of xram and the length of yram ; in burn-in code ; - Change the address of the reserved area in the ; Program ROM to $FFAF80 - $FFAFFF ; ; Revision 0.1 1999/MAR/29 - Enabled 100ns I2C filter in bootstrap ; mode 0110. ; - Added 5 NOP instructions after OnCE enable. ; ; This is the Bootstrap program contained in the DSP56367 192-word Boot ; ROM. This program can load any program RAM segment from an external ; EPROM, from the Host Interface or from the SHI serial interface. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=x000, then the Boot ROM is bypassed and the DSP56367 ; will start fetching instructions beginning with address $C00000 (MD=0) ; or $008000 (MD=1) assuming that an external memory of SRAM type is ; used. The accesses will be performed using 31 wait states with no ; address attributes selected (default area). ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=0001, then it loads a program RAM segment from consecutive ; byte-wide P memory locations, starting at P:$D00000 (bits 7-0). ; The memory is selected by the Address Attribute AA1 and is accessed with ; 31 wait states. ; The EPROM bootstrap code expects to read 3 bytes ; specifying the number of program words, 3 bytes specifying the address ; to start loading the program words and then 3 bytes for each program ; word to be loaded. The number of words, the starting address and the ; program words are read least significant byte first followed by the ; mid and then by the most significant byte. ; The program words will be condensed into 24-bit words and stored in ; contiguous PRAM memory locations starting at the specified starting address. ; After reading the program words, program execution starts from the same
MOTOROLA
DSP56367
A-1
Bootstrap ROM Contents
; address where loading started. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=0010, then the bootstrap code jumps to the internal ; Program ROM, without loading the Program RAM. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Operation mode MD:MC:MB:MA=0011 is reserved. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=01xx, then the Program RAM is loaded from the SHI. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Operation mode MD:MC:MB:MA=1001 is used for burn-in testing. ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Operation mode MD:MC:MB:MA=1010 is reserved ; Operation mode MD:MC:MB:MA=1011 is reserved ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=1100, then it loads the program RAM from the Host ; Interface programmed to operate in the ISA mode. ; The HOST ISA bootstrap code expects to read a 24-bit word ; specifying the number of program words, a 24-bit word specifying the address ; to start loading the program words and then a 24-bit word for each program ; word to be loaded. The program words will be stored in ; contiguous PRAM memory locations starting at the specified starting address. ; After reading the program words, program execution starts from the same ; address where loading started. ; The Host Interface bootstrap load program may be stopped by ; setting the Host Flag 0 (HF0). This will start execution of the loaded ; program from the specified starting address. ; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=1101, then it loads the program RAM from the Host ; Interface programmed to operate in the HC11 non multiplexed mode. ; ; The HOST HC11 bootstrap code expects to read a 24-bit word ; specifying the number of program words, a 24-bit word specifying the address ; to start loading the program words and then a 24-bit word for each program ; word to be loaded. The program words will be stored in ; contiguous PRAM memory locations starting at the specified starting address. ; After reading the program words, program execution starts from the same ; address where loading started. ; The Host Interface bootstrap load program may be stopped by ; setting the Host Flag 0 (HF0). This will start execution of the loaded ; program from the specified starting address.
A-2
DSP56367
MOTOROLA
Bootstrap ROM Contents
; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=1110, then it loads the program RAM from the Host ; Interface programmed to operate in the 8051 multiplexed bus mode, ; in double-strob pin configuration. ; The HOST 8051 bootstrap code expects accesses that are byte wide. ; The HOST 8051 bootstrap code expects to read 3 bytes forming a 24-bit word ; specifying the number of program words, 3 bytes forming a 24-bit word ; specifying the address to start loading the program words and then 3 bytes ; forming 24-bit words for each program word to be loaded. ; The program words will be stored in contiguous PRAM memory locations ; starting at the specified starting address. ; After reading the program words, program execution starts from the same ; address where loading started. ; The Host Interface bootstrap load program may be stopped by setting the ; Host Flag 0 (HF0). This will start execution of the loaded program from ; the specified starting address. ; ; The base address of the HDI08 in multiplexed mode is 0x80 and is not ; modified by the bootstrap code. All the address lines are enabled ; and should be connected accordingly. ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; If MD:MC:MB:MA=1111, then it loads the program RAM from the Host ; Interface programmed to operate in the MC68302 (IMP) bus mode, ; in single-strob pin configuration. ; The HOST MC68302 bootstrap code expects accesses that are byte wide. ; The HOST MC68302 bootstrap code expects to read 3 bytes forming a 24-bit word ; specifying the number of program words, 3 bytes forming a 24-bit word ; specifying the address to start loading the program words and then 3 bytes ; forming 24-bit words for each program word to be loaded. ; The program words will be stored in contiguous PRAM memory locations ; starting at the specified starting address. ; After reading the program words, program execution starts from the same ; address where loading started. ; The Host Interface bootstrap load program may be stopped by setting the ; Host Flag 0 (HF0). This will start execution of the loaded program from ; the specified starting address. ; page opt 132,55,0,0,0 cex,mex,mu
;; ;;;;;;;;;;;;;;;;;;;; GENERAL EQUATES ;;;;;;;;;;;;;;;;;;;;;;;; ;; BOOT equ $D00000 ; this is the location in P memory ; on the external memory bus ; where the external byte-wide ; EPROM is located AARV equ $D00409 ; AAR1 selects the EPROM as CE~
MOTOROLA
DSP56367
A-3
Bootstrap ROM Contents
PROMADDR equ MA MB MC MD EQU EQU EQU EQU
$FF1000 0 1 2 3
; mapped as P from $D00000 to ; $DFFFFF, active low ; Starting PROM address
;; ;;;;;;;;;;;;;;;;;;;; DSP I/O REGISTERS ;;;;;;;;;;;;;;;;;;;;;;;; ;; M_AAR1 M_OGDB M_HPCR M_HSR M_HORX HRDF HF0 HEN M_HRX M_HCSR M_HCKR HRNE HI2C HCKFR HFM0 HFM1 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $FFFFF8 $FFFFFC $FFFFC4 $FFFFC3 $FFFFC6 $0 $3 $6 $FFFF94 $FFFF91 $FFFF90 17 1 4 12 13 ; Address Attribute Register 1 ; OnCE GDB Register ; ; ; ; ; ; ; ; ; ; ; ; ; ; Host Host Host Host Host Host SHI SHI SHI SHI SHI SHI SHI SHI Polarity Control Register Status Register Receive Register Receive Data Full Flag 0 Enable
Receive FIFO Control/Status Register Clock Control Register FIFO Not Empty flag I2C Enable Control Bit I2C Clock Freeze Control Bit I2C Filter Mode Bit 0 I2C Filter Mode Bit 1
ORG PL:$ff0000,PL:$ff0000 START movep #$0,X:M_OGDB nop nop nop nop nop clr a #$0,r5 jset #MD,omr,OMR1XXX jset #MC,omr,SHILD jclr #MB,omr,EPROMLD jset #MA,omr,RESERVED
; bootstrap code starts at $ff0000
; enable OnCE ; 5 NOP instructions, needed for test procedure
; ; ; ; ;
clear a and init R5 with 0 If MD:MC:MB:MA=1xxx go to OMR1XXX If MD:MC:MB:MA=01xx, go load from SHI If MD:MC:MB:MA=0001, go load from EPROM If MD:MC:MB:MA=0011, go to RESERVED
;======================================================================== ; This is the routine that jumps to the internal Program ROM. ; MD:MC:MB:MA=0010
A-4
DSP56367
MOTOROLA
Bootstrap ROM Contents
move #PROMADDR,r1 bra ; store starting PROM address in r1
;======================================================================== ; This is the routine that loads from SHI. ; MD:MC:MB:MA=0100 - reserved for SHI ; MD:MC:MB:MA=0101 - Bootstrap from SHI (SPI slave) ; MD:MC:MB:MA=0110 - Bootstrap from SHI (I2C slave, HCKFR=1,100ns filter) ; MD:MC:MB:MA=0111 - Bootstrap from SHI (I2C slave, HCKFR=0) SHILD ; ; ; ; ; ; ; ; ; ; ; ; ; ; This is the routine which loads a program through the SHI port. The SHI operates in the slave mode, with the 10-word FIFO enabled, and with the HREQ pin enabled for receive operation. The word size for transfer is 24 bits. The SHI operates in the SPI or in the I2C mode, according to the bootstrap mode. The program is downloaded according to the following rules: 1) 3 bytes - Define the program length. 2) 3 bytes - Define the address to which to start loading the program to. 3) 3n bytes (while n is the program length defined by the first 3 bytes) The program words will be stored in contiguous PRAM memory locations starting at the specified starting address. After storing the program words, program execution starts from the same address where loading started. move #$A9,r1 ; prepare SHI control value in r1
; HEN=1, HI2C=0, HM1-HM0=10, HCKFR=0, HFIFO=1, HMST=0, ; HRQE1-HRQE0=01, HIDLE=0, HBIE=0, HTIE=0, HRIE1-HRIE0=00 jclr jclr bset shi_loop movep jclr movep jclr movep move do jclr movep nop _LOOP2 #MA,omr,SHI_CF #MB,omr,shi_loop #HI2C,r1 r1,x:M_HCSR #HRNE,x:M_HCSR,* x:M_HRX,a0 #HRNE,x:M_HCSR,* x:M_HRX,r0 r0,r1 a0,_LOOP2 #HRNE,x:M_HCSR,* x:M_HRX,p:(r0)+ ; If MD:MC:MB:MA=01x0, go to SHI clock freeze ; If MD:MC:MB:MA=0101, select SPI mode ; otherwise select I2C mode. ; enable SHI ; wait for no. of words
; wait for starting address
; wait for HRX not empty ; store in Program RAM ; req. because of restriction
MOTOROLA
DSP56367
A-5
Bootstrap ROM Contents
bra SHI_CF bset bset bset bset jset bra
#HI2C,r1 #HCKFR,r1 #HFM0,x:M_HCKR #HFM1,x:M_HCKR #MB,omr,shi_loop ; ; ; ; ; ;
select I2C mode. enable clock freeze in I2C mode. enable 100ns noise filter enable 100ns noise filter If MD:MC:MB:MA=0110, go to I2C load If MD:MC:MB:MA=0100, go to reserved
;======================================================================== ; This is the routine that loads from external EPROM. ; MD:MC:MB:MA=0001 EPROMLD move #BOOT,r2 movep #AARV,X:M_AAR1 do #6,_LOOP9 movem p:(r2)+,a2 asr #8,a,a _LOOP9 move a1,r0 move a1,r1 do a0,_LOOP10 do #3,_LOOP11 movem p:(r2)+,a2 asr #8,a,a _LOOP11 movem a1,p:(r0)+ nop _LOOP10 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; r2 = address of external EPROM aar1 configured for SRAM types of access read number of words and starting address Get the 8 LSB from ext. P mem. Shift 8 bit data into A1 starting address for load save it in r1 a0 holds the number of words read program words Each instruction has 3 bytes Get the 8 LSB from ext. P mem. Shift 8 bit data into A1 Go get another byte. Store 24-bit result in P mem. pipeline delay and go get another 24-bit word. Boot from EPROM done
bra
OMR1XXX ; ; jclr #MB,omr,OMR1IS0 ; jclr #MA,omr,I8051HOSTLD ; ; jclr #MC,omr,BURN_RESER IF IF IF If If MD:MC:MB:MA=101x, MD:MC:MB:MA=1001, MD:MC:MB:MA=110x, MD:MC:MB:MA=1110, MD:MC:MB:MA=1111, go go go go go to RESERVED to BURN to look for ISA/HC11 load from 8051 Host load from MC68302 Host
;======================================================================== ; This is the routine which loads a program through the HDI08 host port ; The program is downloaded from the host MCU with the following rules: ; 1) 3 bytes - Define the program length. ; 2) 3 bytes - Define the address to which to start loading the program to.
A-6
DSP56367
MOTOROLA
Bootstrap ROM Contents
; 3) 3n bytes (while n is the program length defined by the 3 first bytes) ; The program words will be stored in contiguous PRAM memory locations starting ; at the specified starting address. ; After reading the program words, program execution starts from the same ; address where loading started. ; The host MCU may terminate the loading process by setting the HF1=0 and HF0=1. ; When the downloading is terminated, the program will start execution of the ; loaded program from the specified starting address. ; The HDI08 boot ROM program enables the following busses to download programs ; through the HDI08 port: ; ; C - ISA - Dual strobes non-multiplexed bus with negative strobe ; pulses dual positive request ; D - HC11 - Single strobe non-multiplexed bus with positive strobe ; pulse single negative request. ; E - i8051 - Dual strobes multiplexed bus with negative strobe pulses ; dual negative request. ; F - MC68302 - Single strobe non-multiplexed bus with negative strobe ; pulse single negative request. ;======================================================================== MC68302HOSTLD movep #%0000000000111000,x:M_HPCR ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; bra OMR1IS0 jset #MA,omr,HC11HOSTLD ; If MD:MC:MB:MA=1101, go load from HC11 Host HA8EN = 0 HGEN =0
MOTOROLA
DSP56367
A-7
Bootstrap ROM Contents
; If MD:MC:MB:MA=1100, go load from ISA HOST ISAHOSTLD movep #%0101000000011000,x:M_HPCR ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; bra HC11HOSTLD movep #%0000001000011000,x:M_HPCR ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Configure HAP =0 HRP =0 HCSP = 0 HDDS = 0 HMUX = 0 HASP = 0 HDSP = 1 HROD = 0 spare = 0 HEN HAEN HREN HCSEN HA9EN =0 = = = = 0 1 1 0 the following conditions: Negative host acknowledge Negative host request Negatice chip select input Single strobe bus (R/W~ and DS) Non multiplexed bus (address strobe polarity has no meaning in non-multiplexed bus) Negative data stobes polarity Host request is active when enabled This bit should be set to 0 for future compatability When the HPCR register is modified HEN should be cleared Host acknowledge is disabled Host requests are enabled Host chip select input enabled (address 9 enable bit has no HA8EN = 0 HGEN =0
A-8
DSP56367
MOTOROLA
Bootstrap ROM Contents
; meaning in non-multiplexed bus) ; HA8EN = 0 (address 8 enable bit has no ; meaning in non-multiplexed bus) ; HGEN = 0 Host GPIO pins are disabled bra I8051HOSTLD movep #%0001110000011110,x:M_HPCR ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; HDI08CONT bset jclr #HEN,x:M_HPCR #HRDF,x:M_HSR,* ; ; ; ; Enable the HDI08 to operate as host interface (set HEN=1) wait for the program length to be written Configure HAP =0 HRP =0 HCSP = 0 HDDS = 1 HMUX = 1 HASP = 1 HDSP = 0 HROD = 0 spare = 0 HEN HAEN HREN HCSEN HA9EN HA8EN HGEN =0 = = = = = = 0 1 1 1 1 0 the following conditions: Negative host acknowledge Negatice host request Negatice chip select input Dual strobes bus (RD and WR) Multiplexed bus Positive address strobe polarity Negative data stobes polarity Host request is active when enabled This bit should be set to 0 for future compatability When the HPCR register is modified HEN should be cleared Host acknowledge is disabled Host requests are enabled Host chip select input enabled Enable address 9 input Enable address 8 input Host GPIO pins are disabled movep jclr
x:M_HORX,a0 #HRDF,x:M_HSR,* ; wait for the program starting address ; to be written
movep move do HDI08LL jset jclr
x:M_HORX,r0 r0,r1 a0,HDI08LOOP ; set a loop with the downloaded length
#HRDF,x:M_HSR,HDI08NW #HF0,x:M_HSR,HDI08LL
; If new word was loaded then jump to ; read that word ; If HF0=0 then continue with the
MOTOROLA
DSP56367
A-9
Bootstrap ROM Contents
enddo bra HDI08NW movep nop HDI08LOOP x:M_HORX,p:(r0)+ ; downloading ; Must terminate the do loop
; Move the new word into its destination ; location in the program RAM ; pipeline delay
;======================================================================== ; This is the exit handler that returns execution to normal ; expanded mode and jumps to the RESET vector. FINISH andi #$0,ccr jmp (r1) ; Clear CCR as if RESET to 0. ; Then go to starting Prog addr.
;======================================================================== ; MD:MC:MB:MA=1001 is used for Burn-in code BURN_RESER jclr #MB,omr,BURN ; IF MD:MC:MB:MA=1001, go to BURN
;======================================================================== ; The following modes are reserved, some of which are used for internal testing ; MD:MC:MB:MA=0011 is reserved ; MD:MC:MB:MA=1010 is reserved ; MD:MC:MB:MA=1011 is reserved RESERVED bra <*
;======================================================================== ; Code for burn-in ;======================================================================== M_PCRC M_PDRC M_PRRC SCKT EQU EQU EQU EQU $FFFFBF $FFFFBD $FFFFBE $3 ;; ;; ;; ;; Port Port Port SCKT C GPIO Control Register C GPIO Data Register C Direction Register is GPIO bit #3 in ESAI (Port C)
EQUALDATA
equ
0
;; 1 if xram and yram are of equal ;; size and addresses, 0 otherwise.
if
(EQUALDATA)
A-10
DSP56367
MOTOROLA
Bootstrap ROM Contents
start_dram length_dram else start_xram length_xram start_yram length_yram endif start_pram length_pram
equ equ equ equ equ equ
0 $1600 0 $3400 0 $1c00
;; ;; same addresses ;; 13k XRAM ;; 7k YRAM
equ equ
0 $C00
;; 3k PRAM
BURN ;; get PATTERN pointer clr b #PATTERNS,r6 move #<(NUM_PATTERNS-1),m6 ;; b is the error accumulator ;; program runs forever in ;; cyclic form
;; configure SCKT as gpio output. movep b,x:M_PDRC ;; clear GPIO data register bclr #SCKT,x:M_PCRC ;; Define SCKT as output GPIO pin bset #SCKT,x:M_PRRC ;; SCKT toggles means test pass
lua burnin_loop
(r5)-,r7
;; r5 = test fail flag = $000000 ;; r7 = test pass flag = $FFFFFF
do #9,burn1 ;;---------------------------;; test RAM ;; each pass checks 1 pattern ;;---------------------------move p:(r6)+,x1 move p:(r6)+,x0 move p:(r6)+,y0
;; pattern for x memory ;; pattern for y memory ;; pattern for p memory
;; write pattern to all memory locations if (EQUALDATA) ;; write x and y memory clr a #start_dram,r0 move #>length_dram,n0 rep n0 mac x0,x1,a x,l:(r0)+ ;; x/y ram symmetrical ;; start of x/y ram ;; length of x/y ram ;; exercise mac, write x/y ram ;; x/y ram not symmetrical ;; write x memory clr a #start_xram,r0 move #>length_xram,n0 rep n0 mac x0,y0,a x1,x:(r0)+
else
;; start of xram ;; length of xram ;; exercise mac, write xram
MOTOROLA
DSP56367
A-11
Bootstrap ROM Contents
;; write y memory clr a #start_yram,r1 move #>length_yram,n1 rep n1 mac x1,y0,a x0,y:(r1)+ endif ;; write p memory clr a #start_pram,r2 move #>length_pram,n2 rep n2 move y0,p:(r2)+ ;; check memory contents if (EQUALDATA) ;; check dram clr a #start_dram,r0 do n0,_loopd move x:(r0),a1 eor x1,a add a,b move y:(r0)+,a1 eor x0,a add a,b _loopd else ;; check xram clr a #start_xram,r0 do n0,_loopx move x:(r0)+,a1 eor x1,a add a,b _loopx ;; check yram clr a #start_yram,r1 do n1,_loopy move y:(r1)+,a1 eor x0,a add a,b _loopy endif ;; check pram clr a #start_pram,r2 do n2,_loopp
;; start of yram ;; length of yram ;; exercise mac, write yram
;; start of pram ;; length of pram ;; write pram
;; x/y ram symmetrical
;; restore pointer, clear a ;; a0=a2=0 ;; accumulate error in b ;; a0=a2=0 ;; accumulate error in b
;; x/y ram not symmetrical
;; restore pointer, clear a ;; a0=a2=0 ;; accumulate error in b
;; restore pointer, clear a ;; a0=a2=0 ;; accumulate error in b
;; restore pointer, clear a
A-12
DSP56367
MOTOROLA
Bootstrap ROM Contents
move eor add _loopp
p:(r2)+,a1 y0,a a,b
;; a0=a2=0 ;; accumulate error in b
;;--------------------------------------------------;; toggle pin if no errors, stop execution otherwise. ;;--------------------------------------------------;; if error tne r5,r7 ;; r7=$FFFFFF as long as test pass ;; condition codes preserved ;; this instr can be removed in case of shortage movep r7,x:M_OGDB ;; write pass/fail flag to OnCE ;; condition codes preserved ;; this instr can be removed in case of
shortage beq bclr enddo shortage bra label1 bchg burn1 debug shortage wait disabled) BURN_END ;; enter wait otherwise (OnCE port #SCKT,x:M_PDRC PATTERNS
ORG PL:,PL: dsm 4 ORG PL:BURN_END,PL:BURN_END
;; align for correct modulo addressing
dup PATTERNS-* location dc * endm
; write address in unused Boot ROM
ORG dc dc dc dc
PL:PATTERNS,PL:PATTERNS ;; Each value is written to all memories $555555 $AAAAAA $333333 $F0F0F0
MOTOROLA
DSP56367
A-13
Bootstrap ROM Contents
NUM_PATTERNS
equ
*-PATTERNS
;======================================================================== ; This code fills the unused bootstrap rom locations with their address dup $FF00C0-* dc * endm
;======================================================================== ; Reserved Area in the Program ROM: upper 128 words. ; Address range: $FFAF80 - $FFAFFF ;========================================================================
ORG PL:$FFAF80,PL:$FFAF80 ; This code fills the unused rom locations with their address dup $FFB000-$14-* dc * endm ; Code segment for testing of ROM Patch ; This code segment is located in the uppermost addresses of the Program ROM ORG PL:$FFB000-$14,PL:$FFB000-$14 move move move move move move move move move move move move move move move move move move move #$80000,r0 #$0,x0 x0,x:(r0)+ #$1,x0 x0,x:(r0)+ #$2,x0 x0,x:(r0)+ #$3,x0 x0,x:(r0)+ #$4,x0 x0,x:(r0)+ #$5,x0 x0,x:(r0)+ #$6,x0 x0,x:(r0)+ #$7,x0 x0,x:(r0)+ #$8,x0 x0,x:(r0)+
A-14
DSP56367
MOTOROLA
Bootstrap ROM Contents
end
MOTOROLA
DSP56367
A-15
Bootstrap ROM Contents
A-16
DSP56367
MOTOROLA
APPENDIX EQUATES
B
;*********************************************************************************
; ; ;
EQUATES for DSP56367 interrupts Last update: April 24, 2000
;********************************************************************************* page opt intequ if 132,55,0,0,0 mex ident 1,0
@DEF(I_VEC)
;leave user definition as is. else I_VEC equ $0
endif ;-----------------------------------------------------------------------; Non-Maskable interrupts ;-----------------------------------------------------------------------I_RESET I_STACK I_ILL I_IINST I_DBG I_TRAP EQU EQU EQU I_VEC+$00 I_VEC+$02 I_VEC+$04 I_VEC+$04 ; Hardware RESET ; Stack Error ; Illegal Instruction ; Illegal Instruction ; Debug Request ; Trap
EQU EQU EQU
I_VEC+$06 I_VEC+$08
MOTOROLA
DSP56367
B-1
Equates
I_NMI
EQU
I_VEC+$0A
; Non Maskable Interrupt
;-----------------------------------------------------------------------; Interrupt Request Pins ;-----------------------------------------------------------------------I_IRQA I_IRQB I_IRQC I_IRQD EQU EQU EQU EQU I_VEC+$10 I_VEC+$12 I_VEC+$14 I_VEC+$16 ; IRQA ; IRQB ; IRQC ; IRQD
;-----------------------------------------------------------------------; DMA Interrupts ;-----------------------------------------------------------------------I_DMA0 I_DMA1 I_DMA2 I_DMA3 I_DMA4 I_DMA5 EQU EQU EQU EQU EQU EQU I_VEC+$18 I_VEC+$1A I_VEC+$1C I_VEC+$1E I_VEC+$20 I_VEC+$22 ; DMA Channel 0 ; DMA Channel 1 ; DMA Channel 2 ; DMA Channel 3 ; DMA Channel 4 ; DMA Channel 5
;-----------------------------------------------------------------------; DAX Interrupts ;-----------------------------------------------------------------------I_DAXTUE I_DAXBLK I_DAXTD EQU EQU EQU I_VEC+$28 I_VEC+$2A ; DAX Underrun Error ; DAX Block Transferred ; DAX Audio Data Empty
I_VEC+$2E
;-----------------------------------------------------------------------; ESAI Interrupts ;------------------------------------------------------------------------
B-2
DSP56367
MOTOROLA
Equates
I_ESAIRD I_ESAIRED I_ESAIRDE I_ESAIRLS I_ESAITD I_ESAITED I_ESAITDE I_ESAITLS
EQU EQU EQU EQU EQU EQU EQU EQU
I_VEC+$30 I_VEC+$32 I_VEC+$34 I_VEC+$36 I_VEC+$38 I_VEC+$3A I_VEC+$3C I_VEC+$3E
; ESAI Receive Data ; ESAI Receive Even Data ; ESAI Receive Data With Exception Status ; ESAI Receive Last Slot ; ESAI Transmit Data ; ESAI Transmit Even Data ; ESAI Transmit Data With Exception Status ; ESAI Transmit Last Slot
;-----------------------------------------------------------------------; SHI Interrupts ;-----------------------------------------------------------------------I_SHITD I_SHITUE I_SHIRNE I_SHIRFF I_SHIROE I_SHIBER EQU EQU EQU EQU EQU EQU I_VEC+$40 I_VEC+$42 I_VEC+$44 I_VEC+$48 I_VEC+$4A I_VEC+$4C ; SHI Transmit Data ; SHI Transmit Underrun Error ; SHI Receive FIFO Not Empty ; SHI Receive FIFO Full ; SHI Receive Overrun Error ; SHI Bus Error
;-----------------------------------------------------------------------; Timer Interrupts ;-----------------------------------------------------------------------I_TIM0C EQU I_VEC+$54 I_VEC+$56 I_VEC+$58 I_VEC+$5A I_VEC+$5C I_VEC+$5E ; TIMER 0 compare ; TIMER 0 overflow ; TIMER 1 compare ; TIMER 1 overflow ; TIMER 2 compare ; TIMER 2 overflow
I_TIM0OF EQU I_TIM1C EQU
I_TIM1OF EQU I_TIM2C EQU
I_TIM2OF EQU
;------------------------------------------------------------------------
MOTOROLA
DSP56367
B-3
Equates
; HDI08 Interrupts ;-----------------------------------------------------------------------I_HI08RX EQU I_HI08TX EQU I_HI08CM EQU I_VEC+$60 I_VEC+$62 I_VEC+$64 ; Host Receive Data Full ; Host Transmit Data Empty ; Host Command (Default)
;-----------------------------------------------------------------------; ESAI_1 Interrupts ;-----------------------------------------------------------------------I_ESAI1RD I_ESAI1RED I_ESAI1RDE I_ESAI1RLS I_ESAI1TD I_ESAI1TED I_ESAI1TDE I_ESAI1TLS EQU EQU EQU EQU EQU EQU EQU EQU I_VEC+$70 I_VEC+$72 I_VEC+$74 I_VEC+$76 I_VEC+$78 I_VEC+$7A I_VEC+$7C I_VEC+$7E ; ESAI_1 Receive Data ; ESAI_1 Receive Even Data ; ESAI_1 Receive Data With Exception Status ; ESAI_1 Receive Last Slot ; ESAI_1 Transmit Data ; ESAI_1 Transmit Even Data ; ESAI_1 Transmit Data With Exception Status ; ESAI_1 Transmit Last Slot
;-----------------------------------------------------------------------; INTERRUPT ENDING ADDRESS ;-----------------------------------------------------------------------I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space
;------------------ end of intequ.asm -----------------------;*********************************************************************************
; ; ;
EQUATES for DSP56367 I/O registers and ports Last update: April 24, 2000
;*********************************************************************************
B-4
DSP56367
MOTOROLA
Equates
page opt ioequ
132,55,0,0,0 mex
ident
1,0
;-----------------------------------------------------------------------; ; ; ;-----------------------------------------------------------------------; M_HDR M_HDDR M_PCRC M_PRRC M_PDRC M_PCRD M_PRRD M_PDRD M_PCRE M_PRRE M_PDRE M_OGDB Register Addresses EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $FFFFC9 $FFFFC8 $FFFFBF $FFFFBE $FFFFBD $FFFFD7 $FFFFD6 $FFFFD5 $FFFFD7 $FFFFD6 $FFFFD5 $FFFFFC ; Host port GPIO data Register ; Host port GPIO direction Register ; Port C Control Register ; Port C Direction Register ; Port C GPIO Data Register ; Port D Control register ; Port D Direction Data Register ; Port D GPIO Data Register ; Port E Control register ; Port E Direction Data Register ; Port E GPIO Data Register ; OnCE GDB Register EQUATES for I/O Port Programming
;-----------------------------------------------------------------------; ; ; ;-----------------------------------------------------------------------EQUATES for Exception Processing
MOTOROLA
DSP56367
B-5
Equates
; M_IPRC M_IPRP ; M_IAL M_IAL0 M_IAL1 M_IAL2 M_IBL M_IBL0 M_IBL1 M_IBL2 M_ICL M_ICL0 M_ICL1 M_ICL2 M_IDL M_IDL0 M_IDL1 M_IDL2 M_D0L M_D0L0 M_D0L1 M_D1L M_D1L0 M_D1L1 M_D2L
Register Addresses EQU EQU $FFFFFF $FFFFFE ; Interrupt Priority Register Core ; Interrupt Priority Register Peripheral
Interrupt Priority Register Core (IPRC) EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $7 0 1 2 $38 3 4 5 $1C0 6 7 8 $E00 9 10 11 $3000 12 13 $C000 14 15 $30000 ; IRQA Mode Mask ; IRQA Mode Interrupt Priority Level (low) ; IRQA Mode Interrupt Priority Level (high) ; IRQA Mode Trigger Mode ; IRQB Mode Mask ; IRQB Mode Interrupt Priority Level (low) ; IRQB Mode Interrupt Priority Level (high) ; IRQB Mode Trigger Mode ; IRQC Mode Mask ; IRQC Mode Interrupt Priority Level (low) ; IRQC Mode Interrupt Priority Level (high) ; IRQC Mode Trigger Mode ; IRQD Mode Mask ; IRQD Mode Interrupt Priority Level (low) ; IRQD Mode Interrupt Priority Level (high) ; IRQD Mode Trigger Mode ; DMA0 Interrupt priority Level Mask ; DMA0 Interrupt Priority Level (low) ; DMA0 Interrupt Priority Level (high) ; DMA1 Interrupt Priority Level Mask ; DMA1 Interrupt Priority Level (low) ; DMA1 Interrupt Priority Level (high) ; DMA2 Interrupt priority Level Mask
B-6
DSP56367
MOTOROLA
Equates
M_D2L0 M_D2L1 M_D3L M_D3L0 M_D3L1 M_D4L M_D4L0 M_D4L1 M_D5L M_D5L0 M_D5L1 ; M_ESL M_ESL0 M_ESL1 M_SHL M_SHL0 M_SHL1 M_HDL M_HDL0 M_HDL1 M_DAL M_DAL0 M_DAL1 M_TAL M_TAL0
EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU
16 17 $C0000 18 19 $300000 20 21 $C00000 22 23
; DMA2 Interrupt Priority Level (low) ; DMA2 Interrupt Priority Level (high) ; DMA3 Interrupt Priority Level Mask ; DMA3 Interrupt Priority Level (low) ; DMA3 Interrupt Priority Level (high) ; DMA4 Interrupt priority Level Mask ; DMA4 Interrupt Priority Level (low) ; DMA4 Interrupt Priority Level (high) ; DMA5 Interrupt priority Level Mask ; DMA5 Interrupt Priority Level (low) ; DMA5 Interrupt Priority Level (high)
Interrupt Priority Register Peripheral (IPRP) EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $3 0 1 $C 2 3 $30 4 5 $C0 6 7 $300 8 ; ESAI Interrupt Priority Level Mask ; ESAI Interrupt Priority Level (low) ; ESAI Interrupt Priority Level (high) ; SHI Interrupt Priority Level Mask ; SHI Interrupt Priority Level (low) ; SHI Interrupt Priority Level (high) ; HDI08 Interrupt Priority Level Mask ; HDI08 Interrupt Priority Level (low) ; HDI08 Interrupt Priority Level (high) ; DAX Interrupt Priority Level ; DAX Interrupt Priority Level ; DAX Interrupt Priority Level Mask (low) (high)
;Timer Interrupt Priority Level Mask ;Timer Interrupt Priority Level (low)
MOTOROLA
DSP56367
B-7
Equates
M_TAL1 M_ES1L M_ESL10 M_ESL11
EQU EQU EQU EQU
9 $C00 0 1
;Timer Interrupt Priority Level (high) ; ESAI_1 Interrupt Priority Level Mask ; ESAI_1 Interrupt Priority Level (low) ; ESAI_1 Interrupt Priority Level (high)
;-----------------------------------------------------------------------; ; ; ;-----------------------------------------------------------------------; M_DSTR M_DOR0 M_DOR1 M_DOR2 M_DOR3 ; M_DSR0 M_DDR0 M_DCO0 M_DCR0 ; M_DSR1 M_DDR1 M_DCO1 M_DCR1 ; M_DSR2 Register Addresses Of DMA EQU EQU EQU EQU EQU $FFFFF4 $FFFFF3 $FFFFF2 $FFFFF1 $FFFFF0 ; DMA Status Register ; DMA Offset Register 0 ; DMA Offset Register 1 ; DMA Offset Register 2 ; DMA Offset Register 3 EQUATES for Direct Memory Access (DMA)
Register Addresses Of DMA0 EQU EQU EQU EQU $FFFFEF $FFFFEE $FFFFED $FFFFEC ; DMA0 Source Address Register ; DMA0 Destination Address Register ; DMA0 Counter ; DMA0 Control Register
Register Addresses Of DMA1 EQU EQU EQU EQU $FFFFEB $FFFFEA $FFFFE9 $FFFFE8 ; DMA1 Source Address Register ; DMA1 Destination Address Register ; DMA1 Counter ; DMA1 Control Register
Register Addresses Of DMA2 EQU $FFFFE7 ; DMA2 Source Address Register
B-8
DSP56367
MOTOROLA
Equates
M_DDR2 M_DCO2 M_DCR2
EQU EQU EQU
$FFFFE6 $FFFFE5 $FFFFE4
; DMA2 Destination Address Register ; DMA2 Counter ; DMA2 Control Register
; M_DSR3 M_DDR3 M_DCO3 M_DCR3 ; M_DSR4 M_DDR4 M_DCO4 M_DCR4 ; M_DSR5 M_DDR5 M_DCO5 M_DCR5 ; M_DSS M_DSS0 M_DSS1 M_DDS M_DDS0 M_DDS1
Register Addresses Of DMA3 EQU EQU EQU EQU $FFFFE3 $FFFFE2 $FFFFE1 $FFFFE0 ; DMA3 Source Address Register ; DMA3 Destination Address Register ; DMA3 Counter ; DMA3 Control Register
Register Addresses Of DMA4 EQU EQU EQU EQU $FFFFDF $FFFFDE $FFFFDD $FFFFDC ; DMA4 Source Address Register ; DMA4 Destination Address Register ; DMA4 Counter ; DMA4 Control Register
Register Addresses Of DMA5 EQU EQU EQU EQU $FFFFDB $FFFFDA $FFFFD9 $FFFFD8 ; DMA5 Source Address Register ; DMA5 Destination Address Register ; DMA5 Counter ; DMA5 Control Register
DMA Control Register EQU EQU EQU EQU EQU EQU $3 0 1 $C 2 3 ; DMA Source Space Mask (DSS0-Dss1) ; DMA Source Memory space 0 ; DMA Source Memory space 1 ; DMA Destination Space Mask (DDS-DDS1) ; DMA Destination Memory Space 0 ; DMA Destination Memory Space 1
MOTOROLA
DSP56367
B-9
Equates
M_DAM M_DAM0 M_DAM1 M_DAM2 M_DAM3 M_DAM4 M_DAM5 M_D3D M_DRS M_DRS0 M_DRS1 M_DRS2 M_DRS3 M_DRS4 M_DCON M_DPR M_DPR0 M_DPR1 M_DTM M_DTM0 M_DTM1 M_DTM2 M_DIE M_DE ; M_DTD M_DTD0
EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU
$3f0 4 5 6 7 8 9 10 $F800 11 12 13 14 15 16 $60000 17 18 $380000 19 20 21 22 23
; DMA Address Mode Mask (DAM5-DAM0) ; DMA Address Mode 0 ; DMA Address Mode 1 ; DMA Address Mode 2 ; DMA Address Mode 3 ; DMA Address Mode 4 ; DMA Address Mode 5 ; DMA Three Dimensional Mode ; DMA Request Source Mask (DRS0-DRS4) ;DMA Request Source bit 0 ;DMA Request Source bit 1 ;DMA Request Source bit 2 ;DMA Request Source bit 3 ;DMA Request Source bit 4 ; DMA Continuous Mode ; DMA Channel Priority ; DMA Channel Priority Level (low) ; DMA Channel Priority Level (high) ; DMA Transfer Mode Mask (DTM2-DTM0) ; DMA Transfer Mode 0 ; DMA Transfer Mode 1 ; DMA Transfer Mode 2 ; DMA Interrupt Enable bit ; DMA Channel Enable bit
DMA Status Register EQU EQU $3F 0 ; Channel Transfer Done Status MASK (DTD0-DTD5) ; DMA Channel Transfer Done Status 0
B-10
DSP56367
MOTOROLA
Equates
M_DTD1 M_DTD2 M_DTD3 M_DTD4 M_DTD5 M_DACT M_DCH M_DCH0 M_DCH1 M_DCH2
EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU
1 2 3 4 5 8 $E00 9 10 11
; DMA Channel Transfer Done Status 1 ; DMA Channel Transfer Done Status 2 ; DMA Channel Transfer Done Status 3 ; DMA Channel Transfer Done Status 4 ; DMA Channel Transfer Done Status 5 ; DMA Active State ; DMA Active Channel Mask (DCH0-DCH2) ; DMA Active Channel 0 ; DMA Active Channel 1 ; DMA Active Channel 2
;-----------------------------------------------------------------------; ; ; ;-----------------------------------------------------------------------; M_PCTL ; M_MF M_MF0 M_MF1 M_MF2 M_MF3 M_MF4 M_MF5 M_MF6 Register Addresses Of PLL EQU $FFFFFD ; PLL Control Register EQUATES for Phase Locked Loop (PLL)
PLL Control Register EQU EQU EQU EQU EQU EQU EQU EQU 0 1 2 3 4 5 6 $FFF ; Multiplication Factor Bits Mask (MF0-MF11) ;Multiplication Factor bit 0 ;Multiplication Factor bit 1 ;Multiplication Factor bit 2 ;Multiplication Factor bit 3 ;Multiplication Factor bit 4 ;Multiplication Factor bit 5 ;Multiplication Factor bit 6
MOTOROLA
DSP56367
B-11
Equates
M_MF7 M_MF8 M_MF9 M_MF10 M_MF11 M_DF M_DF0 M_DF1 M_DF2 M_XTLR M_XTLD M_PSTP M_PEN M_COD M_PD M_PD0 M_PD1 M_PD2 M_PD3
EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU
7 8 9 10 11 $7000 12 13 14 15 16 17 18 19 $F00000 20 21 22 23
;Multiplication Factor bit 7 ;Multiplication Factor bit 8 ;Multiplication Factor bit 9 ;Multiplication Factor bit 10 ;Multiplication Factor bit 11 ; Division Factor Bits Mask (DF0-DF2) ;Division Factor bit 0 ;Division Factor bit 1 ;Division Factor bit 2 ; XTAL Range select bit ; XTAL Disable Bit ; STOP Processing State Bit ; PLL Enable Bit ; PLL Clock Output Disable Bit ; PreDivider Factor Bits Mask (PD0-PD3) ;PreDivider Factor bit 0 ;PreDivider Factor bit 1 ;PreDivider Factor bit 2 ;PreDivider Factor bit 3
;-----------------------------------------------------------------------; ; ; ;-----------------------------------------------------------------------; M_BCR M_DCR Register Addresses Of BIU EQU EQU $FFFFFB $FFFFFA ; Bus Control Register ; DRAM Control Register EQUATES for BIU
B-12
DSP56367
MOTOROLA
Equates
M_AAR0 M_AAR1 M_AAR2 M_AAR3 M_IDR ; M_BA0W M_BA0W0 M_BA0W1 M_BA0W2 M_BA0W3 M_BA0W4 M_BA1W M_BA1W0 M_BA1W1 M_BA1W2 M_BA1W3 M_BA1W4 M_BA2W M_BA2W0 M_BA2W1 M_BA2W2 M_BA3W M_BA3W0 M_BA3W1 M_BA3W2
EQU EQU EQU EQU EQU
$FFFFF9 $FFFFF8 $FFFFF7 $FFFFF6 $FFFFF5
; Address Attribute Register 0 ; Address Attribute Register 1 ; Address Attribute Register 2 ; Address Attribute Register 3 ; ID Register
Bus Control Register EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $1F 0 1 2 3 4 $3E0 5 6 7 8 9 $1C00 10 11 12 $E000 13 14 15 ; Area 0 Wait Control Mask (BA0W0-BA0W4) ;Area 0 Wait Control Bit 0 ;Area 0 Wait Control Bit 1 ;Area 0 Wait Control Bit 2 ;Area 0 Wait Control Bit 3 ;Area 0 Wait Control Bit 4 ; Area 1 Wait Control Mask (BA1W0-BA14) ;Area 1 Wait Control Bit 0 ;Area 1 Wait Control Bit 1 ;Area 1 Wait Control Bit 2 ;Area 1 Wait Control Bit 3 ;Area 1 Wait Control Bit 4 ; Area 2 Wait Control Mask (BA2W0-BA2W2) ;Area 2 Wait Control Bit 0 ;Area 2 Wait Control Bit 1 ;Area 2 Wait Control Bit 2 ; Area 3 Wait Control Mask (BA3W0-BA3W3) ;Area 3 Wait Control Bit 0 ;Area 3 Wait Control Bit 1 ;Area 3 Wait Control Bit 2
MOTOROLA
DSP56367
B-13
Equates
M_BDFW M_BDFW0 M_BDFW1 M_BDFW2 M_BDFW3 M_BDFW4 M_BBS M_BLH M_BRH ; M_BCW M_BCW0 M_BCW1 M_BRW M_BRW0 M_BRW1 M_BPS M_BPS0 M_BPS1 M_BPLE M_BME M_BRE M_BSTR M_BRF M_BRF0 M_BRF1 M_BRF2
EQU EQU EQU EQU EQU EQU EQU EQU EQU
$1F0000 16 17 18 19 20 21 22 23
; Default Area Wait Control Mask (BDFW0-BDFW4) ;Default Area Wait Control bit 0 ;Default Area Wait Control bit 1 ;Default Area Wait Control bit 2 ;Default Area Wait Control bit 3 ;Default Area Wait Control bit 4 ; Bus State ; Bus Lock Hold ; Bus Request Hold
DRAM Control Register EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $3 0 1 $C 2 3 $300 4 5 11 12 13 14 $7F8000 15 16 17 ; In Page Wait States Bits Mask (BCW0-BCW1) ; In Page Wait States Bit 0 ; In Page Wait States Bit 1 ; Out Of Page Wait States Bits Mask (BRW0-BRW1) ;Out of Page Wait States bit 0 ; Out of Page Wait States bit 1 ; DRAM Page Size Bits Mask (BPS0-BPS1) ; DRAM Page Size Bits 0 ; DRAM Page Size Bits 1 ; Page Logic Enable ; Mastership Enable ; Refresh Enable ; Software Triggered Refresh ; Refresh Rate Bits Mask (BRF0-BRF7) ; Refresh Rate Bit 0 ; Refresh Rate Bit 1 ; Refresh Rate Bit 2
B-14
DSP56367
MOTOROLA
Equates
M_BRF3 M_BRF4 M_BRF5 M_BRF6 M_BRF7 M_BRP ;
EQU EQU EQU EQU EQU EQU
18 19 20 21 22 23
; Refresh Rate Bit 3 ; Refresh Rate Bit 4 ; Refresh Rate Bit 5 ; Refresh Rate Bit 6 ; Refresh Rate Bit 7 ; Refresh prescaler
Address Attribute Registers $3 ; External Access Type and Pin Definition Bits Mask
M_BAT EQU (BAT0-BAT1) M_BAT0 M_BAT1 M_BAAP M_BPEN M_BXEN M_BYEN M_BAM M_BPAC M_BNC M_BNC0 M_BNC1 M_BNC2 M_BNC3 M_BAC M_BAC0 M_BAC1 M_BAC2 M_BAC3 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU
0 1 2 3 4 5 6 7 $F00 8 9 10 11 $FFF000 12 13 14 15
; External Access Type and Pin Definition Bits 0 ; External Access Type and Pin Definition Bits 1 ; Address Attribute Pin Polarity ; Program Space Enable ; X Data Space Enable ; Y Data Space Enable ; Address Muxing ; Packing Enable ; Number of Address Bits to Compare Mask (BNC0-BNC3) ; Number of Address Bits to Compare 0 ; Number of Address Bits to Compare 1 ; Number of Address Bits to Compare 2 ; Number of Address Bits to Compare 3 ; Address to Compare Bits Mask (BAC0-BAC11) ; Address to Compare Bits 0 ; Address to Compare Bits 1 ; Address to Compare Bits 2 ; Address to Compare Bits 3
MOTOROLA
DSP56367
B-15
Equates
M_BAC4 M_BAC5 M_BAC6 M_BAC7 M_BAC8 M_BAC9 M_BAC10 M_BAC11 ; M_C M_V M_Z M_N M_U M_E M_L M_S M_I0 M_I1 M_S0 M_S1 M_SC M_DM M_LF M_FV M_SA
EQU EQU EQU EQU EQU EQU EQU EQU
16 17 18 19 20 21 22 23
; Address to Compare Bits 4 ; Address to Compare Bits 5 ; Address to Compare Bits 6 ; Address to Compare Bits 7 ; Address to Compare Bits 8 ; Address to Compare Bits 9 ; Address to Compare Bits 10 ; Address to Compare Bits 11
control and status bits in SR EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 0 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 ; Carry ; Overflow ; Zero ; Negative ; Unnormalized ; Extension ; Limit ; Scaling Bit ; Interupt Mask Bit 0 ; Interupt Mask Bit 1 ; Scaling Mode Bit 0 ; Scaling Mode Bit 1 ; Sixteen_Bit Compatibility ; Double Precision Multiply ; DO-Loop Flag ; DO-Forever Flag ; Sixteen-Bit Arithmetic
B-16
DSP56367
MOTOROLA
Equates
M_CE M_SM M_RM M_CP M_CP0 M_CP1 ; M_MA M_MB M_MC M_MD M_EBD M_SD M_MS M_CDP M_CDP0 M_CDP1 M_BE M_TAS M_BRT M_ABE M_APD M_ATE M_XYS M_EUN M_EOV M_WRP
EQU EQU EQU EQU EQU EQU
19 20 21 $c00000 22 23
; Instruction Cache Enable ; Arithmetic Saturation ; Rounding Mode ; mask for CORE-DMA priority bits in SR ; bit 0 of priority bits in SR ; bit 1 of priority bits in SR
control and status bits in OMR EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 0 1 2 3 4 6 7 $300 8 9 10 11 12 13 14 15 16 17 18 19 ; Operating Mode A ; Operating Mode B ; Operating Mode C ; Operating Mode D ; External Bus Disable bit in OMR ; Stop Delay ;Memory Switch Mode ; mask for CORE-DMA priority bits in OMR ; bit 0 of priority bits in OMR Core DMA ; bit 1 of priority bits in OMR Core DMA ; Burst Enable ; TA Synchronize Select ; Bus Release Timing ;Async. Bus Arbitration Enable ;Addess Priority Disable ;Address Tracing Enable ; Stack Extension space select bit in OMR. ; Extensed stack UNderflow flag in OMR. ; Extended stack OVerflow flag in OMR. ; Extended WRaP flag in OMR.
MOTOROLA
DSP56367
B-17
Equates
M_SEN M_PAEN
EQU EQU
20 23
; Stack Extension Enable bit in OMR. ; Patch Enable
;-----------------------------------------------------------------------; ; ; ;-----------------------------------------------------------------------; Register Addresses EQUATES for DAX (SPDIF Tx)
M_XSTR M_XADRB M_XADR M_XADRA M_XNADR M_XCTR ; M_XADE M_XAUR M_XBLK ; M_XVA M_XUA M_XCA M_XVB M_XUB M_XCB
EQU EQU EQU EQU EQU EQU
$FFFFD4 $FFFFD3 $FFFFD2 $FFFFD2 $FFFFD1 $FFFFD0
; DAX Status Register (XSTR) ; DAX Audio Data Register B (XADRB) ;DAX Audio Data Register (XADR) ; DAX Audio Data Register A (XADRA) ; DAX Non-Audio Data Register (XNADR) ; DAX Control Register (XCTR)
status bits in XSTR EQU EQU EQU 0 1 2 ; DAX Audio Data Register Empty (XADE) ; DAX Trasmit Underrun Error Flag (XAUR) ; DAX Block Transferred (XBLK)
non-audio bits in XNADR EQU EQU EQU EQU EQU EQU 10 11 12 13 14 15 ; DAX Channel A Validity (XVA) ; DAX Channel A User Data (XUA) ; DAX Channel A Channel Status (XCA) ; DAX Channel B Validity (XVB) ; DAX Channel B User Data (XUB) ; DAX Channel B Channel Status (XCB)
B-18
DSP56367
MOTOROLA
Equates
; M_XDIE M_XUIE M_XBIE M_XCS0 M_XCS1 M_XSB
control bits in XCTR EQU EQU EQU EQU EQU EQU 0 1 2 3 4 5 ; DAX Audio Data Register Empty Interrupt Enable (XDIE) ; DAX Underrun Error Interrupt Enable (XUIE) ; DAX Block Transferred Interrupt Enable (XBIE) ; DAX Clock Input Select 0 (XCS0) ; DAX Clock Input Select 1 (XCS1) ; DAX Start Block (XSB)
;-----------------------------------------------------------------------; ; ; ;-----------------------------------------------------------------------; Register Addresses EQUATES for SHI
M_HRX M_HTX M_HSAR M_HCSR M_HCKR ; M_HA6 M_HA5 M_HA4 M_HA3 M_HA1 ;
EQU EQU EQU EQU EQU
$FFFF94 $FFFF93 $FFFF92 $FFFF91 $FFFF90
; SHI Receive FIFO (HRX) ; SHI Transmit Register (HTX) ; SHI I2C Slave Address Register (HSAR) ; SHI Control/Status Register (HCSR) ; SHI Clock Control Register (HCKR)
HSAR bits EQU EQU EQU EQU EQU 23 22 21 20 18 ; SHI I2C Slave Address (HA6) ; SHI I2C Slave Address (HA5) ; SHI I2C Slave Address (HA4) ; SHI I2C Slave Address (HA3) ; SHI I2C Slave Address (HA1)
control and status bits in HCSR EQU 22 ; SHI Host Busy (HBUSY)
M_HBUSY
MOTOROLA
DSP56367
B-19
Equates
M_HBER M_HROE M_HRFF M_HRNE M_HTDE M_HTUE M_HRIE1 M_HRIE0 M_HTIE M_HBIE M_HIDLE M_HRQE1 M_HRQE0 M_HMST M_HFIFO M_HCKFR M_HM1 M_HM0 M_HI2C M_HEN ; M_HFM1 M_HFM0 M_HDM7 M_HDM6 M_HDM5
EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU
21 20 19 17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
; SHI Bus Error (HBER) ; SHI Receive Overrun Error (HROE) ; SHI Receivr FIFO Full (HRFF) ; SHI Receive FIFO Not Empty (HRNE) ; SHI Host Transmit data Empty (HTDE) ; SHI Host Transmit Underrun Error (HTUE) ; SHI Receive Interrupt Enable (HRIE1) ; SHI Receive Interrupt Enable (HRIE0) ; SHI Transmit Interrupt Enable (HTIE) ; SHI Bus-Error Interrupt Enable (HBIE) ; SHI Idle (HIDLE) ; SHI Host Request Enable (HRQE1) ; SHI Host Request Enable (HRQE0) ; SHI Master Mode (HMST) ; SHI FIFO Enable Control (HFIFO) ; SHI Clock Freeze (HCKFR) ; SHI Serial Host Interface Mode (HM1) ; SHI Serial Host Interface Mode (HM0) ; SHI I2c/SPI Selection (HI2C) ; SHI Host Enable (HEN)
control bits in HCKR EQU EQU EQU EQU EQU 13 12 10 9 8 ; SHI Filter Model (HFM1) ; SHI Filter Model (HFM0) ; SHI Divider Modulus Select (HDM7) ; SHI Divider Modulus Select (HDM6) ; SHI Divider Modulus Select (HDM5)
B-20
DSP56367
MOTOROLA
Equates
M_HDM4 M_HDM3 M_HDM2 M_HDM1 M_HDM0 M_HRS M_CPOL M_CPHA
EQU EQU EQU EQU EQU EQU EQU EQU
7 6 5 4 3 2 1 0
; SHI Divider Modulus Select (HDM4) ; SHI Divider Modulus Select (HDM3) ; SHI Divider Modulus Select (HDM2) ; SHI Divider Modulus Select (HDM1) ; SHI Divider Modulus Select (HDM0) ; SHI Prescalar Rate Select (HRS) ; SHI Clock Polarity (CPOL) ; SHI Clock Phase (CPHA)
;-----------------------------------------------------------------------; ; EQUATES for ESAI_1 Registers
; register bit equates can be the same as for the ESAI register bit equates. ;-----------------------------------------------------------------------; Register Addresses
M_EMUXR
EQU
$FFFFAF $FFFF9C $FFFF9B $FFFF9A $FFFF99 $FFFF98 $FFFF97 $FFFF96 $FFFF95 $FFFF94 $FFFF93 $FFFF8B
; MUX PIN CONTROL REGISTER (EMUXR) ; ESAI_1 Receive Slot Mask Register B (RSMB_1) ; ESAI_1 Receive Slot Mask Register A (RSMA_1) ; ESAI_1 Transmit Slot Mask Register B (TSMB_1) ; ESAI_1 Transmit Slot Mask Register A (TSMA_1) ; ESAI_1 Receive Clock Control Register (RCCR_1) ; ESAI_1 Receive Control Register (RCR_1) ; ESAI_1 Transmit Clock Control Register (TCCR_1) ; ESAI_1 Transmit Control Register (TCR_1) ; ESAI_1 Control Register (SAICR_1) ; ESAI_1 Status Register (SAISR_1) ; ESAI_1 Receive Data Register 3 (RX3_1)
M_RSMB_1 EQU M_RSMA_1 EQU M_TSMB_1 EQU M_TSMA_1 EQU M_RCCR_1 EQU M_RCR_1 EQU
M_TCCR_1 EQU M_TCR_1 EQU
M_SAICR_1 EQU M_SAISR_1 EQU M_RX3_1 EQU
MOTOROLA
DSP56367
B-21
Equates
M_RX2_1 EQU M_RX1_1 EQU M_RX0_1 EQU M_TSR_1 EQU M_TX5_1 EQU M_TX4_1 EQU M_TX3_1 EQU M_TX2_1 EQU M_TX1_1 EQU M_TX0_1 EQU
$FFFF8A $FFFF89 $FFFF88 $FFFF86 $FFFF85 $FFFF84 $FFFF83 $FFFF82 $FFFF81 $FFFF80
; ESAI_1 Receive Data Register 2 (RX2_1) ; ESAI_1 Receive Data Register 1 (RX1_1) ; ESAI_1 Receive Data Register 0 (RX0_1) ; ESAI_1 Time Slot Register (TSR_1) ; ESAI_1 Transmit Data Register 5 (TX5_1) ; ESAI_1 Transmit Data Register 4 (TX4_1) ; ESAI_1 Transmit Data Register 3 (TX3_1) ; ESAI_1 Transmit Data Register 2 (TX2_1) ; ESAI_1 Transmit Data Register 1 (TX1_1) ; ESAI_1 Transmit Data Register 0 (TX0_1)
;-----------------------------------------------------------------------; ; ; ;-----------------------------------------------------------------------; Register Addresses EQUATES for ESAI
M_RSMB M_RSMA M_TSMB M_TSMA M_RCCR M_RCR M_TCCR M_TCR M_SAICR
EQU EQU EQU EQU EQU EQU EQU EQU EQU
$FFFFBC $FFFFBB $FFFFBA $FFFFB9 $FFFFB8 $FFFFB7 $FFFFB6 $FFFFB5 $FFFFB4
; ESAI Receive Slot Mask Register B (RSMB) ; ESAI Receive Slot Mask Register A (RSMA) ; ESAI Transmit Slot Mask Register B (TSMB) ; ESAI Transmit Slot Mask Register A (TSMA) ; ESAI Receive Clock Control Register (RCCR) ; ESAI Receive Control Register (RCR) ; ESAI Transmit Clock Control Register (TCCR) ; ESAI Transmit Control Register (TCR) ; ESAI Control Register (SAICR)
B-22
DSP56367
MOTOROLA
Equates
M_SAISR M_RX3 M_RX2 M_RX1 M_RX0 M_TSR M_TX5 M_TX4 M_TX3 M_TX2 M_TX1 M_TX0 ; M_RS31 M_RS30 M_RS29 M_RS28 M_RS27 M_RS26 M_RS25 M_RS24 M_RS23 M_RS22 M_RS21 M_RS20 M_RS19 M_RS18
EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU
$FFFFB3 $FFFFAB $FFFFAA $FFFFA9 $FFFFA8 $FFFFA6 $FFFFA5 $FFFFA4 $FFFFA3 $FFFFA2 $FFFFA1 $FFFFA0
; ESAI Status Register (SAISR) ; ESAI Receive Data Register 3 (RX3) ; ESAI Receive Data Register 2 (RX2) ; ESAI Receive Data Register 1 (RX1) ; ESAI Receive Data Register 0 (RX0) ; ESAI Time Slot Register (TSR) ; ESAI Transmit Data Register 5 (TX5) ; ESAI Transmit Data Register 4 (TX4) ; ESAI Transmit Data Register 3 (TX3) ; ESAI Transmit Data Register 2 (TX2) ; ESAI Transmit Data Register 1 (TX1) ; ESAI Transmit Data Register 0 (TX0)
RSMB Register bits EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI
MOTOROLA
DSP56367
B-23
Equates
M_RS17 M_RS16 ; M_RS15 M_RS14 M_RS13 M_RS12 M_RS11 M_RS10 M_RS9 M_RS8 M_RS7 M_RS6 M_RS5 M_RS4 M_RS3 M_RS2 M_RS1 M_RS0 ; M_TS31 M_TS30 M_TS29 M_TS28 M_TS27 M_TS26
EQU EQU
1 0
; ESAI ; ESAI
RSMA Register bits EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI
TSMB Register bits EQU EQU EQU EQU EQU EQU 15 14 13 12 11 10 ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI
B-24
DSP56367
MOTOROLA
Equates
M_TS25 M_TS24 M_TS23 M_TS22 M_TS21 M_TS20 M_TS19 M_TS18 M_TS17 M_TS16 ; M_TS15 M_TS14 M_TS13 M_TS12 M_TS11 M_TS10 M_TS9 M_TS8 M_TS7 M_TS6 M_TS5 M_TS4 M_TS3 M_TS2 M_TS1 M_TS0
EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU
9 8 7 6 5 4 3 2 1 0
; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI
TSMA Register bits EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI
MOTOROLA
DSP56367
B-25
Equates
; M_RHCKD M_RFSD M_RCKD M_RHCKP M_RFSP M_RCKP M_RFP M_RFP3 M_RFP2 M_RFP1 M_RFP0 M_RDC M_RDC4 M_RDC3 M_RDC2 M_RDC1 M_RDC0 M_RPSR M_RPM M_RPM7 M_RPM6 M_RPM5 M_RPM4 M_RPM3 M_RPM2
RCCR Register bits EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 23 22 21 20 19 18 $3C000 17 16 15 14 $3E00 13 12 11 10 9 8 $FF 7 6 5 4 3 2 ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ;ESAI ; ESAI ;ESAI ;ESAI MASK ; ESAI ; ESAI ; ESAI ; ESAI ;ESAI MASK ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI
B-26
DSP56367
MOTOROLA
Equates
M_RPM1 M_RPM0 ; M_RLIE M_RIE M_REDIE M_REIE M_RPR M_RFSR M_RFSL M_RSWS M_RSWS4 M_RSWS3 M_RSWS2 M_RSWS1 M_RSWS0 M_RMOD M_RMOD1 M_RMOD0 M_RWA M_RSHFD M_RE M_RE3 M_RE2 M_RE1 M_RE0 ;
EQU EQU
1 0
; ESAI ; ESAI
RCR Register bits EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 3 2 1 0 9 8 7 6 $F ; ESAI ; ESAI ; ESAI ; ESAI 16 15 $7C00 14 13 12 11 10 $300 ; ESAI ; ESAI ; ESAI ; ESAI 23 22 21 20 19 ; ; ESAI ; ESAI ;ESAI MASK ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ESAI
TCCR Register bits
MOTOROLA
DSP56367
B-27
Equates
M_THCKD M_TFSD M_TCKD M_THCKP M_TFSP M_TCKP M_TFP M_TFP3 M_TFP2 M_TFP1 M_TFP0 M_TDC M_TDC4 M_TDC3 M_TDC2 M_TDC1 M_TDC0 M_TPSR M_TPM M_TPM7 M_TPM6 M_TPM5 M_TPM4 M_TPM3 M_TPM2 M_TPM1
EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU
23 22 21 20 19 18 $3C000 17 16 15 14 $3E00 13 12 11 10 9 8 $FF 7 6 5 4 3 2 1 ;
; ESAI ; ESAI ; ESAI ;ESAI ; ESAI ; ESAI
; ESAI ; ESAI ; ESAI ; ESAI
; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI
B-28
DSP56367
MOTOROLA
Equates
M_TPM0 ; M_TLIE M_TIE M_TEDIE M_TEIE M_TPR M_PADC M_TFSR M_TFSL M_TSWS M_TSWS4 M_TSWS3 M_TSWS2 M_TSWS1 M_TSWS0 M_TMOD M_TMOD1 M_TMOD0 M_TWA M_TSHFD M_TEM M_TE5 M_TE4 M_TE3 M_TE2 M_TE1
EQU
0
; ESAI
TCR Register bits EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 5 4 3 2 1 9 8 7 6 $3F ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI 16 15 $7C00 14 13 12 11 10 $300 ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI 23 22 21 20 19 17 ; ; ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ESAI ESAI
MOTOROLA
DSP56367
B-29
Equates
M_TE0 ; M_ALC M_TEBE M_SYN M_OF2 M_OF1 M_OF0 ; M_TODE M_TEDE M_TDE M_TUE M_TFS M_RODF M_REDF M_RDF M_ROE M_RFS M_IF2 M_IF1 M_IF0
EQU
0
; ESAI
control bits of SAICR EQU EQU EQU EQU EQU EQU 8 7 6 2 1 0 ;ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI
status bits of SAISR EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 17 16 15 14 13 10 9 8 7 6 2 1 0 ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI ; ESAI
;-----------------------------------------------------------------------; ; ; EQUATES for HDI08
B-30
DSP56367
MOTOROLA
Equates
;-----------------------------------------------------------------------; Register Addresses
M_HOTX M_HORX M_HBAR M_HPCR M_HSR M_HCR ; M_HRIE M_HOTIE M_HCIE M_HF2 M_HF3 M_HODM0 M_HODM1 M_HODM2
EQU EQU EQU EQU EQU EQU HCR bits EQU EQU EQU EQU EQU EQU EQU EQU
$FFFFC7 $FFFFC6 $FFFFC5 $FFFFC4 $FFFFC3 $FFFFC2
; HOST Transmit Register (HOTX) ; HOST Receive Register (HORX) ; HOST Base Address Register (HBAR) ; HOST Port Control Register (HPCR) ; HOST Status Register (HSR) ; HOST Control Register (HCR)
$0 $1 $2 $3 $4 $5 $6 $7
; HOST Receive interrupts Enable ; HOST Transmit Interrupt Enable ; HOST Command Interrupt Enable ; HOST Flag 2 ; HOST Flag 3 ; HOST DMA Mode Control Bit 0 ; HOST DMA Mode Control Bit 1 ; HOST DMA Mode Control Bit 2
; M_HRDF M_HOTDE M_HCP M_HF0 M_HF1 M_DMA
HSR bits EQU EQU EQU EQU EQU EQU $0 $1 $2 $3 $4 $7 ; HOST Receive Data Full ; HOST Receive Data Emptiy ; HOST Command Pending ; HOST Flag 0 ; HOST Flag 1 ; HOST DMA Status
MOTOROLA
DSP56367
B-31
Equates
; M_HGEN M_HA8EN M_HA9EN M_HCSEN M_HREN M_HAEN M_HOEN M_HROD M_HDSP M_HASP M_HMUX M_HDDS M_HCSP M_HRP M_HAP ; M_BA M_BA10 M_BA9 M_BA8 M_BA7 M_BA6 M_BA5 M_BA4 M_BA3
HPCR bits EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $0 $1 $2 $3 $4 $5 $6 $8 $9 $a $b $c $d $e $f HBAR EQU EQU EQU EQU EQU EQU EQU EQU EQU $FF 7 6 5 4 3 2 1 0 BITS ; HOST Port Enable ; HOST Address 8 Enable ; HOST Address 9 Enable ; HOST Chip Select Enable ; HOST Request Enable ; HOST Acknowledge Enable ; HOST Enable ; HOST Request Open Dranin mode ; HOST Data Strobe Polarity ; HOST Address Strobe Polarity ; HOST Multiplexed bus select ; HOST Double/Single Strobe select ; HOST Chip Select Polarity ; HOST Request Polarity ; HOST Acknowledge Polarity
B-32
DSP56367
MOTOROLA
Equates
;----------------------------------------------------------------------; ; ; ;-----------------------------------------------------------------------; M_TCSR0 M_TLR0 M_TCPR0 M_TCR0 ; M_TCSR1 M_TLR1 M_TCPR1 M_TCR1 ; M_TCSR2 M_TLR2 M_TCPR2 M_TCR2 M_TPLR M_TPCR ; M_TE M_TOIE M_TCIE M_TC Register Addresses Of TIMER0 EQU EQU EQU EQU $FFFF8F $FFFF8E $FFFF8D $FFFF8C ; TIMER0 Control/Status Register ; TIMER0 Load Reg ; TIMER0 Compare Register ; TIMER0 Count Register EQUATES for TIMER
Register Addresses Of TIMER1 EQU EQU EQU EQU $FFFF8B $FFFF8A $FFFF89 $FFFF88 ; TIMER1 Control/Status Register ; TIMER1 Load Reg ; TIMER1 Compare Register ; TIMER1 Count Register
Register Addresses Of TIMER2 EQU EQU EQU EQU EQU EQU $FFFF87 $FFFF86 $FFFF85 $FFFF84 $FFFF83 $FFFF82 ; TIMER2 Control/Status Register ; TIMER2 Load Reg ; TIMER2 Compare Register ; TIMER2 Count Register ; TIMER Prescaler Load Register ; TIMER Prescalar Count Register
Timer Control/Status Register Bit Flags EQU EQU EQU EQU 0 1 2 $F0 ; Timer Enable ; Timer Overflow Interrupt Enable ; Timer Compare Interrupt Enable ; Timer Control Mask (TC0-TC3)
MOTOROLA
DSP56367
B-33
Equates
M_INV M_TRM M_DIR M_DI M_DO M_PCE M_TOF M_TCF ; M_PS M_PS0 M_PS1 ;
EQU EQU EQU EQU EQU EQU EQU EQU
8 9 11 12 13 15 20 21
; Inverter Bit ; Timer Restart Mode ; Direction Bit ; Data Input ; Data Output ; Prescaled Clock Enable ; Timer Overflow Flag ; Timer Compare Flag
Timer Prescaler Register Bit Flags EQU EQU EQU $600000 21 22 ; Prescaler Source Mask
Timer Control Bits EQU EQU EQU EQU 4 5 6 7 ; Timer Control 0 ; Timer Control 1 ; Timer Control 2 ; Timer Control 3
M_TC0 M_TC1 M_TC2 M_TC3
;------------------ end of ioequ.asm ------------------------
B-34
DSP56367
MOTOROLA
APPENDIX JTAG BSDL
--------
C
FILENAME : 56367TQFP_revA.bsdl MOTOROLA SSDT JTAG SOFTWARE BSDL File Generated: Mon Jan 18 10:13:53 1999 Revision History:
entity DSP56367 is generic (PHYSICAL_PIN_MAP : string := "TQFP144"); port ( TDO:out TDI:in TMS:in TCK:in SCK:inout SDO0:inout SDO1:inout SDOI23:inout PINIT:in SDOI32:inout SVCC:linkage SGND:linkage SDOI41:inout SDOI50:inout FST:inout FSR:inout SCKT:inout SCKR:inout HSCKT:inout HSCKR:inout QVCC:linkage QGND:linkage QVCCH:linkage HP:inout ADO:inout ACI:inout TIO:inout HVCC:linkage HGND:linkage SS_:in HREQ_:inout RESET_:in PVCC:linkage bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit_vector(0 bit_vector(0 bit; bit; bit; bit; bit; bit; bit; bit; bit_vector(0 bit_vector(0 bit_vector(0 bit_vector(0 bit; bit; bit; bit; bit; bit; bit; bit; bit;
to 1); to 1);
to to to to
3); 3); 2); 15);
MOTOROLA
DSP56367
C-1
JTAG BSDL
PCAP:linkage PGND:linkage AA:out CAS_:out EXTAL:in CVCC:linkage CGND:linkage TA_:in BR_:buffer BB_:inout WR_:out RD_:out BG_:in A:out AVCC:linkage AGND:linkage D:inout DVCC:linkage DGND:linkage MODD:in MODC:in MODB:in MODA:in MOSI:inout SDA:inout SDO41_1:inout SDO50_1:inout FST_1:inout FSR_1:inout SCKR_1:inout SCKT_1:inout
bit; bit; bit_vector(0 bit; bit; bit_vector(0 bit_vector(0 bit; bit; bit; bit; bit; bit; bit_vector(0 bit_vector(0 bit_vector(0 bit_vector(0 bit_vector(0 bit_vector(0 bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit);
to 2);
to 1); to 1);
to to to to to to
17); 2); 3); 23); 3); 3);
use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of DSP56367 : entity is "STD_1149_1_1993"; attribute PIN_MAP of DSP56367 : entity is PHYSICAL_PIN_MAP; constant TQFP144 : PIN_MAP_STRING := "SCK: 1, " & "SS_: 2, " & "HREQ_: 3, " & "SDO0: 4, " & "SDO1: 5, " & "SDOI23: 6, " & "SDOI32: 7, " & "SVCC: (8, 25), " & "SGND: (9, 26), " & "SDOI41: 10, " & "SDOI50: 11, " & "FST: 12, " & "FSR: 13, " & "SCKT: 14, " &
C-2
DSP56367
MOTOROLA
JTAG BSDL
"SCKR: "HSCKT: "HSCKR: "QVCC: "QGND: "QVCCH: "HP: "&
15, " & 16, " & 17, " & (18, 56, 91, 126), " & (19, 54, 90, 127), " & (20, 49, 95), " & (43, 42, 41, 40, 37, 36, 35, 34, 33, 32, 31, 22, 21, 30, 24, 23),
"ADO: 27, " & "ACI: 28, " & "TIO: 29, " & "HVCC: 38, " & "HGND: 39, " & "RESET_: 44, " & "PVCC: 45, " & "PCAP: 46, " & "PGND: 47, " & "SDO50_1: 48, " & "FST_1: 50, " & "AA: (70, 69, 51), " & "CAS_: 52, " & "SCKT_1: 53, " & "EXTAL: 55, " & "CVCC: (57, 65), " & "CGND: (58, 66), " & "FSR_1: 59, " & "SCKR_1: 60, " & "PINIT: 61, " & "TA_: 62, " & "BR_: 63, " & "BB_: 64, " & "WR_: 67, " & "RD_: 68, " & "BG_: 71, " & "A: (72, 73, 76, 77, 78, 79, 82, 83, 84, 85, 88, 89, 92, 93, 94, 97, 98, 99), " & "AVCC: (74, 80, 86), " & "AGND: (75, 81, 87, 96), " & "D: (100, 101, 102, 105, 106, 107, 108, 109, 110, 113, 114, 115, 116, 117, 118, 121, " & "122, 123, 124, 125, 128, 131, 132, 133), " & "DVCC: (103, 111, 119, 129), " & "DGND: (104, 112, 120, 130), " & "MODD: 134, " & "MODC: 135, " & "MODB: 136, " & "MODA: 137, " & "SDO41_1: 138, " & "TDO: 139, " & "TDI: 140, " & "TCK: 141, " & "TMS: 142, " & "MOSI: 143, " &
MOTOROLA
DSP56367
C-3
JTAG BSDL
"SDA: attribute attribute attribute attribute
144 "; TAP_SCAN_IN TAP_SCAN_OUT TAP_SCAN_MODE TAP_SCAN_CLOCK of of of of TDI TDO TMS TCK : : : : signal signal signal signal is is is is true; true; true; (20.0e6, BOTH);
attribute INSTRUCTION_LENGTH of DSP56367 : entity is 4; attribute INSTRUCTION_OPCODE of DSP56367 : entity is "EXTEST (0000)," & "SAMPLE (0001)," & "IDCODE (0010)," & "CLAMP (0101)," & "HIGHZ (0100)," & "ENABLE_ONCE (0110)," & "DEBUG_REQUEST(0111)," & "BYPASS (1111)"; attribute INSTRUCTION_CAPTURE of DSP56367 : entity is "0001"; attribute IDCODE_REGISTER of DSP56367 : entity is "0000" & -- version "000111" & -- manufacturer's use "0001001111" & -- sequence number "00000001110" & -- manufacturer identity "1"; -- 1149.1 requirement
attribute REGISTER_ACCESS of DSP56367 : entity is "ONCE[8] (ENABLE_ONCE,DEBUG_REQUEST)" ; attribute BOUNDARY_LENGTH of DSP56367 : entity is 152; attribute -- num "0 "1 "2 "3 "4 "5 "6 "7 "8 "9 "10 "11 "12 "13 "14 "15 "16 "17 BOUNDARY_REGISTER of DSP56367 : entity is cell port func safe [ccell dis rslt] (BC_1, *, control, 1)," & (BC_6, SDO41_1, bidir, X, 0, 1, Z)," (BC_1, MODA, input, X)," & (BC_1, MODB, input, X)," & (BC_1, MODC, input, X)," & (BC_1, MODD, input, X)," & (BC_6, D(23), bidir, 1, 15, 1, Z)," (BC_6, D(22), bidir, X, 15, 1, Z)," (BC_6, D(21), bidir, X, 15, 1, Z)," (BC_6, D(20), bidir, X, 15, 1, Z)," (BC_6, D(19), bidir, X, 15, 1, Z)," (BC_6, D(18), bidir, X, 15, 1, Z)," (BC_6, D(17), bidir, X, 15, 1, Z)," (BC_6, D(16), bidir, X, 15, 1, Z)," (BC_6, D(15), bidir, X, 15, 1, Z)," (BC_1, *, control, 1)," & (BC_6, D(14), bidir, X, 15, 1, Z)," (BC_6, D(13), bidir, X, 15, 1, Z),"
&
& & & & & & & & & & &
C-4
DSP56367
MOTOROLA
JTAG BSDL
"18 "19 -- num "20 "21 "22 "23 "24 "25 "26 "27 "28 "29 "30 "31 "32 "33 "34 "35 "36 "37 "38 "39 -- num "40 "41 "42 "43 "44 "45 "46 "47 "48 "49 "50 "51 "52 "53 "54 "55 "56 "57 "58 "59 -- num "60 "61 "62 "63 "64 "65 "66 "67
(BC_6, (BC_6, cell (BC_6, (BC_6, (BC_6, (BC_6, (BC_6, (BC_6, (BC_6, (BC_6, (BC_1, (BC_6, (BC_6, (BC_6, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, cell (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, cell (BC_6, (BC_1, (BC_1, (BC_1, (BC_1, (BC_6, (BC_1, (BC_6,
D(12), bidir, D(11), bidir, port func D(10), bidir, D(9), bidir, D(8), bidir, D(7), bidir, D(6), bidir, D(5), bidir, D(4), bidir, D(3), bidir, *, control, D(2), bidir, D(1), bidir, D(0), bidir, A(17), output3, A(16), output3, A(15), output3, *, control, A(14), output3, A(13), output3, A(12), output3, A(11), output3, port func A(10), output3, A(9), output3, A(8), output3, A(7), output3, A(6), output3, *, control, A(5), output3, A(4), output3, A(3), output3, A(2), output3, A(1), output3, A(0), output3, BG_, input, *, control, AA(0), output3, *, control, AA(1), output3, RD_, output3, WR_, output3, *, control, port func BB_, bidir, BR_, output2, TA_, input, PINIT, input, *, control, SCKR_1, bidir, *, control, FSR_1, bidir,
X, 15, 1, Z)," X, 28, 1, Z)," safe [ccell dis rslt] X, 28, 1, Z)," X, 28, 1, Z)," X, 28, 1, Z)," X, 28, 1, Z)," X, 28, 1, Z)," X, 28, 1, Z)," X, 28, 1, Z)," X, 28, 1, Z)," 1)," & X, 28, 1, Z)," X, 28, 1, Z)," X, 28, 1, Z)," X, 35, 1, Z)," X, 35, 1, Z)," X, 35, 1, Z)," 1)," & X, 35, 1, Z)," X, 35, 1, Z)," X, 35, 1, Z)," X, 35, 1, Z)," safe [ccell dis rslt] X, 35, 1, Z)," X, 35, 1, Z)," X, 45, 1, Z)," X, 45, 1, Z)," X, 45, 1, Z)," 1)," & X, 45, 1, Z)," X, 45, 1, Z)," X, 45, 1, Z)," X, 45, 1, Z)," X, 45, 1, Z)," X, 45, 1, Z)," X)," & 1)," & X, 53, 1, Z)," 1)," & X, 55, 1, Z)," X, 68, 1, Z)," X, 68, 1, Z)," 1)," & safe [ccell dis rslt] X, 59, 1, Z)," X)," & X)," & X)," & 1)," & X, 64, 1, Z)," 1)," & X, 66, 1, Z),"
& & & & & & & & & & & & & & & & & & & & & & & & & & & & & & &
& & & &
&
& &
MOTOROLA
DSP56367
C-5
JTAG BSDL
"68 "69 "70 "71 "72 "73 "74 "75 "76 "77 "78 "79 -- num "80 "81 "82 "83 "84 "85 "86 "87 "88 "89 "90 "91 "92 "93 "94 "95 "96 "97 "98 "99 -- num "100 "101 "102 "103 "104 "105 "106 "107 "108 "109 "110 "111 "112 "113 "114 "115 "116 "117 "118
(BC_1, (BC_1, (BC_1, (BC_6, (BC_1, (BC_1, (BC_1, (BC_1, (BC_1, (BC_6, (BC_1, (BC_6, cell (BC_1, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6,
*, control, EXTAL, input, *, control, SCKT_1, bidir, *, control, CAS_, output3, *, control, AA(2), output3, *, control, FST_1, bidir, *, control, SDO50_1, bidir, port func RESET_, input, *, control, HP(0), bidir, *, control, HP(1), bidir, *, control, HP(2), bidir, *, control, HP(3), bidir, *, control, HP(4), bidir, *, control, HP(5), bidir, *, control, HP(6), bidir, *, control, HP(7), bidir, *, control, HP(8), bidir, *, control, port func HP(9), bidir, *, control, HP(10), bidir, *, control, HP(13), bidir, *, control, TIO, bidir, *, control, ACI, bidir, *, control, ADO, bidir, *, control, HP(14), bidir, *, control, HP(15), bidir, *, control, HP(11), bidir, *, control, HP(12), bidir,
1)," & X)," & 1)," & X, 70, 1, Z)," 1)," & X, 72, 1, Z)," 1)," & X, 74, 1, Z)," 1)," & X, 76, 1, Z)," 1)," & X, 78, 1, Z)," safe [ccell dis rslt] X)," & 1)," & X, 81, 1, Z)," 1)," & X, 83, 1, Z)," 1)," & X, 85, 1, Z)," 1)," & X, 87, 1, Z)," 1)," & X, 89, 1, Z)," 1)," & X, 91, 1, Z)," 1)," & X, 93, 1, Z)," 1)," & X, 95, 1, Z)," 1)," & X, 97, 1, Z)," 1)," & safe [ccell dis rslt] X, 99, 1, Z)," 1)," & X, 101, 1, Z)," 1)," & X, 103, 1, Z)," 1)," & X, 105, 1, Z)," 1)," & X, 107, 1, Z)," 1)," & X, 109, 1, Z)," 1)," & X, 111, 1, Z)," 1)," & X, 113, 1, Z)," 1)," & X, 115, 1, Z)," 1)," & X, 117, 1, Z),"
& & & & &
& & & & & & & & &
& & & & & & & & & &
C-6
DSP56367
MOTOROLA
JTAG BSDL
"119 -- num "120 "121 "122 "123 "124 "125 "126 "127 "128 "129 "130 "131 "132 "133 "134 "135 "136 "137 "138 "139 -- num "140 "141 "142 "143 "144 "145 "146 "147 "148 "149 "150 "151 end DSP56367;
(BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, cell (BC_6, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_1, (BC_6, (BC_1, (BC_6, (BC_1, (BC_6,
*, control, port func HSCKR, bidir, *, control, HSCKT, bidir, *, control, SCKR, bidir, *, control, SCKT, bidir, *, control, FSR, bidir, *, control, FST, bidir, *, control, SDOI50, bidir, *, control, SDOI41, bidir, *, control, SDOI32, bidir, *, control, SDOI23, bidir, *, control, port func SDO1, bidir, *, control, SDO0, bidir, *, control, HREQ_, bidir, SS_, input, *, control, SCK, bidir, *, control, SDA, bidir, *, control, MOSI, bidir,
1)," & safe [ccell dis rslt] X, 119, 1, Z)," 1)," & X, 121, 1, Z)," 1)," & X, 123, 1, Z)," 1)," & X, 125, 1, Z)," 1)," & X, 127, 1, Z)," 1)," & X, 129, 1, Z)," 1)," & X, 131, 1, Z)," 1)," & X, 133, 1, Z)," 1)," & X, 135, 1, Z)," 1)," & X, 137, 1, Z)," 1)," & safe [ccell dis rslt] X, 139, 1, Z)," 1)," & X, 141, 1, Z)," 1)," & X, 143, 1, Z)," X)," & 1)," & X, 146, 1, Z)," 1)," & X, 148, 1, Z)," 1)," & X, 150, 1, Z)";
& & & & & & & & & &
& & &
& &
MOTOROLA
DSP56367
C-7
JTAG BSDL
C-8
DSP56367
MOTOROLA
APPENDIX
D
PROGRAMMER'S REFERENCE
D.1 INTRODUCTION
This section has been compiled as a reference for programmers. It contains a table showing the addresses of all the DSPs memory-mapped peripherals, an interrupt address table, an interrupt exception priority table, a quick reference to the host interface, and programming sheets for the major programmable registers on the DSP.
D.1.1
Peripheral Addresses
Table D-1 lists the memory addresses of all on-chip peripherals.
D.1.2
Interrupt Addresses
Table D-2 lists the interrupt starting addresses and sources.
D.1.3
Interrupt Priorities
Table D-3 lists the priorities of specific interrupts within interrupt priority levels.
D.1.4
Host Interface Quick Reference
Table D-4 is a quick reference guide to the host interface (HDI08).
D.1.5
Programming Sheets
The remaining figures describe major programmable registers on the DSP56367.
MOTOROLA
DSP56367
D-1
Programmer's Reference
D.2
INTERNAL I/O MEMORY MAP
Table D-1 Internal I/O Memory Map
Peripheral IPR PLL ONCE BIU
Address X:$FFFFFF X:$FFFFFE X:$FFFFFD X:$FFFFFC X:$FFFFFB X:$FFFFFA X:$FFFFF9 X:$FFFFF8 X:$FFFFF7 X:$FFFFF6 X:$FFFFF5
Register Name INTERRUPT PRIORITY REGISTER CORE (IPR-C) INTERRUPT PRIORITY REGISTER PERIPHERAL (IPR-P) PLL CONTROL REGISTER (PCTL) ONCE GDB REGISTER (OGDB) BUS CONTROL REGISTER (BCR) DRAM CONTROL REGISTER (DCR) ADDRESS ATTRIBUTE REGISTER 0 (AAR0) ADDRESS ATTRIBUTE REGISTER 1 (AAR1) ADDRESS ATTRIBUTE REGISTER 2 (AAR2) ADDRESS ATTRIBUTE REGISTER 3 (AAR3) [pin not available] ID REGISTER (IDR) DMA STATUS REGISTER (DSTR) DMA OFFSET REGISTER 0 (DOR0) DMA OFFSET REGISTER 1 (DOR1) DMA OFFSET REGISTER 2 (DOR2) DMA OFFSET REGISTER 3 (DOR3) DMA SOURCE ADDRESS REGISTER (DSR0) DMA DESTINATION ADDRESS REGISTER (DDR0) DMA COUNTER (DCO0) DMA CONTROL REGISTER (DCR0) DMA SOURCE ADDRESS REGISTER (DSR1) DMA DESTINATION ADDRESS REGISTER (DDR1) DMA COUNTER (DCO1) DMA CONTROL REGISTER (DCR1) DMA SOURCE ADDRESS REGISTER (DSR2) DMA DESTINATION ADDRESS REGISTER (DDR2) DMA COUNTER (DCO2) DMA CONTROL REGISTER (DCR2) DMA SOURCE ADDRESS REGISTER (DSR3) DMA DESTINATION ADDRESS REGISTER (DDR3) DMA COUNTER (DCO3) DMA CONTROL REGISTER (DCR3) DMA SOURCE ADDRESS REGISTER (DSR4) DMA DESTINATION ADDRESS REGISTER (DDR4) DMA COUNTER (DCO4) DMA CONTROL REGISTER (DCR4) DMA SOURCE ADDRESS REGISTER (DSR5) DMA DESTINATION ADDRESS REGISTER (DDR5) DMA COUNTER (DCO5) DMA CONTROL REGISTER (DCR5) PORT D CONTROL REGISTER (PCRD) PORT D DIRECTION REGISTER (PRRD) PORT D DATA REGISTER (PDRD)
DMA
X:$FFFFF4 X:$FFFFF3 X:$FFFFF2 X:$FFFFF1 X:$FFFFF0
DMA0
X:$FFFFEF X:$FFFFEE X:$FFFFED X:$FFFFEC
DMA1
X:$FFFFEB X:$FFFFEA X:$FFFFE9 X:$FFFFE8
DMA2
X:$FFFFE7 X:$FFFFE6 X:$FFFFE5 X:$FFFFE4
DMA3
X:$FFFFE3 X:$FFFFE2 X:$FFFFE1 X:$FFFFE0
DMA4
X:$FFFFDF X:$FFFFDE X:$FFFFDD X:$FFFFDC
DMA5
X:$FFFFDB X:$FFFFDA X:$FFFFD9 X:$FFFFD8
PORT D
X:$FFFFD7 X:$FFFFD6 X:$FFFFD5
D-2
DSP56367
MOTOROLA
Programmer's Reference
Table D-1 Internal I/O Memory Map (Continued)
Peripheral DAX Address X:$FFFFD4 X:$FFFFD3 X:$FFFFD2 X:$FFFFD1 X:$FFFFD0 X:$FFFFCF X:$FFFFCE X:$FFFFCD X:$FFFFCC X:$FFFFCB X:$FFFFCA PORT B HDI08 X:$FFFFC9 X:$FFFFC8 X:$FFFFC7 X:$FFFFC6 X:$FFFFC5 X:$FFFFC4 X:$FFFFC3 X:$FFFFC2 X:$FFFFC1 X:$FFFFC0 PORT C X:$FFFFBF X:$FFFFBE X:$FFFFBD DAX STATUS REGISTER (XSTR) DAX AUDIO DATA REGISTER B (XADRB) DAX AUDIO DATA REGISTER A (XADRA) DAX NON-AUDIO DATA REGISTER (XNADR) DAX CONTROL REGISTER (XCTR) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED HOST PORT GPIO DATA REGISTER (HDR) HOST PORT GPIO DIRECTION REGISTER (HDDR) HOST TRANSMIT REGISTER (HOTX) HOST RECEIVE REGISTER (HORX) HOST BASE ADDRESS REGISTER (HBAR) HOST PORT CONTROL REGISTER (HPCR) HOST STATUS REGISTER (HSR) HOST CONTROL REGISTER (HCR) RESERVED RESERVED PORT C CONTROL REGISTER (PCRC) PORT C DIRECTION REGISTER (PRRC) PORT C GPIO DATA REGISTER (PDRC) Register Name
MOTOROLA
DSP56367
D-3
Programmer's Reference
Table D-1 Internal I/O Memory Map (Continued)
Peripheral ESAI Address X:$FFFFBC X:$FFFFBB X:$FFFFBA X:$FFFFB9 X:$FFFFB8 X:$FFFFB7 X:$FFFFB6 X:$FFFFB5 X:$FFFFB4 X:$FFFFB3 X:$FFFFB2 X:$FFFFB1 X:$FFFFB0 X:$FFFFAF X:$FFFFAE X:$FFFFAD X:$FFFFAC X:$FFFFAB X:$FFFFAA X:$FFFFA9 X:$FFFFA8 X:$FFFFA7 X:$FFFFA6 X:$FFFFA5 X:$FFFFA4 X:$FFFFA3 X:$FFFFA2 X:$FFFFA1 X:$FFFFA0 X:$FFFF9F X:$FFFF9E X:$FFFF9D X:$FFFF9C X:$FFFF9B X:$FFFF9A X:$FFFF99 X:$FFFF98 X:$FFFF97 X:$FFFF96 X:$FFFF95 SHI X:$FFFF94 X:$FFFF93 X:$FFFF92 X:$FFFF91 X:$FFFF90 Register Name ESAI RECEIVE SLOT MASK REGISTER B (RSMB) ESAI RECEIVE SLOT MASK REGISTER A (RSMA) ESAI TRANSMIT SLOT MASK REGISTER B (TSMB) ESAI TRANSMIT SLOT MASK REGISTER A (TSMA) ESAI RECEIVE CLOCK CONTROL REGISTER (RCCR) ESAI RECEIVE CONTROL REGISTER (RCR) ESAI TRANSMIT CLOCK CONTROL REGISTER (TCCR) ESAI TRANSMIT CONTROL REGISTER (TCR) ESAI COMMON CONTROL REGISTER (SAICR) ESAI STATUS REGISTER (SAISR) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ESAI RECEIVE DATA REGISTER 3 (RX3) ESAI RECEIVE DATA REGISTER 2 (RX2) ESAI RECEIVE DATA REGISTER 1 (RX1) ESAI RECEIVE DATA REGISTER 0 (RX0) RESERVED ESAI TIME SLOT REGISTER (TSR) ESAI TRANSMIT DATA REGISTER 5 (TX5) ESAI TRANSMIT DATA REGISTER 4 (TX4) ESAI TRANSMIT DATA REGISTER 3 (TX3) ESAI TRANSMIT DATA REGISTER 2 (TX2) ESAI TRANSMIT DATA REGISTER 1 (TX1) ESAI TRANSMIT DATA REGISTER 0 (TX0) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SHI RECEIVE FIFO (HRX) SHI TRANSMIT REGISTER (HTX) SHI I2C SLAVE ADDRESS REGISTER (HSAR) SHI CONTROL/STATUS REGISTER (HCSR) SHI CLOCK CONTROL REGISTER (HCKR)
D-4
DSP56367
MOTOROLA
Programmer's Reference
Table D-1 Internal I/O Memory Map (Continued)
Peripheral TRIPLE TIMER Address X:$FFFF8F X:$FFFF8E X:$FFFF8D X:$FFFF8C X:$FFFF8B X:$FFFF8A X:$FFFF89 X:$FFFF88 X:$FFFF87 X:$FFFF86 X:$FFFF85 X:$FFFF84 X:$FFFF83 X:$FFFF82 X:$FFFF81 X:$FFFF80 ESAI MUX PIN CONTROL Y:$FFFFAF Y:$FFFFAE Y:$FFFFAD Y:$FFFFAC Y:$FFFFAB Y:$FFFFAA Y:$FFFFA9 Y:$FFFFA8 Y:$FFFFA7 Y:$FFFFA6 Y:$FFFFA5 Y:$FFFFA4 Y:$FFFFA3 Y:$FFFFA2 Y:$FFFFA1 Y:$FFFFA0 PORT E Y:$FFFF9F Y:$FFFF9E Y:$FFFF9D Register Name TIMER 0 CONTROL/STATUS REGISTER (TCSR0) TIMER 0 LOAD REGISTER (TLR0) TIMER 0 COMPARE REGISTER (TCPR0) TIMER 0 COUNT REGISTER (TCR0) TIMER 1 CONTROL/STATUS REGISTER (TCSR1) TIMER 1 LOAD REGISTER (TLR1) TIMER 1 COMPARE REGISTER (TCPR1) TIMER 1 COUNT REGISTER (TCR1) TIMER 2 CONTROL/STATUS REGISTER (TCSR2) TIMER 2 LOAD REGISTER (TLR2) TIMER 2 COMPARE REGISTER (TCPR2) TIMER 2 COUNT REGISTER (TCR2) TIMER PRESCALER LOAD REGISTER (TPLR) TIMER PRESCALER COUNT REGISTER (TPCR) RESERVED RESERVED ESAI MUX PIN CONTROL REGISTER (EMUXR) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED PORT E CONTROL REGISTER (PCRE) PORT E DIRECTION REGISTER(PRRE) PORT E GPIO DATA REGISTER(PDRE)
MOTOROLA
DSP56367
D-5
Programmer's Reference
Table D-1 Internal I/O Memory Map (Continued)
Peripheral ESAI_1 Address Y:$FFFF9C Y:$FFFF9B Y:$FFFF9A Y:$FFFF99 Y:$FFFF98 Y:$FFFF97 Y:$FFFF96 Y:$FFFF95 Y:$FFFF94 Y:$FFFF93 Y:$FFFF92 Y:$FFFF91 Y:$FFFF90 Y:$FFFF8F Y:$FFFF8E Y:$FFFF8D Y:$FFFF8C Y:$FFFF8B Y:$FFFF8A Y:$FFFF89 Y:$FFFF88 Y:$FFFF87 Y:$FFFF86 Y:$FFFF85 Y:$FFFF84 Y:$FFFF83 Y:$FFFF82 Y:$FFFF81 Y:$FFFF80 Register Name ESAI_1 RECEIVE SLOT MASK REGISTER B (RSMB_1) ESAI_1 RECEIVE SLOT MASK REGISTER A (RSMA_1) ESAI_1 TRANSMIT SLOT MASK REGISTER B (TSMB_1) ESAI_1 TRANSMIT SLOT MASK REGISTER A (TSMA_1) ESAI_1 RECEIVE CLOCK CONTROL REGISTER (RCCR_1) ESAI_1 RECEIVE CONTROL REGISTER (RCR_1) ESAI_1 TRANSMIT CLOCK CONTROL REGISTER (TCCR_1) ESAI_1 TRANSMIT CONTROL REGISTER (TCR_1) ESAI_1 COMMON CONTROL REGISTER (SAICR_1) ESAI_1 STATUS REGISTER (SAISR_1) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED ESAI_1 RECEIVE DATA REGISTER 3 (RX3_1) ESAI_1 RECEIVE DATA REGISTER 2 (RX2_1) ESAI_1 RECEIVE DATA REGISTER 1 (RX1_1) ESAI_1 RECEIVE DATA REGISTER 0 (RX0_1) RESERVED ESAI_1 TIME SLOT REGISTER (TSR_1) ESAI_1 TRANSMIT DATA REGISTER 5 (TX5_1) ESAI_1 TRANSMIT DATA REGISTER 4 (TX4_1) ESAI_1 TRANSMIT DATA REGISTER 3 (TX3_1) ESAI_1 TRANSMIT DATA REGISTER 2 (TX2_1) ESAI_1 TRANSMIT DATA REGISTER 1 (TX1_1) ESAI_1 TRANSMIT DATA REGISTER 0 (TX0_1)
D-6
DSP56367
MOTOROLA
Programmer's Reference
D.3
INTERRUPT VECTOR ADDRESSES
Table D-2 DSP56367 Interrupt Vectors
Interrupt Starting Address
Interrupt Priority Level Range 3 3 3 3 3 3 3 3 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Non-Maskable Interrupt (NMI)
Interrupt Source
VBA:$00 VBA:$02 VBA:$04 VBA:$06 VBA:$08 VBA:$0A VBA:$0C VBA:$0E VBA:$10 VBA:$12 VBA:$14 VBA:$16 VBA:$18 VBA:$1A VBA:$1C VBA:$1E VBA:$20 VBA:$22 VBA:$24 VBA:$26 VBA:$28 VBA:$2A VBA:$2C VBA:$2E VBA:$30 VBA:$32 VBA:$34 VBA:$36 VBA:$38 VBA:$3A VBA:$3C
Reserved For Future Level-3 Interrupt Source Reserved For Future Level-3 Interrupt Source IRQA IRQB IRQC IRQD DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 DMA Channel 4 DMA Channel 5 Reserved Reserved DAX Underrun Error DAX Block Transferred Reserved DAX Audio Data Empty ESAI Receive Data ESAI Receive Even Data ESAI Receive Data With Exception Status ESAI Receive Last Slot ESAI Transmit Data ESAI Transmit Even Data ESAI Transmit Data with Exception Status
MOTOROLA
DSP56367
D-7
Programmer's Reference
Table D-2 DSP56367 Interrupt Vectors (Continued)
Interrupt Starting Address Interrupt Priority Level Range 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 0-2 ESAI Transmit Last Slot SHI Transmit Data SHI Transmit Underrun Error SHI Receive FIFO Not Empty Reserved SHI Receive FIFO Full SHI Receive Overrun Error SHI Bus Error Reserved Reserved Reserved TIMER0 Compare TIMER0 Overflow TIMER1 Compare TIMER1 Overflow TIMER2 Compare TIMER2 Overflow Host Receive Data Full Host Transmit Data Empty Host Command (Default) Reserved Reserved Reserved Reserved Reserved ESAI_1 Receive Data ESAI_1 Receive Even Data ESAI_1 Receive Data With Exception Status ESAI_1 Receive Last Slot ESAI_1 Transmit Data ESAI_1 Transmit Even Data ESAI_1 Transmit Data with Exception Status ESAI_1 Transmit Last Slot Interrupt Source
VBA:$3E VBA:$40 VBA:$42 VBA:$44 VBA:$46 VBA:$48 VBA:$4A VBA:$4C VBA:$4E VBA:$50 VBA:$52 VBA:$54 VBA:$56 VBA:$58 VBA:$5A VBA:$5C VBA:$5E VBA:$60 VBA:$62 VBA:$64 VBA:$66 VBA:$68 VBA:$6A VBA:$6C VBA:$6E VBA:$70 VBA:$72 VBA:$74 VBA:$76 VBA:$78 VBA:$7A VBA:$7C VBA:$7E
D-8
DSP56367
MOTOROLA
Programmer's Reference
Table D-2 DSP56367 Interrupt Vectors (Continued)
Interrupt Starting Address Interrupt Priority Level Range 0-2 : 0-2 Reserved : Reserved Interrupt Source
VBA:$80 : VBA:$FE
MOTOROLA
DSP56367
D-9
Programmer's Reference
D.4
INTERRUPT SOURCE PRIORITIES (WITHIN AN IPL)
Table D-3 Interrupt Sources Priorities Within an IPL
Priority Interrupt Source
Level 3 (Nonmaskable) Highest Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Lowest Levels 0, 1, 2 (Maskable) Highest IRQA (External Interrupt) IRQB (External Interrupt) IRQC (External Interrupt) IRQD (External Interrupt) DMA Channel 0 Interrupt DMA Channel 1 Interrupt DMA Channel 2 Interrupt DMA Channel 3 Interrupt DMA Channel 4 Interrupt DMA Channel 5 Interrupt ESAI Receive Data with Exception Status ESAI Receive Even Data ESAI Receive Data ESAI Receive Last Slot ESAI Transmit Data with Exception Status ESAI Transmit Last Slot ESAI Transmit Even Data ESAI Transmit Data SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data SHI Receive FIFO Not Empty HOST Command Interrupt Non-Maskable Interrupt
D-10
DSP56367
MOTOROLA
Programmer's Reference
Table D-3 Interrupt Sources Priorities Within an IPL (Continued)
Priority HOST Receive Data Interrupt HOST Transmit Data Interrupt DAX Transmit Underrun Error DAX Block Transferred DAX Transmit Register Empty TIMER0 Overflow Interrupt TIMER0 Compare Interrupt TIMER1 Overflow Interrupt TIMER1 Compare Interrupt TIMER2 Overflow Interrupt TIMER2 Compare Interrupt ESAI_1 Receive Data with Exception Status ESAI_1 Receive Even Data ESAI_1 Receive Data ESAI_1 Receive Last Slot ESAI_1 Transmit Data with Exception Status ESAI_1 Transmit Last Slot ESAI_1 Transmit Even Data Lowest ESAI_1 Transmit Data Interrupt Source
MOTOROLA
DSP56367
D-11
Programmer's Reference
D.5
HOST INTERFACE--QUICK REFERENCE
Table D-4 HDI08 Programming Model
Bit Reset Type Val Function Comments HW / SW 0 0 0 0 0 000 IR ST
Reg
Num Mnemonic
Name
DSP SIDE
HCR 0 1 2 3 4 7-5 HRIE HTIE HCIE HF2 HF3 HDM[2:0] Receive Interrupt Enable Transmit Interrupt Enable Host Command Interrupt Enable Host Flag 2 Host Flag 3 Host DMA Mode 0 1 0 1 0 1 HRRQ interrupt disabled HRRQ interrupt enabled HTRQ interrupt disabled HTRQ interrupt enabled HCP interrupt disabled HCP interrupt enabled -
-
-
000 100 001 010 011 101 110 111
DMA operation disabled DMA operation enabled 24-bit host-to-DSP DMA enabled 16-bit host-to-DSP DMA enabled 8-bit host-to-DSP DMA enabled 24-bit DSP-to-host DMA enabled 16-bit DSP-to-host DMA enabled 8-bit DSP-to-host DMA enabled
D-12
DSP56367
MOTOROLA
Programmer's Reference
Table D-4 HDI08 Programming Model
Bit Reg HPCR Num Mnemonic 0 1 HGEN HA8EN Name Host GPIO Enable Host Address Line 8 Enable Val 0 1 0 1 2 HA9EN Host Address Line 9 Enable 0 1 3 4 HCSEN HREN Host Chip Select Enable Host Request Enable 0 1 0 1 5 HAEN Host Acknowledge Enable 0 Function GPIO pin disconnected GPIO pins active HA8/HA1 = GPIO HA8/HA1 = HA8/HA1 HA9/HA2 = GPIO HA9/HA2 = HA9/HA2 HCS/HA10 = GPIO HCS/HA10 = HCS/HA10 HOREQ/HTRQ = GPIO HACK/HRRQ=GPIO
HOREQ/HTRQ=HOREQ/HTRQ HACK/HRRQ=HACK/HRRQ
Reset Type Comments HW / SW 0 this bit is treated as 1 if HMUX=0 this bit is treated as 0 if HEN=0 this bit is treated as 1 if HMUX=0 this bit is treated as 0 if HEN=0 this bit is treated as 0 if HEN=0 this bit is treated as 0 if HEN=0 0 IR ST -
0
-
-
0 0
-
-
HACK/HRRQ = GPIO
1
HACK/HRRQ= HACK
this bit is ignored if HDRQ=1 this bit is treated as 0 if HREN=0 this bit is treated as 0 if HEN=0
0
-
-
6 8 9 10 11 12
HEN HROD HDSP HASP HMUX HDDS
Host Enable Host Request Open Drain Host Data Strobe Polarity Host Address Strobe Polarity Host Multiplxed Bus Host Dual Data Strobe
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Host Port=GPIO Host Port Active
HOREQ/HTRQ/HRRQ=driven HOREQ/HTRQ/HRRQ=open drain
0 this bit is ignored if HEN=0 0 0 0 0 0
-
-
13 14
HCSP HRP
Host Chip Select Polarity Host Request polarity
15 HSR 0 1 2 3 4 7 HBAR 7-0
HAP HRDF HTDE HCP HF0 HF1 DMA
Host Acknowledge Polarity Host Receive Data Full Host Transmit Data Empty Host Command Pending Host Flag0 Host Flag1 DMA Status
0 1 0 1 1 0 0 1
HDS/HRD/HWR active low this bit is ignored if HDS/HRD/HWR active high HEN=0 HAS active low this bit is ignored if HAS active high HEN=0 Seprate address and data lines this bit is ignored if Multiplexed address/data HEN=0 Single Data Strobe (HDS) this bit is ignored if Double Data Strobe (HWR, HEN=0 HRD) HCS active low this bit is ignored if HCSactive high HEN=0 HOREQ/HTRQ/HRRQ this bit is ignored if active low HEN=0 HOREQ/HTRQ/HRRQ active high HACK active low this bit is ignored if HACK active high HEN=0 no receive data to be read receive data register is full transmit data register empty transmit data reg. not empty no host command pending host command pending
0 0
-
-
0 0 1 0 0 0 0 $80
0 1 0 -
0 1 0 -
0 1
DMA mode disabled DMA mode enabled
BA10-BA3 Host base Address Register
MOTOROLA
DSP56367
D-13
Programmer's Reference
Table D-4 HDI08 Programming Model
Bit Reg Num Mnemonic Name Val Function Comments Reset Type HW / SW IR empty empty $0000 $0000 ST
HORX 23-0 HOTX 23-0 HDR 15-0 HDDR 15-0
DSP Receive Data Register DSP Transmit Data Register D15-D0 GPIO Pin Data DR15-DR0 GPIO Pin Direction
0 1 0 1 0 1 0 1
ICR
0 1 2
RREQ TREQ HDRQ
Receive Request Enable Transmit Request Enable Double Host Request
Input Output Host Side HRRQ interrupt disabled HRRQ interrupt enabled HTRQ interrupt disabled HTRQ interrupt enabled HOREQ/HTRQ=HOREQ, HACK/HRRQ=HACK HOREQ/HTRQ=HTRQ, HACK/HRRQ=HRRQ
0 0 available if HDM2-HDM0=000 0
-
-
3 4 5 6-5
HF0 HF1 HLEND
Host Flag 0 Host Flag 1 Host Little Endian
HM1-HM0 Host Mode Control
7 ISR 0 1 2
INIT RXDF TXDE TRDY
Initialize Receive Data Register Full Transmit Data Register Empty Transmitter Ready
0 1 00 01 10 11 1 0 1 1 0 1 0
"Big Endian" order "Little Endian" order Interrupt Mode 24-bit DMA enabled 16-bit DMA enabled 8-bit DMA enabled Reset data paths according to TREQ and RREQ host receive register is empty host receive register is full host transmit register empty host transmit register full transmit FIF O (6 deep) is empty transmit FIFO is not empty
available if HDM2-HDM0=000 available if HDM2-HDM0=100
0 0 0 00
-
-
cleared by HDI08 hardware
0 0 1 1
0 1 1
0 1 1
3 4 7
HF2 HF3 HREQ
Host Flag2 Host Flag3 Host Request
0 1
HOREQ pin is deasserted HOREQ pin is asserted (if enabled) no host command pending host command pending default vector cleared by HDI08 hardware when the HC int. req. is serviced
0 0 0
0
0
CVR
6-0 7
HV6-HV0 HC
Host Command Vector Host Command
0 1
$2A 0
0
0
RXH/ M/L TXH/ M/L IVR
7-0 7-0 7-0 IV7-IV0
Host Receive Data Register Host Transmit Data Register Interrupt Register
empty empty 68000 family vector register $0F -
D-14
DSP56367
MOTOROLA
Programmer's Reference
D.6
PROGRAMMING SHEETS
The worksheets shown on the following pages contain listings of major programmable registers for the DSP56367. The programming sheets are grouped into the following order: * * * * * * * Central Processor Host Interface (HDI08) Serial Host Interface (SHI) Two Enhanced Serial Audio Interfaces (ESAI and ESAI_1) Digital Audio Interface (DAX) Timer/Event Controller (TEC) GPIO (Ports B-E)
Each sheet provides room to write in the value of each bit and the hexadecimal value for each register. Programmers can photocopy these sheets and reuse them for each application development project. For details on the instruction set of the DSP56300 family chips, see the DSP56300 Family Manual.
MOTOROLA
DSP56367
D-15
Programmer's Reference
Application:
Date: Programmer: Sheet 1 of 5
Central Processor
Unnormalized ( U = Acc(47) xnor Acc(46) ) Extension Limit FFT Scaling ( S = Acc(46) xor Acc(45) )
Scaling Mode S(1:0) Scaling Mode 00 No scaling 01 Scale down 10 Scale up 11 Reserved I(1:0) 00 01 10 11
Carry Overfow Zero Negative
Interrupt Mask Exceptions Masked None IPL 0 IPL 0, 1 IPL 0, 1, 2
Reserved Sixteen-Bit Compatibilitity Double Precision Multiply Mode Loop Flag DO-Forever Flag Sixteenth-Bit Arithmetic Reserved Instruction Cache Enable Arithmetic Saturation Rounding Mode
Core Priority CP(1:0) Core Priority 00 0 (lowest) 1 01 10 2 11 3 (highest)
23 22
21 20 19 18 17 16 15 14 13 12
CE
11 10
S1 S0
9
I1
8
I0
7
S
6
L
5
E
4
U
3
N
2
Z
1
V
0
C
CP1 CP0 RM SM
* 0
SA
FV
LF
DM
SC
* 0
Extended Mode Register (MR) Status Register (SR) Read/Write
Mode Register (MR) Reset = $C00300
Condition Code Register (CCR)
* = Reserved, Program as 0
Figure D-1 Status Register (SR)
D-16
DSP56367
MOTOROLA
Programmer's Reference
Application:
Date:
Programmer: Sheet 2 of 5
Central Processor
Chip Operating Modes MOD(D:A) Reset Vector Description See Core Configuration Section.
External Bus Disable Stop Delay Memory Switch Mode
CDP(1:0) 00 01 10 11 Core-DMA Priority Core-DMA Priority Core vs DMA Priority DMA accesses > Core DMA accesses = Core DMA accesses < Core
Burst Mode Enable TA Synchronize Select Bus Release Timing Asynchronous Bus Arbitration Enable Address Priority Disable Address Tracing Enable Stack Extension Space Select Extended Stack Underflow Flag Extended Stack Overflow Flag Extended Stack Wrap Flag Stack Extension Enable Memory Switch Mode Patch Enable
23 22
PEN
21 20 19 18 17 16 15 14 13 12
11 10
9
8
7
6
SD
5
4
3
2
1
0
MA
MSW1 MSW0
SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CDP1CDP0 MS
* 0
EBD MD MC MB
System Stack Control Status Register (SCS) Operating Mode Register (OMR)
Extended Chip Operating Mode Register (COM) Read/Write Reset = $00030X
Chip Operating Mode Register (COM)
* = Reserved, Program as 0
Figure D-2 Operating Mode Register (OMR)
MOTOROLA
DSP56367
D-17
D-18
Figure D-3 Interrupt Priority Register-Core (IPR-C)
Application:
CENTRAL PROCESSOR
IRQC Mode
ICL2 0 1 Trigger Level Neg. Edge ICL1 0 0 1 1 ICL0 0 1 0 1 Enabled No Yes Yes Yes IPL -- 0 1 2 IAL2 0 1 Trigger Level Neg. Edge
Programmer's Reference
IRQA Mode
IAL1 0 0 1 1 IAL0 0 1 0 1 Enabled No Yes Yes Yes IPL -- 0 1 2
IRQD Mode
IDL2 0 1 Trigger Level Neg. Edge IDL1 0 0 1 1 IDL0 0 1 0 1 Enabled No Yes Yes Yes IPL -- 0 1 2 IBL2 0 1 Trigger Level Neg. Edge
IRQB Mode
IBL1 0 0 1 1 IBL0 0 1 0 1 Enabled No Yes Yes Yes IPL -- 0 1 2
DSP56367 MOTOROLA
Date:
23 22 21 20 19 18 17 16 15 14 13 12 11 10 Interrupt Priority Register (IPR-C) X:$FFFFFF R/W Reset = $000000
9
8
7
6
5
4
3
2
1
0
Programmer: Sheet 3 of 5
D5L1 D5L0 D4L1 D4L0 D3L1 D3L0 D2L1 D2L0 D1L1 D1L0 D0L1D0L0 IDL2 IDL1 IDL0 ICL2 ICL1 ICL0 IBL2 IBL1 IBL0 IAL2 IAL1 IAL0
Application:
MOTOROLA DSP56367 D-19
CENTRAL PROCESSOR
ESAI_1 IPL
ESL1 ESL0 Enabled 0 0 No 0 1 Yes 1 0 Yes 1 1 Yes IPL -- 0 1 2
HDI08 IPL
HDL1 HDL0 Enabled 0 0 No 0 1 Yes 1 0 Yes 1 1 Yes IPL -- 0 1 2
ESAI IPL
ESL1 ESL0 Enabled 0 0 No 0 1 Yes 1 0 Yes 1 1 Yes IPL -- 0 1 2
TEC IPL
TAL1 0 0 1 1 TAL0 0 1 0 1 Enabled No Yes Yes Yes IPL -- 0 1 2 DAL1 0 0 1 1
DAX IPL
DAL0 0 1 0 1 Enabled No Yes Yes Yes IPL -- 0 1 2
SHI IPL
SHL1 SHL0 Enabled 0 0 No 0 1 Yes 1 0 Yes 1 1 Yes IPL -- 0 1 2
Date:
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Programmer:
Figure D-4 Interrupt Priority Register - Peripherals (IPR-P)
************ 000000000000
$0 $0 $0
ESL11 ESL10 TAL1 TAL0 DAL1 DAL0 HDL1 HDL0 SHL1 SHL0 ESL1 ESL0
Interrupt Priority Register (IPR-P) X:$FFFFFE R/W Reset = $000000
Programmer's Reference
Sheet 4 of 5
* = Reserved, Program as 0
D-20
Figure D-5 Phase Lock Loop Control Register (PCTL)
Application:
PLL
PSTP 0 1 1
PEN x 0 1
PSTP and PEN Relationship Operation During STOP Recovery Time for STOP PLL Oscillator Disabled Disabled Long Disabled Enabled Short Enabled Enabled Short
Power Consumption during STOP Minimal Lower Higher
XTAL Disable Bit (XTLD) 0 = Enable Xtal Oscillator 1 = EXTAL Driven From An External Source
Programmer's Reference
Clock Output Disable (COD) 0 = 50% Duty Cycle Clock 1 = Pin Held In High State
Crystal Range Bit (XTLR) 0 = External Xtal Freq >200KHz 1 = External Xtal Freq <200KHz
Multiplication Factor Bits MF0 - MF11 MF11 - MF0 Multiplication Factor MF $000 1 $001 2 $002 3 * * * * * * $FFE 4095 $FFF 4096
DSP56367 MOTOROLA
Predivision Factor Bits (PD0 - PD3) PD3 - PD0 Predivision Factor PDF $0 1 $1 2 $2 3 * * * * * * $F 16 Note that bits XTLR, COD and XTLD have no effect on DSP56367 operation
Division Factor Bits (DF0 - DF2) DF2 - DF0 Division Factor DF $0 20 $1 21 $2 22 * * * * * * $7 27
Date:
Programmer:
23 22 21 20 19 18 17 16 15 14 13 12 11 10
PLL Control Register (PCTL) X:$FFFFFD Read/Write Reset = $010005
PD3 PD2 PD1 PD0 COD PEN PSTP XTLD XTLR DF2 DF1
9
8
7
6
5
4
3
2
1
0 Sheet 5 of 5
DF0 MF11 MF10 MF9 MF8
MF7 MF6 MF5 MF4 MF3 MF2
MF1 MF0
Programmer's Reference
Application:
Date: Programmer: Sheet 1 of 6
HOST (HDI08)
23 22 21 20 19 18 17 16 15 14 13 12
Receive High Byte
DSP Side
11 10 9 8 7 6 5 4 3 2 1 0
Receive Middle Byte Receive Low Byte
Host Receive Data (usually read by program)
Host Receive Register (HORX) X:$FFFEC6 Read Only Reset = empty Host Transmit Data (usually loaded by program)
23 22
21 20 19 18 17 16 15 14 13 12
Transmit High Byte
11 10
9
8
7
6
5
4
3
2
1
0
Transmit Middle Byte
Transmit Low Byte
Host Transmit Register (HOTX) X:$FFFEC7 Write Only Reset = empty
Figure D-6 Host Receive and Host Transmit Data Registers
MOTOROLA
DSP56367
D-21
Programmer's Reference
Application:
Date: Programmer: Sheet 2 of 6
HOST (HDI08)
Host Receive Interrupt Enable 0 = Disable 1 = Enable if HRDF = 1 Host Transmit Interrupt Enable 0 = Disable 1 = Enable if HTDE = 1 Host Command Interrupt Enable 0 = Disable 1 = Enable if HCP = 1 Host Flag 2 Host Flag 3 Host DMA Control Bits See Table 6-5 in Section 6 Host Control Register (HCR) X:$FFFFC2 Read /Write Reset = $0
15
8
7
6
5
4
3
HF2
2
1
0
HRIE
** 00
HDM2 HDM1 HDM0 HF3
HCIE HTIE
DSP Side
Host Receive Data Full 0 = Wait 1 = Read Host Transmit Data Empty 0 = Wait 1 = Write Host Command Pending 0 = Wait 1 = Ready Host Flags Read Only DMA status 0 = DMA Mode Disabled 1 = DMA Mode Enabled Host Status Register (HSR) X:$FFFFC3 Reset = $2
* = Reserved, Program as 0
15
8
7
DMA
6
5
4
HF1
3
HF0
2
1
0
** 00
** 00
HCP HTDE HRDF
* = Reserved, Program as 0
Figure D-7 Host Control and Status Registers
D-22
DSP56367
MOTOROLA
Programmer's Reference
Application:
Date: Programmer:
Sheet 3 of 6
HOST (HDI08)
Host Base Address Register (HBAR) X:$FFFFC5 Reset = $80
DSP Side
15 8 7
BA10
6
BA9
5
BA8
4
BA7
3
BA6
2
BA5
1
BA4
0
BA3
** 00
Host Request Open Drain HDRQ HROD HREN/HEW 0 0 1 0 1 1 1 0 1 1 1 1
Host GPIO Port Enable 0 = GPIO Pins Disconnected 1 = GPIO Pin Enable Host Address Line 8 Enable 0 HA8 = GPIO, 1 HA8 = HA8 Host Address Line 9 Enable 0 HA9 = GPIO, 1 HA9 = HA9 Host Chip Select Enable 0 HCS/HAI0 = GPIO, 1 HCS/HA10 = HCS, if HMUX = 0 1 HCS/HA10 = HC10, if HMUX = 1 Host Request Enable 0 HOREQ/HACK = GPIO, 1 HOREQ = HOREQ, if HDRQ = 0 Host Acknowledge Enable 0 HACK = GPIO If HDRQ & HREN = 1, HACK = HACK Host Enable 0 HDI08 Disable Pins = GPIO 1 HDI08 Enable
Host Data Strobe Polarity 0 = Strobe Active Low, 1 = Strobe Active High Host Address Strobe Polarity 0 = Strobe Active Low, 1 = Strobe Active High Host Multiplexed Bus 0 = Nonmultiplexed, 1 = Multiplexed Host Dual Data Strobe 0 = Single Strobe, 1 = Dual Strobe
Host Chip Select Polarity 0 = HCS Active Low HTRQ & HRRQ Enable 1 = HCS Active High
HDRQ 0 0 1 1 Host Request Polarity HRP 0 HOREQ Active Low 1 HOREQ Active High 0 HTRQ,HRRQ Active Low 1 HTRQ,HRRQ Active High
Host Acknowledge Polarity 0 = HACK Active Low, 1 = HACK Active High
15
Host Port Control Register (HPCR) X:$FFFFC4 Read/Write Reset = $0
HAP
14
HRP
13
HCSP
12
11
10
9
HDSP
8
HROD
7
6
HEN
5
HAEN
4
3
2
1
0
HDDS HMUX HASP
* 0
HREN HCSEN HA9EN HA8EN HGEN
* = Reserved, Program as 0
Figure D-8 Host Base Address and Host Port Control
MOTOROLA
DSP56367
D-23
Programmer's Reference
Application:
Date: Programmer: Sheet 4 of 6
HOST (HDI08)
Processor Side
1 = Interrupts Enabled 1 = DSP -> Host 1 = Interrupts Enabled 1 = Host -> DSP
Receive Request Enable DMA Off 0 = Interrupts Disabled DMA On 0 = Host -> DSP Transmit Request Enable DMA Off 0 = Interrupts Disabled DMA On 0 = DSP -> Host HDRQ 0 1 HOREQ/HTRQ HOREQ HTRQ HACK/HRRQ HACK HRRQ
Host Flags Write Only Host Little Endian Initialize (Write Only) 0 = No Action 1 = Initialize DMA HDM[2:0] = 000 For HM[1:0] bits, see Table 6-12 in Section 6 HDM[2:0] = 100 HDM1 and/or HDM0 = 1 Interrupt Control Register (ICR) $0 R/W Reset = $0 Receive Data Register Full 0 = Wait 1 = Read Transmit Data Register Empty 0 = Wait 1 = Write Transmitter Ready 0 = Data in HI 1 = Data Not in HI Host Flags Read Only
INIT INIT
7
INIT
6
HM1
5
HLEND HM0
4
HF1 HF1
3
HF0
2
1
0
HDRQ TREQ RREQ TREQ RREQ TREQ RREQ
* 0
(HDM1) (HDM0) HF1
HF0 HF0
* 0 * 0
Host Request 0 = HOREQ Deasserted
1 = HOREQ Asserted
7
HREQ
Interrupt Status Register (ISR) $2 R/W Reset = $0
6 5 ** 0 0
4
HF3
3
HF2
2
1
0
RXDF
TRDY TXDE
* = Reserved, Program as 0
Figure D-9 Host Interrupt Control and Interrupt Status
D-24
DSP56367
MOTOROLA
Programmer's Reference
Application:
Date: Programmer: Sheet 5 of 6
HOST (HDI08)
7
Interrupt Vector Register (IVR) $3 R/W Reset = $0F
Processor Side
6
IV6
5
IV5
4
IV4
3
IV3
2
IV2
1
IV1
0
IV0
IV7
Contains the interrupt vector or number
Host Vector Contains Host Command Interrupt Address / 2 Host Command Handshakes Executing Host Command Interrupts
7
HC
6
HV6
5
HV5
4
HV4
3
HV3
2
HV2
1
HV1
0
HV0
Command Vector Register (CVR) $1 R/W Reset = $32
Contains the host command interrupt address
Figure D-10 Host Interrupt Vector and Command Vector
MOTOROLA
DSP56367
D-25
Programmer's Reference
Application:
Date: Programmer: Sheet 6 of 6
HOST (HDI08)
7
Receive Low Byte
Processor Side
07 07
Receive High Byte
0 0 0
Host Receive Data (HLEND = 0)
07
Receive Middle Byte
0
Not Used
0 0 0 0 0
$7
$6
$5
$4
Host Receive Data (HLEND = 1)
7
Receive Low Byte
07
Receive Middle Byte
07
Receive High Byte
07
Not Used
0 0 0 0 0 0 0
0
0
$5
Receive Byte Registers $7, $6, $5, $4 Read Only Reset = Empty
$6
$7
$4
Receive Byte Registers
Host Transmit Data (HLEND = 0)
7
Transmit Low Byte
07
Transmit Middle Byte
07
Transmit High Byte
07
Not Used
0 0 0 0 0 0 0
0
0
$7
$6
$5
$4
Host Transmit Data (HLEND = 1)
7
Transmit Low Byte
07
Transmit Middle Byte
07
Transmit High Byte
07
Not Used
0 0 0 0 0 0 0
0
0
$5
Transmit Byte Registers $7, $6, $5, $4 Write Only Reset = Empty
$6
$7
$4
Transmit Byte Registers
Figure D-11 Host Receive and Transmit Byte Registers
D-26
DSP56367
MOTOROLA
MOTOROLA DSP56367 D-27
SHI
Application:
HSAR I2C Slave Address Slave address = Bits HA6-HA3, HA1 and external pins HA2, HA0 Slave address after reset = 1011[HA2]0[HA0]
23 22 21 20 19 18 17 16
HA6 HA5 HA4 HA3 HA1
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
SHI Slave Address Register (HSAR) X:$FFFF92 Reset = $Bx0000
* * ********* ******** 0
000000000000000000 0 0 0 0
SHI Slave Address Register (HSAR)
HFM1 HFM0 0 0 0 1 1 0 1 1
SHI Noise Reduction Filter Mode Bypassed (Filter disabled) Reserved Narrow spike tolerance Wide spike tolerance
CPOL CPHA Result 0 0 SCK active low, strobe on rising edge 0 1 SCK active low, strobe on falling edge 1 0 SCK active high, strobe on falling edge 1 1 SCK active high, strobe on rising edge HRS Result 0 Prescaler operational 1 Prescaler bypassed HCKR Divider Modulus
Date:
23 22 21 20 19 18 17 16
15 14 13 12
HFM1HFM0
11
10
HDM7
9
8
7
6
5
4
3
2
1
0
Programmer:
Figure D-12 SHI Slave Address and Clock Control Registers
SHI Clock Control Register (HCKR) X:$FFFF90 Reset = $000001
**********
0000000000 0 0
* 0
HDM6HDM5HDM4HDM3HDM2HDM1HDM0 HRS CPOLCPHA
Programmer's Reference
Sheet 1 of 3
as *= Reserved, writeSHI0Clock Control Register (HCKR)
D-28
Application:
SHI
Host Transmit Data Register SHI Host Transmit 23 Data Register (HTX) X:$FFFF93 Write Only Reset = $xxxxxx
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Programmer's Reference
SHI Host Transmit Data Register (HTX)
Figure D-13 SHI Transmit and Receive Data Registers
DSP56367 MOTOROLA
Host Receive Data Register SHI Host Receive 23 Data Register (HRX) X:$FFFF94 Read Only Reset = $xxxxxx
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Date:
Programmer:
SHI Host Receive Data Register (HRX) (FIFO) 10 words deep
Sheet 2 of 3
MOTOROLA
Figure D-14 SHI Host Control/Status Register
SHI
1 1 HRIE1 HRIE0 Interrupt 0 0 disabled 1 Receive FIFO not empty 0 0 Receive Overrun Error 1 reserved Receive FIFO full Receive Overrun Error Host Transmit Underrun Error Read Only Status Bit Host Transfer Data Empty Read Only Status Bit Host Receive FIFO Not Empty Read Only Status Bit Host Receive FIFO Full Read Only Status Bit Host Receive Overrun Error Read Only Status Bit HBER I2C SPI Mode 0 No error No error 1 No acknowledge SS asserted HBUSY 0 1 I2C Stop event SHI detects Start SPI Mode Not Busy SS detected (Slave) -ORHTX/IOSR not empty (master) Condition n.a. HRNE=1 & HROE=0 HROE=1 n.a. HRFF=1 & HROE=0 HROE=1
HRQE1 HRQE0 0 0 0 1 1 0 1 1
HREQ Pin Operation High impedance Asserted if IOSR ready to receive new word Asserted if IOSR ready to transmit new word I2C: Asserted if IOSR ready to transmit or receive SPI: Asserted if OISR ready to transmit and receive HM1 HM0 0 0 0 1 1 0 1 1 Description 8 bit data 16 bit data 24 bit data Reserved
HCKFR 0 1 Description I2C Slave Clock Freeze Disabled I2C Slave Clock Freeze Enabled
Application:
HIDLE Description 0 Bus busy 1 Stop event
HFIFO Description 0 1 level FIFO 1 10 level
HMST Result
0 1 Slave mode Master mode
HBIE Description 0 Bus Error Interruptdisabled 1 Bus Error Interrupt enabled
DSP56367 D-29
HEN Description 0 SHI disabled 1 SHI enabled HTIE Description 0 Transmit Interrupt disabled 1 Transmit Interrupt activated HI2C Result 0 SPI mode 1 I2C mode
Date: Programmer:
23
22
21 20
19
18
17
HRNE
16
15
14
13
12
11
10
9
8
7
6
5
4
32
1
0
Sheet 3 of 3
SHI Control/Status Register (HCSR) X:$FFFF91 Reset = $008200
* 0
HBUSY HBER HROE HRFF
* 0
* 0
HTDE HTUEHRIE1HRIE0 HTIE HBIE HIDLE HRQE1 HRQE0 HMSTHFIF0HCKFR HM1 HM0 HI2C HEN
Programmer's Reference
**
= Reserved, write as 0
D-30
Figure D-15 ESAI Transmit Clock Control Register
THCKD
Description HCKT is input HCKT is output Description FST is input FST is output Description External clock source used Internal clock source Description
0 1
TFSD
TCCR - ESAI Transmit Clock Control Register X: $FFFFB6 Reset: $000000
Application:
ESAI
0 1
Programmer's Reference
TCKD
TFP [3:0]
Description
0 1
Sets divide rate for transmission high frequency clock Range $0 - $F (1 -16). See 8.3.1.4
THCKP
0 1
Transmitter High Frequency Clock Polarity set to clockout on rising edge of transmit clock, latch in on falling edge Transmitter High Frequency Clock Polarity set to clockout on falling edge of transmit clock, latch in on rising edge Description Frame sync polarity positive Frame sync polarity negative TCKP Description
TDC [4:0]
Description Divider control. Range $00 - $FF (1 - 32) See 8.3.1.3
TFSP
TPSR
Description Divide by 8 prescaler operational Divide by 8 prescaler bypassed
DSP56367 MOTOROLA
0 1
0 1
0 1
Transmitter Clock Polarity set to clockout on rising edge of transmit clock, latch in on falling edge of transmit clock. Transmitter Clock Polarity set to clockout on falling edge of transmit clock, latch in on rising edge of transmit clock
TPM [7:0]
Description Specifies the prescaler divide rate is for the transmitter clock generator Range from $00 - $FF (1 - 256). See 8.3.1.1
Date: Programmer:
23
THCKD
22
TFSD
21
TCKD
20
THCKP
19
TFSP
18
TCKP
17
TFP3
16
15
14
TFP0
13
TDC4
12
TDC3
11
TDC2
10
TDC1
9
TDC0
8
TPSR
7
6
5
TPM5
4
TPM4
3
TPM3
2
TPM2
1
0
TFP2 TFP1
TPM7 TPM6
TPM1 TPM0
AA1777
TLIE
Description Transmit Last Slot Interrupt disabled Transmit Last Slot Interrupt enabled Description Transmit Interrupt disabled Transmit Interrupt enabled TEDIE Description
0 1
TIE
TCR - ESAI Transmit Control Register X: $FFFFB5 Reset: $000000
TFSL Description Word length frame sync 1-bit clock period frame sync
MOTOROLA
Figure D-16 ESAI Transmit Control Register
ESAI
Application:
0 1
0 1
TSWS [0:4]
Description Defines slot and data word length See 8.3.2.10 and table 8-5
0 1
Transmit Even Slot Data Interrupt disabled Transmit Even Slot Data Interrupt enabled TEIE Description Transmit Exception Interrupt disabled Transmit Exception Interrupt enabled TPR Description Transmitter Normal Operation Transmitter Personal Reset Description Zero Padding disabled Zero Padding enabled TFSR Description TWA
TMOD1 TMOD0 0 0 1 1 0 1 0 1
Network Mode Normal mode Network mode Reserved AC97 Description
0 1
0 1
PADC
Data left aligned Data right aligned Description Data shifted out MSB first Data shifted out LSB first Description Transmitter disabled Transmitter enabled
DSP56367 D-31
0 1
0 1
TSHFD
Date:
0 1
0 1
TE [0:5]
Programmer:
Word-length frame sync synchronous to beginning of data word first slot Word-length frame sync 1 clock before beginning of data word first slot
0 1
23
TLIE
22
TIE
21
20
19
TPR
18
17
16
15
14
13
12
11
10
9
8
7
6
5
TE5
4
TE4
3
TE3
2
TE2
1
TE1
0
TE0
TEDIE TEIE
*
PADC TFSR TFSL TSWS4 TSWS3 TSWS2 TSWS1 TSWS0 TMOD1 TMOD0 TWA TSHFD
Programmer's Reference
0
D-32
Figure D-17 ESAI Receive Clock Control Register
RHCKD
Description HCKR is input HCKR is output RFSD Description FSR is input FSR is output RCKD Description
Application:
0 1
RCCR - ESAI Receive Clock Control Register X: $FFFFB8 Reset: $000000
ESAI
0 1
Programmer's Reference
RFP [3:0]
Description Sets divide rate for receiver high frequency clock Range $0 - $F (1 -16). See 8.3.3.4
External clock source used Internal clock source Description
0 1
RHCKP
RDC [4:0]
Description Controls frame rate dividers Range 00000 - 11111 (1-32) See 8.3.3.2
0 1
Clockout on rising edge of receive clock, latch in on falling edge of receive clock Clockout on falling edge of receive clock, latch in on rising edge of receive clock RFSP Description Frame sync polarity positive Frame sync polarity negative Description
RPSR
Description Divide by 8 prescaler operational Divide by 8 prescaler bypassed
DSP56367 MOTOROLA
0 1
0 1
RCKP
0 1
Clockout on rising edge of receive clock, latch in on falling edge of receive clock Clockout on falling edge of receive clock, latch in on rising edge of receive clock
RPM [7:0]
Description Specifies prescaler ratio for the receive clock generator Range from $00 - $FF (1 - 256). See 8.3.3.1
Date:
Programmer:
23
RHCKD
22
21
20
RHCKP
19
RFSP
18
RCKP
17
16
15
14
RFP0
13
RDC4
12
RDC3
11
RDC2
10
9
8
RPSR
7
6
5
4
3
2
1
0
RFSD RCKD
RFP3 RFP2 RFP1
RDC1 RDC0
RPM7 RPM6 RPM5 RPM4 RPM3 RPM2
RPM1 RPM0
RLIE 0 1
Description Receive Last Slot Interrupt disabled Receive Last Slot interrupt enabled RIE 0 1 Description Receive Interrupt disabled Receive interrupt enabled REDIE 0 1 Description
RCR - ESAI Receive Control Register X: $FFFFB7 Reset: $000000
RFSL 0 1 Description Word length frame sync 1-bit clock period frame sync
Description
MOTOROLA
Figure D-18 ESAI Receive Control Register
ESAI
Application:
RSWS [0:4]
Defines slot and data word length See 8.3.4.9 and table 8-8
Receive Even Slot Data Interrupt disabled Receive Even Slot Data Interrupt enabled
RMOD1 RMOD0 0 0 0 1 0 1 RWA
Network Mode Normal mode Network mode Reserved AC97 Description Data left aligned Data right aligned
REIE 0 1
Description Receive Exception Interrupt disabled Receive Exception Interrupt enabled
1 1
RPR 0 1
Description Receiver Normal Operation Receiver Personal Reset
0 1
DSP56367 D-33
RSHFD RFSR 0 1 Description Word-length frame sync synchronous to beginning of data word first slot Word-length frame sync 1 clock before beginning of data word first slot 0 1
Description Data shifted in MSB first Data shifted in LSB first
Date:
RE [0:3] 0 1
Description Receiver disabled Receiver enabled
Programmer:
23
22
21
20
19
18
17
16
15
RFSL
14
RSWS4
13
12
11
10
9
8
7
6
5
Rsvd
4
Rsvd
3
RE3
2
RE2
1
RE1
0
RE0
Programmer's Reference
RLIE RIE REDIE REIE RPR Rsvd Rsvd RFSR
RSWS3 RSWS2
RSWS1 RSWS0 RMOD1 RMOD0 RWA RSHFD
D-34
Figure D-19 ESAI Common Control Register
SAICR - ESAI Common Control Register X: $FFFFB4 Reset: $000000
ALC Description Data left aligned to bit 23 Data left aligned to bit 15 TEBE Description Controls FSR pin. See 8.3.5.6 and table 8-9
ESAI
Application:
Programmer's Reference
0 1
SYN
Description Asynchronous mode Synchronous mode
0 1
Description Reserved
DSP56367 MOTOROLA
Description Reserved
OF(2:0)
Description Holds data to send to OFn pin. See 8.3.5.1 to .3
Date:
Programmer:
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
ALC
7
TEBE
6
SYN
5
4
3
2
OF2
1
OF1
0
OF0
RODF
Description Receive odd-data register empty Receive odd-data register full
SAISR - ESAI Status Register X: $FFFFB3 Reset $000000
REDF Description Receive even-data register empty Receive even-data register full RDF Description Receive data register empty Receive data register full ROE Description
ESAI
0 1
Application:
MOTOROLA
TFS
Description Reserved Description Transmit Frame sync did not occur during word transmission Transmit frame sync occurred during word transmission Description No transmit underrun error Transmit underrun error Description Transmit data registers not empty Transmit data registers empty Description Transmit even-data registers not empty Transmit even-data registers empty
0 1
0 1
0 1
TUE
0 1
TDE
0 No receiver overrun error 1 Receiver overrun error
RFS Description
0 1
0 1
TEDE
Receive frame sync did not occur during word reception Receive frame sync did occur during word reception Description Reserved
Figure D-20 ESAI Status Register
DSP56367 D-35
0 1
TODE
IF [0:2] Description Transmit odd-data register not empty Transmit odd-data register empty Description Reserved
Description
0 1 2
Date:
Programmer:
0 1
Holds data sent from SCKR pin. See 8.3.6.1 Holds data sent from FSR pin. See 8.3.6.2 Holds data sent from HCKR pin. See 8.3.6.3
23
22
21
20
19
18
17
TODE
16
TEDE
15
TDE
14
TUE
13
TFS
12
11
10
9
8
RDF
7
ROE
6
RFS
5
4
3
2
IF2
1
IF1
0
IF0
Programmer's Reference
RODF REDF
D-36
Figure D-21 ESAI_1 Multiplex Control Register
EMUXR - ESAI_1 Multiplex Control Register Y: $FFFFAF Reset: $000000
ESAI_1
Application:
EMUXR ESAI/ESAI_1 Pin Selection
EMUXR bit EMUX0 EMUX0 EMUX1 EMUX1 EMUX2 EMUX2 EMUX3 EMUX3 0 1 0 1 0 1 0 1 ESAI pin SDO0 [PC11] disconnected SDO1[PC10] disconnected SDO2/SDI3 [PC9] disconnected SDO3/SDI2 [PC8] disconnected ESAI_1 pin disconnected SDO0_1 [PE11] disconnected SDO1_1 [PE10] disconnected SDO2_1/SDI3_1 [PE9] disconnected SDO3_1/SDI2_1 [PE8]
Programmer's Reference
DSP56367 MOTOROLA
Description Reserved
Date:
Programmer:
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EMUX3 EMUX2 EMUX1 EMUX0
THCKD
Description Reserved Must be set for proper operation Description FST_1 is input FST_1 is output Description External clock source used Internal clock source
0 1
TFSD
TCCR_1 - ESAI_1 Transmit Clock Control Register Y: $FFFF96 Reset: $000000
Application:
MOTOROLA
Figure D-22 ESAI_1 Transmit Clock Control Register
ESAI_1
TFP [3:0] Divider control. Range $0 - $F (1 -16). Description
0 1
TCKD
0 1
THCKP
Description Keep cleared for proper operation Reserved Description Frame sync polarity positive Frame sync polarity negative TCKP Description TPM [7:0] Description Specifies the prescaler divide rate is for the transmitter clock generator Range from $00 - $FF (1 - 256). TPSR Description Divide by 8 prescaler operational Divide by 8 prescaler bypassed TDC [4:0] Description Divider control. Range $00 - $FF (1 - 32)
0 1
TFSP
DSP56367 D-37
0 1
0 1
0 1
Transmitter Clock Polarity set to clockout on rising edge of transmit clock, latch in on falling edge of transmit clock. Transmitter Clock Polarity set to clockout on falling edge of transmit clock, latch in on rising edge of transmit clock
Date: Programmer:
23
THCKD
22
TFSD
21
TCKD
20
THCKP
19
TFSP
18
TCKP
17
TFP3
16
15
14
TFP0
13
TDC4
12
TDC3
11
TDC2
10
TDC1
9
TDC0
8
TPSR
7
6
5
TPM5
4
TPM4
3
TPM3
2
TPM2
1
0
TFP2 TFP1
TPM7 TPM6
TPM1 TPM0
Programmer's Reference
AA1777
TLIE
Description Transmit Last Slot Interrupt disabled Transmit Last Slot Interrupt enabled Description Transmit Interrupt disabled Transmit Interrupt enabled TEDIE Description
0 1
TIE
TCR_1 - ESAI_1 Transmit Control Register Y: $FFFF95 Reset: $000000
TFSL Description Word length frame sync 1-bit clock period frame sync
D-38
Figure D-23 ESAI_1 Transmit Control Register
ESAI_1
Application:
0 1
0 1
TSWS [0:4]
Description Defines slot and data word length
0 1
Transmit Even Slot Data Interrupt disabled Transmit Even Slot Data Interrupt enabled TEIE Description Transmit Exception Interrupt disabled Transmit Exception Interrupt enabled TPR Description Transmitter Normal Operation Transmitter Personal Reset Description Zero Padding disabled Zero Padding enabled TFSR Description TWA
Programmer's Reference
TMOD1 TMOD0 0 0 1 1 0 1 0 1
Network Mode Normal mode Network mode Reserved AC97 Description
0 1
0 1
PADC
Data left aligned Data right aligned Description Data shifted out MSB first Data shifted out LSB first Description Transmitter disabled Transmitter enabled
DSP56367 MOTOROLA
0 1
0 1
TSHFD
Date:
0 1
0 1
TE [0:5]
Programmer:
Word-length frame sync synchronous to beginning of data word first slot Word-length frame sync 1 clock before beginning of data word first slot
0 1
23
TLIE
22
TIE
21
20
19
TPR
18
17
16
15
14
13
12
11
10
9
8
7
6
5
TE5
4
TE4
3
TE3
2
TE2
1
TE1
0
TE0
TEDIE TEIE
*
PADC TFSR TFSL TSWS4 TSWS3 TSWS2 TSWS1 TSWS0 TMOD1 TMOD0 TWA TSHFD
0
RHCKD
Description Reserved Must be set for proper operation RFSD Description FSR_1 is input FSR_1 is output RCKD Description
Application:
MOTOROLA
Figure D-24 ESAI_1 Receive Clock Control Register
0 1
RCCR_1 - ESAI_1 Receive Clock Control Register Y: $FFFF98 Reset: $000000
ESAI_1
RFP [3:0] Description Sets divide rate Range $0 - $F (1 -16).
0 1
0 1
External clock source used Internal clock source Description Keep cleared for proper operation Reserved
RHCKP
RDC [4:0]
Description Controls frame rate dividers Range 00000 - 11111 (1-32)
0 1
RFSP
Description Frame sync polarity positive Frame sync polarity negative Description
RPSR
Description Divide by 8 prescaler operational Divide by 8 prescaler bypassed
DSP56367 D-39
0 1
0 1
RCKP
0 1
RPM [7:0]
Description Specifies prescaler ratio for the receive clock generator Range from $00 - $FF (1 - 256).
Clockout on rising edge of receive clock, latch in on falling edge of receive clock Clockout on falling edge of receive clock, latch in on rising edge of receive clock
Date:
Programmer:
23
RHCKD
22
21
20
RHCKP
19
RFSP
18
RCKP
17
16
15
14
RFP0
13
RDC4
12
RDC3
11
RDC2
10
9
8
RPSR
7
6
5
4
3
2
1
0
Programmer's Reference
RFSD RCKD
RFP3 RFP2 RFP1
RDC1 RDC0
RPM7 RPM6 RPM5 RPM4 RPM3 RPM2
RPM1 RPM0
D-40
Figure D-25 ESAI_1 Receive Control Register
RLIE 0 1
Description Receive Last Slot Interrupt disabled Receive Last Slot interrupt enabled RIE 0 1 Description Receive Interrupt disabled Receive interrupt enabled REDIE 0 1 Description
RCR_1 - ESAI_1 Receive Control Register Y: $FFFF97 Reset: $000000
RFSL 0 1 Description Word length frame sync 1-bit clock period frame sync
ESAI_1
Application:
RSWS [0:4]
Description Defines slot and data word length
Programmer's Reference
Receive Even Slot Data Interrupt disabled Receive Even Slot Data Interrupt enabled
RMOD1 RMOD0 0 0 0 1 0 1 RWA
Network Mode Normal mode Network mode Reserved AC97 Description Data left aligned Data right aligned
REIE 0 1
Description Receive Exception Interrupt disabled Receive Exception Interrupt enabled
1 1
RPR 0 1
Description Receiver Normal Operation Receiver Personal Reset
0 1
DSP56367 MOTOROLA
RSHFD RFSR 0 1 Description Word-length frame sync synchronous to beginning of data word first slot Word-length frame sync 1 clock before beginning of data word first slot 0 1
Description Data shifted in MSB first Data shifted in LSB first
Date:
RE [0:3] 0 1
Description Receiver disabled Receiver enabled
Programmer:
23
22
21
20
19
18
17
16
15
RFSL
14
RSWS4
13
12
11
10
9
8
7
6
5
Rsvd
4
Rsvd
3
RE3
2
RE2
1
RE1
0
RE0
RLIE RIE REDIE REIE RPR Rsvd Rsvd RFSR
RSWS3 RSWS2
RSWS1 RSWS0 RMOD1 RMOD0 RWA RSHFD
SAICR_1 - ESAI_1 Common Control Register Y: $FFFF94 Reset: $000000
ALC Description Data left aligned to bit 23 Data left aligned to bit 15 TEBE Description Controls FSR_1 pin.
MOTOROLA
Figure D-26 ESAI_1 Common Control Register
Application:
ESAI_1
0 1
SYN
Description Asynchronous mode Synchronous mode
0 1
Description Reserved
DSP56367 D-41
Description Reserved
OF(2:0)
Description Holds data to send to OFn pin.
Date:
Programmer:
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
ALC
7
TEBE
6
SYN
5
4
3
2
OF2
1
OF1
0
OF0
Programmer's Reference
D-42
TFS
ESAI_1
RODF
Description Receive odd-data register empty Receive odd-data register full
SAISR_1 - ESAI_1 Status Register Y: $FFFF93 Reset $000000
REDF Description Receive even-data register empty Receive even-data register full RDF Description Receive data register empty Receive data register full ROE Description
0 1
Application:
Description Reserved Description Transmit Frame sync did not occur during word transmission Transmit frame sync occurred during word transmission Description No transmit underrun error Transmit underrun error Description Transmit data registers not empty Transmit data registers empty Description Transmit even-data registers not empty Transmit even-data registers empty
0 1
0 1
Programmer's Reference
0 1
TUE
0 1
TDE
0 No receiver overrun error 1 Receiver overrun error
RFS Description
0 1
0 1
TEDE
Receive frame sync did not occur during word reception Receive frame sync did occur during word reception Description Reserved
Figure D-27 ESAI_1 Status Register
DSP56367 MOTOROLA
0 1
TODE
IF [0:2] Description Transmit odd-data register not empty Transmit odd-data register not empty Transmit odd-data register empty Description Reserved
Description
Holds data sent from SCKR_1 pin. Holds data sent from FSR_1 pin. Holds data sent from HCKR_1 pin.
0 1
0 1 2
Date:
Programmer:
23
22
21
20
19
18
17
TODE
16
TEDE
15
TDE
14
TUE
13
TFS
12
11
10
9
8
RDF
7
ROE
6
RFS
5
4
3
2
IF2
1
IF1
0
IF0
RODF REDF
Application:
MOTOROLA
DAX
Channel A Validity (XVA) Channel A User Data (XUA)
Figure D-28 DAX Non-Audio Data Register
DSP56367 D-43
Channel B Validity (XVB) Channel B User Data (XUB)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 DAX Non-Audio Data Register (XNADR) X:$FFFFD1 Reset = $00XX00
******* * 0000000 0
XCB XUB XVB XCA XUA XVA
9876543210 00000 ******** ** 00000 Date: Programmer: Sheet 1 of 2
Programmer's Reference
D-44
Figure D-29 DAX Control and Status Registers
Application:
DAX
XBIE DAX Block Trans. Int. Enable 0 Disabled 1 Enabled
XUIE DAX Underrun Int. Enable 0 Disabled 1 Enabled
XDIE Aud. Dat. Reg. Emp. Int. En. 0 Disabled 1 Enabled
XCS1 0 0 1 1 XSB DAX Start Block 0 Disabled 1 Force Block Start
XCS0 DAX Clock Source 0 1 0 1 DSP Core Clock (f = 1024 x fs) ACI Pin, f = 256 x fs ACI Pin, f = 384 x fs ACI Pin, f = 512 x fs
Programmer's Reference
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 DAX Control Register (XCTR) X:$FFFFD0 Reset = $000000
8
7
6
5
4
3
2
1
0
************** **** 00000000000000 0000
XBLK DAX Block transfer 0 not last frame 1 191st frame transmission
XSB XCS1 XCS0 XBIE XUIE XDIE
DSP56367 MOTOROLA
XADE DAX Audio Data Empty 0 Register(s) full 1 Register(s) empty XAUR DAX Underrun error 0 No error 1 Underrun error
Date:
Programmer:
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 DAX Status Register (XSTR) X:$FFFFD4 Reset = $000000
8
7
6
5
4
3
2
1
0
** * ** ** * ** * ** * * * **** * 00 0 00 00 0000 000000000 0
XBLK XAURXADE
* = Reserved; write as 0
Programmer's Reference
Application:
Date: Programmer: Sheet 1 of 3
TEC
PS (1:0) 00 01 10 11 Prescaler Clock Source Internal CLK/2 TIO0 Reserved Reserved
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
* 0
PS1
PS0
Prescaler Preload Value (PL [0:20])
Timer Prescaler Load Register TPLR:$FFFF83 Read/Write Reset = $000000
* = Reserved, Program as 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
*** 000
Timer Prescaler Count Register TPCR:$FFFF82 Read Only Reset = $000000
Current Value of Prescaler Counter (PC [0:20])
*= Reserved, Program as 0
Figure D-30 Timer Prescaler Load and Prescaler Count Registers (TPLR, TPCR)
MOTOROLA
DSP56367
D-45
Programmer's Reference
Application:
Date: Programmer:
Sheet 2 of 3
TEC
Inverter Bit 8 0 = 0- to-1 transitions on TIO input increment the counter, or high pulse width measured, or high pulse output on TIO 1 = 1-to-0 transitions on TIO input increment the counter, or low pulse width measured, or low pulse output on TIO
Timer Reload Mode Bit 9 0 = Timer operates as a free running counter 1 = Timer is reloaded when selected condition occurs Direction Bit 11 0 = TIO pin is input 1 = TIO pin is output Data Input Bit 12 0 = Zero read on TIO pin 1 = One read on TIO pin Data Output Bit 13 0 = Zero written to TIO pin 1 = One written to TIO pin Prescaled Clock Enable Bit 15 0 = Clock source is CLK/2 or TIO 1 = Clock source is prescaler output Timer Compare Flag Bit 21 0 = "1" has been written to TCSR(TCF), or timer compare interrupt serviced 1 = Timer Compare has occurred Timer Overflow Flag Bit 20 0 = "1" has been written to TCSR(TOF), or timer Overflow interrupt serviced 1 = Counter wraparound has occurred
TC (3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Timer Control Bits 4 - 7 (TC0 - TC3) TIO Clock Mode GPIO Internal Timer Output Internal Timer Pulse Output Internal Timer Toggle Input External Event Counter Input Internal Input Width Input Internal Input Period Input Internal Capture Output Internal Pulse Width Modulation - - Reserved Output Internal Watchdog Pulse Output Internal Watchdog Toggle - - Reserved - - Reserved - - Reserved - - Reserved - - Reserved Timer Enable Bit 0 0 = Timer Disabled 1 = Timer Enabled Timer Overflow Interrupt Enable Bit 1 0 = Overflow Interrupts Disabled 1 = Overflow Interrupts Enabled
Timer Compare Interrupt Enable Bit 2 0 = Compare Interrupts Disabled 1 = Compare Interrupts Enabled
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
TC3
6
TC2
5
TC1
4
TC0
3
2
1
0
TE
** 00
TCF
TOF
* * ** 0000
PCE
* 0
DO
DI
DIR
* 0
TRM INV
* 0
TCIE TOIE
Timer Control/Status Register TCSR0:$FFFF8F Read/Write TCSR1:$FFFF8B Read/Write TCSR2:$FFFF87 Read/Write Reset = $000000
* = Reserved, Program as 0
Note that for Timers 1 and 2, TC (3:0) = 0000 is the only valid combination. All other combinations are reserved.
Figure D-31 Timer Control/Status Register
D-46
DSP56367
MOTOROLA
Programmer's Reference
Application:
Date: Programmer:
Sheet 3 of 3
TEC
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Timer Reload Value 8 7 6 5 4 3 2 1 0
Timer Load Register TLR0:$FFFF8E Write Only TLR1:$FFFF8A Write Only TLR2:$FFFF86 Write Only Reset = $XXXXXX
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Value Compared to Counter Value
Timer Compare Register TCPR0:$FFFF8D Read/Write TCPR1:$FFFF89 Read/Write TCPR2:$FFFF85 Read/Write Reset = $XXXXXX
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Timer Count Value
8
7
6
5
4
3
2
1
0
Timer Count Register TCR0:$FFFF8C Read Only TCR1:$FFFF88 Read Only TCR2:$FFFF84 Read Only Reset = $000000
Figure D-32 Timer Load, Compare and Count Registers
MOTOROLA
DSP56367
D-47
Programmer's Reference
Application:
Date: Programmer:
Sheet 1 of 4
GPIO
Host Data Direction Register (HDDR) X:$FFFFC8 Read/Write Reset = $0 DRx = 1 PBx is Output
Port B (HDI08)
15
DR15
14
13
12
DR12
11
DR11
10
DR10
9
DR9
8
DR8
7
DR7
6
DR6
5
DR5
4
DR4
3
DR3
2
DR2
1
DR1
0
DR0
DR14 DR13
DRx = 0 PBx is Input
Host Data Register (HDR) X:$FFFFC9 Read/Write Reset = Undefined
15
D15
14
D14
13
D13
12
D12
11
D11
10
D10
9
D9
8
D8
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
Dx holds value of corresponding HDI08 GPIO pin. Function depends on HDDR. See the HDI08 HPCR Register (Figure D-8) for additional Port B GPIO control bits.
Figure D-33 GPIO Port B
D-48
DSP56367
MOTOROLA
Programmer's Reference
Application:
Date: Programmer:
Sheet 2 of 4
GPIO
23 Port C Control Register (PCRC) X:$FFFFBF Read/Write Reset = $0
Port C (ESAI) 11 10
PC11 PC10
9
PC9
8
PC8
7
PC7
6
PC6
5
PC5
4
PC4
3
2
1
0
PC0
* 0
23
PC3 PC2 PC1
* = Reserved, Program as 0
11 Port C Direction Register (PRRC) X:$FFFFBE Read/Write Reset = $0 10 9 8
PDC8
7
PDC7
6
PDC6
5
PDC5
4
3
21
0
* 0
PDC11 PDC10 PDC9
PDC4 PDC3 PDC2 PDC1 PDC0
* = Reserved, Program as 0
PCn = 0 & PDCn = 0 -> Port pin PCn disconnected PCn = 1 & PDCn = 0 -> Port pin PCn configured as input PCn = 0 & PDCn = 1 -> Port pin PCn configured as output PCn = 1 & PDCn = 1 -> Port pin configured as ESAI
23 Port C GPIO Data Register (PDRC) X:$FFFFBD Read/Write Reset = undefined
11 10
PD11 PD10
9
PD9
8
PD8
7
6
5
PD5
4
PD4
3
PD3
2
1
0
PD0
* 0
PD7 PD6
PD2 PD1
* = Reserved, Program as 0
If port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n
Figure D-34 GPIO Port C
MOTOROLA
DSP56367
D-49
Programmer's Reference
Application:
Date: Programmer:
Sheet 3 of 4
GPIO
Port D Control Register (PCRD) X:$FFFFD7 Read/Write Reset = $0 23
Port D (DAX) 6 5 4 3 2 1
PC1
0
PC0
****** 000000
* = Reserved, Program as 0
23 6 5 4 3 2
Port D Direction Register (PRRD) X:$FFFFD6 Read/Write Reset = $0
1
0
****** 000000
* = Reserved, Program as 0
PDC1 PDC0
PCn = 0 & PDCn = 0 -> Port pin PDn disconnected PCn = 1 & PDCn = 0 -> Port pin PDn configured as input PCn = 0 & PDCn = 1 -> Port pin PDn configured as output PCn = 1 & PDCn = 1 -> Port pin configured as DAX
23 Port D GPIO Data Register (PDRD) X:$FFFFD5 Read/Write Reset = $0
6
5
4
3
2
1
PD1
0
PD0
****** 000000
* = Reserved, Program as 0
If port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n
Figure D-35 GPIO Port D
D-50
DSP56367
MOTOROLA
Programmer's Reference
Application:
Date: Programmer:
Sheet 4 of 4
GPIO
23 Port E Control Register (PCRE) Y:$FFFF9F Read/Write Reset = $0
Port E (ESAI_1) 11 10
PC11 PC10
9
PC9
8
PC8
7
PC7
6
PC6
5
4
PC4
3
PC3
2
1
PC1
0
PC0
* 0
23
* 0
6 5
* 0
* = Reserved, Program as 0
11
PDC11
Port E Direction Register (PRRE) Y:$FFFF9E Read/Write Reset = $0
10
PDC10
9
PDC9
8
PDC8
7
PDC7
4
3
21
0
* 0
PDC6
* 0
PDC4 PDC3
* 0
PDC1 PDC0
* = Reserved, Program as 0
PCn = 0 & PDCn = 0 -> Port pin PEn disconnected PCn = 1 & PDCn = 0 -> Port pin PEn configured as input PCn = 0 & PDCn = 1 -> Port pin PEn configured as output PCn = 1 & PDCn = 1 -> Port pin configured as ESAI_1
23 Port E GPIO Data Register (PDRE) Y:$FFFF9D Read/Write Reset = undefined
11 10
9
8
PD8
7
6
5
4
PD4
3
PD3
2
1
PD1
0
PD0
* 0
PD11 PD10 PD9
PD7 PD6
* 0
* 0
* = Reserved, Program as 0
If port pin n is GPIO input, then PDn reflects the value on port pin n if port pin n is GPIO output, then value written to PDn is reflected on port pin n
Figure D-36 GPIO Port E
MOTOROLA
DSP56367
D-51
Programmer's Reference
D-52
DSP56367
MOTOROLA
APPENDIX
E
POWER CONSUMPTION BENCHMARK
The following benchmark program permits evaluation of DSP power usage in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate instructions with a set of synthetic DSP application data to emulate intensive sustained DSP operation.
;********************************************************************;**************** **************************************************** ;* ;* CHECKS Typical Power Consumption
;******************************************************************** page 200,55,0,0,0 nolist I_VEC EQU START EQU INT_PROG INT_XDAT INT_YDAT $000000 $8000 EQU $100 EQU $0 EQU $0 ; ; ; ; ; Interrupt vectors for program debug only MAIN (external) program starting address INTERNAL program memory starting address INTERNAL X-data memory starting address INTERNAL Y-data memory starting address
INCLUDE "ioequ.asm" INCLUDE "intequ.asm" list org ; movep #$0123FF,x:M_BCR; BCR: Area 3 : 1 w.s (SRAM) ; Default: 1 w.s (SRAM) ; movep #$0d0000,x:M_PCTL ; XTAL disable ; PLL enable ; CLKOUT disable ; ; Load the program ; move #INT_PROG,r0 move #PROG_START,r1 do #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ nop PLOAD_LOOP P:START
MOTOROLA
DSP56367
E-1
Power Consumption Benchmark
; ; Load the X-data ; move move do move move XLOAD_LOOP ; ; Load the Y-data ; move move do move move YLOAD_LOOP ; jmp PROG_START move move move move ; clr clr move move move move bset ; sbr dor mac mac add mac mac move bra nop nop nop nop PROG_END nop nop
#INT_XDAT,r0 #XDAT_START,r1 #(XDAT_END-XDAT_START),XLOAD_LOOP p:(r1)+,x0 x0,x:(r0)+
#INT_YDAT,r0 #YDAT_START,r1 #(YDAT_END-YDAT_START),YLOAD_LOOP p:(r1)+,x0 x0,y:(r0)+
INT_PROG
#$0,r0 #$0,r4 #$3f,m0 #$3f,m4 a b #$0,x0 #$0,x1 #$0,y0 #$0,y1 #4,omr #60,_end x0,y0,a x1,y1,a a,b x0,y0,a x1,y1,a b1,x:$ff sbr
; ebd
x:(r0)+,x1 x:(r0)+,x0 x:(r0)+,x1
y:(r4)+,y1 y:(r4)+,y0
y:(r4)+,y0
_end
E-2
DSP56367
MOTOROLA
Power Consumption Benchmark
XDAT_START ; org dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc
x:0 $262EB9 $86F2FE $E56A5F $616CAC $8FFD75 $9210A $A06D7B $CEA798 $8DFBF1 $A063D6 $6C6657 $C2A544 $A3662D $A4E762 $84F0F3 $E6F1B0 $B3829 $8BF7AE $63A94F $EF78DC $242DE5 $A3E0BA $EBAB6B $8726C8 $CA361 $2F6E86 $A57347 $4BE774 $8F349D $A1ED12 $4BFCE3 $EA26E0 $CD7D99 $4BA85E $27A43F $A8B10C $D3A55 $25EC6A $2A255B $A5F1F8 $2426D1 $AE6536 $CBBC37 $6235A4 $37F0D $63BEC2 $A5E4D3 $8CE810 $3FF09 $60E50E
MOTOROLA
DSP56367
E-3
Power Consumption Benchmark
dc dc dc dc dc dc dc dc dc dc dc dc dc dc XDAT_END YDAT_START ; org dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc
$CFFB2F $40753C $8262C5 $CA641A $EB3B4B $2DA928 $AB6641 $28A7E6 $4E2127 $482FD4 $7257D $E53C72 $1A8C3 $E27540
y:0 $5B6DA $C3F70B $6A39E8 $81E801 $C666A6 $46F8E7 $AAEC94 $24233D $802732 $2E3C83 $A43E00 $C2B639 $85A47E $ABFDDF $F3A2C $2D7CF5 $E16A8A $ECB8FB $4BED18 $43F371 $83A556 $E1E9D7 $ACA2C4 $8135AD $2CE0E2 $8F2C73 $432730 $A87FA9 $4A292E $A63CCF $6BA65C $E06D65 $1AA3A $A1B6EB $48AC48
E-4
DSP56367
MOTOROLA
Power Consumption Benchmark
dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc YDAT_END
$EF7AE1 $6E3006 $62F6C7 $6064F4 $87E41D $CB2692 $2C3863 $C6BC60 $43A519 $6139DE $ADF7BF $4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF $6162BC $E4A245
MOTOROLA
DSP56367
E-5
Power Consumption Benchmark
E-6
DSP56367
MOTOROLA
APPENDIX IBIS MODEL
[IBIS ver] 2.1 [File name] 56367.ibs [File Rev] 0.0 [Date] 29/6/2000 [Component] 56367 [Manufacturer] Motorola [Package] |variable typ R_pkg 45m L_pkg 2.5nH C_pkg 1.3pF
F
min 22m 1.1nH 1.2pF
max 75m 4.3nH 1.4pF
[Pin]signal_name model_name 1 sck ip5b_io 2 ss_ ip5b_io 3 hreq_ ip5b_io 4 sdo0 ip5b_io 5 sdo1 ip5b_io 6 sdoi23 ip5b_io 7 sdoi32 ip5b_io 8 svcc power 9 sgnd gnd 10 sdoi41 ip5b_io 11 sdoi50 ip5b_io 12 fst ip5b_io 13 fsr ip5b_io 14 sckt ip5b_io 15 sckr ip5b_io 16 hsckt ip5b_io 17 hsckr ip5b_io 18 qvccl power 19 gnd gnd 20 qvcch power 21 hp12 ip5b_io 22 hp11 ip5b_io 23 hp15 ip5b_io 24 hp14 ip5b_io 25 svcc power 26 sgnd gnd 27 ado ip5b_io 28 aci ip5b_io 29 tio ip5b_io
MOTOROLA
DSP56367
F-1
IBIS Model
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82
hp13 hp10 hp9 hp8 hp7 hp6 hp5 hp4 svcc sgnd hp3 hp2 hp1 hp0 ires_ pvcc pcap pgnd sdo5 qvcch fst_1 aa2 cas_ sck_1 qgnd cxtldis_ qvccl cvcc cgnd fsr_1 sckr1 nmi_ ta_ br_ bb_ cvcc cgnd wr_ rd_ aa1 aa0 bg_ eab0 eab1 avcc agnd eab2 eab3 eab4 eab5 avcc agnd eab6
ip5b_io ip5b_io ip5b_io ip5b_io ip5b_io ip5b_io ip5b_io ip5b_io power gnd ip5b_io ip5b_io ip5b_io ip5b_io ip5b_i power power gnd ipbw_io power ipbw_io icbc_o icbc_o ipbw_io gnd iexlh_i power power gnd ipbw_io ipbw_io ipbw_i icbc_o icbc_o icbc_o power gnd icbc_o icbc_o icbc_o icbc_o icbc_o icba_o icba_o power gnd icba_o icba_o icba_o icba_o power gnd icba_o
F-2
DSP56367
MOTOROLA
IBIS Model
83 eab7 84 eab8 85 eab9 86 avcc 87 agnd 88 eab10 89 eab11 90 qgnd 91 qvcc 92 eab12 93 eab13 94 eab14 95 qvcch 96 agnd 97 eab15 98 eab16 99 eab17 100 edb0 101 edb1 102 edb2 103 dvcc 104 dgnd 105 edb3 106 edb4 107 edb5 108 edb6 109 edb7 110 edb8 111 dvcc 112 dgnd 113 edb9 114 edb10 115 edb11 116 edb12 117 edb13 118 edb14 119 dvcc 120 dgnd 121 edb15 122 edb16 123 edb17 124 edb18 125 edb19 126 qvccl 127 qgnd 128 edb20 129 dvcc 130 dgnd 131 edb21 132 edb22 133 edb23 134 irqd_ 135 irqc_
icba_o icba_o icba_o power gnd icba_o icba_o gnd power icba_o icba_o icba_o power gnd icba_o icba_o icba_o icba_io icba_io icba_io power gnd icba_io icba_io icba_io icba_io icba_io icba_io power gnd icba_io icba_io icba_io icba_io icba_io icba_io power gnd icba_io icba_io icba_io icba_io icba_io power gnd icba_io power gnd icba_io icba_io icba_io ip5b_i ip5b_i
MOTOROLA
DSP56367
F-3
IBIS Model
136 irqb_ ip5b_i 137 irqa_ ip5b_i 138 sdo4_1 ip5b_io 139 tdo ip5b_o 140 tdi ip5b_i 141 tck ip5b_i 142 tms ip5b_i 143 mosi ip5b_io 144 sda ip5b_io | [Model] ip5b_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | | [Model] ip5b_io Model_type I/O Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max)
F-4
DSP56367
MOTOROLA
IBIS Model
| -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 |
-5.21e+02 -4.69e+02 -4.18e+02 -3.67e+02 -3.16e+02 -2.65e+02 -2.14e+02 -1.63e+02 -1.13e+02 -7.83e+01 -4.43e+01 -1.02e+01 -5.10e-02 -3.65e-02 -2.65e-02 -1.62e-02 -5.49e-03 5.377e-03 1.516e-02 2.370e-02 3.098e-02 3.700e-02 4.175e-02 4.531e-02 4.779e-02 4.935e-02 5.013e-02 5.046e-02 5.063e-02 5.075e-02 5.085e-02 5.090e-02 4.771e-02 4.525e-02 4.657e-02 4.904e-02 5.221e-02 5.524e-02 5.634e-02 5.751e-02 5.634e-02 5.648e-02 5.664e-02 5.679e-02 5.693e-02 5.707e-02 5.722e-02 5.741e-02 5.766e-02 5.801e-02 5.824e-02
-3.65e+02 -3.30e+02 -2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.52e+01 -2.15e+01 -1.18e+00 -2.25e-02 -1.38e-02 -8.35e-03 -2.80e-03 2.744e-03 7.871e-03 1.252e-02 1.667e-02 2.026e-02 2.324e-02 2.553e-02 2.709e-02 2.803e-02 2.851e-02 2.876e-02 2.892e-02 2.904e-02 2.912e-02 2.876e-02 2.994e-02 3.321e-02 3.570e-02 3.801e-02 4.029e-02 4.253e-02 4.463e-02 4.645e-02 4.786e-02 4.881e-02 4.912e-02 4.795e-02 4.679e-02 4.688e-02 4.700e-02 4.712e-02 4.723e-02 4.733e-02 4.737e-02
-5.18e+02 -4.67e+02 -4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02 -2.12e+02 -1.61e+02 -1.10e+02 -7.58e+01 -4.17e+01 -7.69e+00 -5.63e-02 -4.28e-02 -3.12e-02 -1.91e-02 -6.52e-03 6.427e-03 1.823e-02 2.869e-02 3.776e-02 4.544e-02 5.171e-02 5.660e-02 6.023e-02 6.271e-02 6.419e-02 6.494e-02 6.525e-02 6.540e-02 6.549e-02 6.555e-02 6.561e-02 6.182e-02 6.049e-02 6.178e-02 6.450e-02 6.659e-02 6.867e-02 6.970e-02 6.938e-02 6.960e-02 6.983e-02 7.005e-02 7.026e-02 7.049e-02 7.074e-02 7.105e-02 7.147e-02 7.205e-02 7.242e-02
MOTOROLA
DSP56367
F-5
IBIS Model
[Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00
I(typ) 2.922e-04 2.881e-04 2.853e-04 2.836e-04 2.825e-04 2.819e-04 2.815e-04 2.813e-04 2.812e-04 2.811e-04 2.810e-04 2.809e-04 2.808e-04 2.997e-04 1.750e-02 1.048e-02 3.487e-03 -3.40e-03 -9.69e-03 -1.52e-02 -2.02e-02 -2.46e-02 -2.84e-02 -3.14e-02 -3.37e-02 -3.55e-02 -3.68e-02 -3.78e-02 -3.85e-02 -3.91e-02 -3.96e-02 -4.01e-02 -4.04e-02 -4.08e-02 -4.11e-02 -4.14e-02 -4.17e-02 -4.32e-02 -4.08e-01 -2.73e+01 -6.13e+01 -9.54e+01 -1.38e+02 -1.89e+02 -2.40e+02 -2.91e+02 -3.42e+02 -3.93e+02 -4.44e+02 -4.95e+02
I(min) 2.177e-04 2.175e-04 2.173e-04 2.172e-04 2.171e-04 2.170e-04 2.169e-04 2.167e-04 2.520e-04 3.078e-02 2.684e-02 2.277e-02 1.864e-02 1.447e-02 1.031e-02 6.181e-03 2.084e-03 -2.03e-03 -5.71e-03 -8.99e-03 -1.19e-02 -1.43e-02 -1.62e-02 -1.77e-02 -1.88e-02 -1.95e-02 -2.00e-02 -2.04e-02 -2.07e-02 -2.10e-02 -2.12e-02 -2.15e-02 -2.17e-02 -2.18e-02 -2.20e-02 -2.78e-02 -1.20e+00 -2.15e+01 -4.52e+01 -6.89e+01 -9.25e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02
I(max)
4.123e-04 4.021e-04 3.946e-04 3.893e-04 3.857e-04 3.834e-04 3.820e-04 3.812e-04 3.808e-04 3.806e-04 3.804e-04 3.802e-04 3.801e-04 3.799e-04 3.797e-04 3.776e-04 4.568e-03 -4.22e-03 -1.24e-02 -1.95e-02 -2.61e-02 -3.21e-02 -3.73e-02 -4.18e-02 -4.55e-02 -4.85e-02 -5.09e-02 -5.27e-02 -5.41e-02 -5.51e-02 -5.60e-02 -5.67e-02 -5.74e-02 -5.79e-02 -5.84e-02 -5.89e-02 -5.94e-02 -5.98e-02 -6.10e-02 -6.84e-02 -7.73e+00 -4.18e+01 -7.59e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02
F-6
DSP56367
MOTOROLA
IBIS Model
6.600e+00 -5.21e+02 -4.18e+02 -4.41e+02 | [GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.030/0.465 0.605/0.676 1.320/0.366 | | dV/dt_f 1.290/0.671 0.829/0.122 1.520/0.431 | | [Model] ip5b_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02
MOTOROLA
DSP56367
F-7
IBIS Model
-1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00
-1.13e+02 -7.83e+01 -4.43e+01 -1.02e+01 -5.10e-02 -3.65e-02 -2.65e-02 -1.62e-02 -5.49e-03 5.377e-03 1.516e-02 2.370e-02 3.098e-02 3.700e-02 4.175e-02 4.531e-02 4.779e-02 4.935e-02 5.013e-02 5.046e-02 5.063e-02 5.075e-02 5.085e-02 5.090e-02 4.771e-02 4.525e-02 4.657e-02 4.904e-02 5.221e-02 5.524e-02 5.634e-02 5.751e-02 5.634e-02 5.648e-02 5.664e-02 5.679e-02 5.693e-02 5.707e-02 5.722e-02 5.741e-02 5.766e-02 5.801e-02 5.824e-02
-9.25e+01 -6.88e+01 -4.52e+01 -2.15e+01 -1.18e+00 -2.25e-02 -1.38e-02 -8.35e-03 -2.80e-03 2.744e-03 7.871e-03 1.252e-02 1.667e-02 2.026e-02 2.324e-02 2.553e-02 2.709e-02 2.803e-02 2.851e-02 2.876e-02 2.892e-02 2.904e-02 2.912e-02 2.876e-02 2.994e-02 3.321e-02 3.570e-02 3.801e-02 4.029e-02 4.253e-02 4.463e-02 4.645e-02 4.786e-02 4.881e-02 4.912e-02 4.795e-02 4.679e-02 4.688e-02 4.700e-02 4.712e-02 4.723e-02 4.733e-02 4.737e-02
-1.10e+02 -7.58e+01 -4.17e+01 -7.69e+00 -5.63e-02 -4.28e-02 -3.12e-02 -1.91e-02 -6.52e-03 6.427e-03 1.823e-02 2.869e-02 3.776e-02 4.544e-02 5.171e-02 5.660e-02 6.023e-02 6.271e-02 6.419e-02 6.494e-02 6.525e-02 6.540e-02 6.549e-02 6.555e-02 6.561e-02 6.182e-02 6.049e-02 6.178e-02 6.450e-02 6.659e-02 6.867e-02 6.970e-02 6.938e-02 6.960e-02 6.983e-02 7.005e-02 7.026e-02 7.049e-02 7.074e-02 7.105e-02 7.147e-02 7.205e-02 7.242e-02
I(typ) 2.922e-04 2.881e-04 2.853e-04 2.836e-04 2.825e-04 2.819e-04
I(min) 2.177e-04 2.175e-04 2.173e-04 2.172e-04 2.171e-04 2.170e-04
I(max)
4.123e-04 4.021e-04 3.946e-04 3.893e-04 3.857e-04 3.834e-04
F-8
DSP56367
MOTOROLA
IBIS Model
-2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [GND_clamp] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00
2.815e-04 2.813e-04 2.812e-04 2.811e-04 2.810e-04 2.809e-04 2.808e-04 2.997e-04 1.750e-02 1.048e-02 3.487e-03 -3.40e-03 -9.69e-03 -1.52e-02 -2.02e-02 -2.46e-02 -2.84e-02 -3.14e-02 -3.37e-02 -3.55e-02 -3.68e-02 -3.78e-02 -3.85e-02 -3.91e-02 -3.96e-02 -4.01e-02 -4.04e-02 -4.08e-02 -4.11e-02 -4.14e-02 -4.17e-02 -4.32e-02 -4.08e-01 -2.73e+01 -6.13e+01 -9.54e+01 -1.38e+02 -1.89e+02 -2.40e+02 -2.91e+02 -3.42e+02 -3.93e+02 -4.44e+02 -4.95e+02 -5.21e+02
2.169e-04 2.167e-04 2.520e-04 3.078e-02 2.684e-02 2.277e-02 1.864e-02 1.447e-02 1.031e-02 6.181e-03 2.084e-03 -2.03e-03 -5.71e-03 -8.99e-03 -1.19e-02 -1.43e-02 -1.62e-02 -1.77e-02 -1.88e-02 -1.95e-02 -2.00e-02 -2.04e-02 -2.07e-02 -2.10e-02 -2.12e-02 -2.15e-02 -2.17e-02 -2.18e-02 -2.20e-02 -2.78e-02 -1.20e+00 -2.15e+01 -4.52e+01 -6.89e+01 -9.25e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.18e+02
3.820e-04 3.812e-04 3.808e-04 3.806e-04 3.804e-04 3.802e-04 3.801e-04 3.799e-04 3.797e-04 3.776e-04 4.568e-03 -4.22e-03 -1.24e-02 -1.95e-02 -2.61e-02 -3.21e-02 -3.73e-02 -4.18e-02 -4.55e-02 -4.85e-02 -5.09e-02 -5.27e-02 -5.41e-02 -5.51e-02 -5.60e-02 -5.67e-02 -5.74e-02 -5.79e-02 -5.84e-02 -5.89e-02 -5.94e-02 -5.98e-02 -6.10e-02 -6.84e-02 -7.73e+00 -4.18e+01 -7.59e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.41e+02
I(typ) -5.21e+02 -4.69e+02 -4.18e+02 -3.67e+02
I(min) -3.65e+02 -3.30e+02 -2.94e+02 -2.59e+02
I(max)
-5.18e+02 -4.67e+02 -4.16e+02 -3.65e+02
MOTOROLA
DSP56367
F-9
IBIS Model
-2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.61e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -9.69e-03 -1.18e+00 -7.81e-03 -7.00e-01 -2.83e-04 -5.70e-03 -8.42e-04 -5.00e-01 -1.35e-06 -4.53e-05 -1.00e-05 -3.00e-01 -1.31e-09 -3.74e-07 -8.58e-09 -1.00e-01 -2.92e-11 -3.00e-09 -3.64e-11 0.000e+00 -2.44e-11 -5.14e-10 -2.79e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.030/0.465 0.605/0.676 1.320/0.366 | | dV/dt_f 1.290/0.671 0.829/0.122 1.520/0.431 | | [Model] icba_io Model_type I/O Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.68e+00 -9.00e-01 -2.70e-02 -1.19e+00 -2.90e-02 -7.00e-01 -1.32e-02 -1.25e-02 -1.63e-02 -5.00e-01 -9.33e-03 -4.69e-03 -1.10e-02
F-10
DSP56367
MOTOROLA
IBIS Model
-3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01
-5.75e-03 -1.97e-03 1.945e-03 5.507e-03 8.649e-03 1.136e-02 1.364e-02 1.547e-02 1.688e-02 1.299e-01 1.366e-01 1.404e-01 1.423e-01 1.433e-01 1.440e-01 1.445e-01 1.450e-01 1.454e-01 1.458e-01 1.461e-01 1.464e-01 1.469e-01 1.490e-01 1.501e+00 1.813e+01 3.540e+01 5.269e+01 7.541e+01 1.012e+02 1.270e+02 1.527e+02 1.785e+02 2.043e+02 2.301e+02 2.559e+02 2.688e+02
-2.81e-03 -9.48e-04 9.285e-04 2.640e-03 4.168e-03 5.504e-03 6.636e-03 7.551e-03 8.240e-03 6.458e-02 6.746e-02 6.916e-02 7.006e-02 7.059e-02 7.098e-02 7.128e-02 7.154e-02 7.176e-02 7.196e-02 7.223e-02 8.810e-02 2.589e+00 1.451e+01 2.658e+01 3.866e+01 5.076e+01 6.461e+01 8.261e+01 1.006e+02 1.186e+02 1.366e+02 1.546e+02 1.726e+02 1.906e+02 2.086e+02 2.176e+02
-6.76e-03 -2.32e-03 2.307e-03 6.599e-03 1.048e-02 1.393e-02 1.693e-02 1.950e-02 2.162e-02 2.331e-02 1.755e-01 1.847e-01 1.907e-01 1.940e-01 1.958e-01 1.970e-01 1.979e-01 1.986e-01 1.993e-01 1.999e-01 2.004e-01 2.009e-01 2.015e-01 2.030e-01 2.385e-01 9.563e+00 2.682e+01 4.409e+01 6.258e+01 8.836e+01 1.141e+02 1.399e+02 1.657e+02 1.915e+02 2.173e+02 2.302e+02
I(typ) 2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 2.662e+01 9.360e+00 4.275e-02
I(min) 1.905e+02 1.725e+02 1.545e+02 1.365e+02 1.185e+02 1.005e+02 8.253e+01 6.454e+01 5.068e+01 3.859e+01 2.651e+01 1.444e+01 2.518e+00
I(max)
2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 2.662e+01 9.362e+00 4.663e-02
MOTOROLA
DSP56367
F-11
IBIS Model
-7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [GND_clamp] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00
8.208e-03 5.635e-03 3.370e-03 1.118e-03 -1.09e-03 -3.12e-03 -4.96e-03 -6.60e-03 -8.04e-03 -9.26e-03 -1.03e-02 -1.25e-01 -1.31e-01 -1.36e-01 -1.40e-01 -1.42e-01 -1.44e-01 -1.46e-01 -1.48e-01 -1.49e-01 -1.50e-01 -1.52e-01 -1.53e-01 -1.54e-01 -1.57e-01 -5.25e-01 -2.74e+01 -6.14e+01 -9.55e+01 -1.38e+02 -1.89e+02 -2.40e+02 -2.91e+02 -3.42e+02 -3.93e+02 -4.44e+02 -4.95e+02 -5.21e+02
2.012e-02 3.518e-03 2.053e-03 6.789e-04 -6.56e-04 -1.86e-03 -2.93e-03 -3.87e-03 -4.66e-03 -5.30e-03 -6.55e-02 -6.93e-02 -7.19e-02 -7.38e-02 -7.53e-02 -7.65e-02 -7.76e-02 -7.85e-02 -7.93e-02 -8.00e-02 -8.06e-02 -8.13e-02 -8.84e-02 -1.26e+00 -2.16e+01 -4.53e+01 -6.89e+01 -9.26e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.19e+02
1.070e-02 7.068e-03 4.233e-03 1.410e-03 -1.38e-03 -3.99e-03 -6.39e-03 -8.59e-03 -1.06e-02 -1.23e-02 -1.38e-02 -1.70e-01 -1.82e-01 -1.91e-01 -1.97e-01 -2.03e-01 -2.07e-01 -2.10e-01 -2.13e-01 -2.15e-01 -2.17e-01 -2.19e-01 -2.21e-01 -2.22e-01 -2.24e-01 -2.27e-01 -2.38e-01 -7.90e+00 -4.20e+01 -7.60e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.42e+02
I(typ) -5.20e+02 -4.69e+02 -4.18e+02 -3.67e+02 -3.16e+02 -2.65e+02 -2.14e+02 -1.63e+02 -1.13e+02 -7.83e+01 -4.43e+01
I(min) -3.65e+02 -3.30e+02 -2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.52e+01
I(max)
-5.18e+02 -4.67e+02 -4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02 -2.12e+02 -1.60e+02 -1.10e+02 -7.58e+01 -4.17e+01
F-12
DSP56367
MOTOROLA
IBIS Model
-1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -1.22e-02 -1.18e+00 -1.17e-02 -7.00e-01 -5.18e-04 -6.62e-03 -1.56e-03 -5.00e-01 -2.43e-06 -6.64e-05 -1.80e-05 -3.00e-01 -2.33e-09 -6.35e-07 -1.54e-08 -1.00e-01 -2.10e-11 -6.31e-09 -2.99e-11 0.000e+00 -1.70e-11 -1.95e-09 -1.91e-11 | [POWER_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.236e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.358e+00 1.444e+01 9.359e+00 -9.00e-01 3.399e-02 2.517e+00 3.554e-02 -7.00e-01 3.426e-04 1.577e-02 9.211e-04 -5.00e-01 2.840e-06 7.857e-05 1.655e-05 -3.00e-01 3.401e-09 6.836e-07 1.946e-08 -1.00e-01 6.162e-11 7.379e-09 7.622e-11 0.000e+00 5.758e-11 2.438e-09 6.240e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.680/0.164 1.360/0.329 1.900/0.124 | | dV/dt_f 1.690/0.219 1.310/0.442 1.880/0.155 | | [Model] icba_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02
MOTOROLA
DSP56367
F-13
IBIS Model
-2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage |
-4.18e+02 -3.67e+02 -3.16e+02 -2.65e+02 -2.14e+02 -1.63e+02 -1.13e+02 -7.83e+01 -4.43e+01 -1.02e+01 -2.70e-02 -1.32e-02 -9.33e-03 -5.75e-03 -1.97e-03 1.945e-03 5.507e-03 8.649e-03 1.136e-02 1.364e-02 1.547e-02 1.688e-02 1.299e-01 1.366e-01 1.404e-01 1.423e-01 1.433e-01 1.440e-01 1.445e-01 1.450e-01 1.454e-01 1.458e-01 1.461e-01 1.464e-01 1.469e-01 1.490e-01 1.501e+00 1.813e+01 3.540e+01 5.269e+01 7.541e+01 1.012e+02 1.270e+02 1.527e+02 1.785e+02 2.043e+02 2.301e+02 2.559e+02 2.688e+02
-2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.52e+01 -2.15e+01 -1.19e+00 -1.25e-02 -4.69e-03 -2.81e-03 -9.48e-04 9.285e-04 2.640e-03 4.168e-03 5.504e-03 6.636e-03 7.551e-03 8.240e-03 6.458e-02 6.746e-02 6.916e-02 7.006e-02 7.059e-02 7.098e-02 7.128e-02 7.154e-02 7.176e-02 7.196e-02 7.223e-02 8.810e-02 2.589e+00 1.451e+01 2.658e+01 3.866e+01 5.076e+01 6.461e+01 8.261e+01 1.006e+02 1.186e+02 1.366e+02 1.546e+02 1.726e+02 1.906e+02 2.086e+02 2.176e+02
-4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02 -2.12e+02 -1.60e+02 -1.10e+02 -7.58e+01 -4.17e+01 -7.68e+00 -2.90e-02 -1.63e-02 -1.10e-02 -6.76e-03 -2.32e-03 2.307e-03 6.599e-03 1.048e-02 1.393e-02 1.693e-02 1.950e-02 2.162e-02 2.331e-02 1.755e-01 1.847e-01 1.907e-01 1.940e-01 1.958e-01 1.970e-01 1.979e-01 1.986e-01 1.993e-01 1.999e-01 2.004e-01 2.009e-01 2.015e-01 2.030e-01 2.385e-01 9.563e+00 2.682e+01 4.409e+01 6.258e+01 8.836e+01 1.141e+02 1.399e+02 1.657e+02 1.915e+02 2.173e+02 2.302e+02
I(typ)
I(min)
I(max)
F-14
DSP56367
MOTOROLA
IBIS Model
-3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [GND_clamp]
2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 2.662e+01 9.360e+00 4.275e-02 8.208e-03 5.635e-03 3.370e-03 1.118e-03 -1.09e-03 -3.12e-03 -4.96e-03 -6.60e-03 -8.04e-03 -9.26e-03 -1.03e-02 -1.25e-01 -1.31e-01 -1.36e-01 -1.40e-01 -1.42e-01 -1.44e-01 -1.46e-01 -1.48e-01 -1.49e-01 -1.50e-01 -1.52e-01 -1.53e-01 -1.54e-01 -1.57e-01 -5.25e-01 -2.74e+01 -6.14e+01 -9.55e+01 -1.38e+02 -1.89e+02 -2.40e+02 -2.91e+02 -3.42e+02 -3.93e+02 -4.44e+02 -4.95e+02 -5.21e+02
1.905e+02 1.725e+02 1.545e+02 1.365e+02 1.185e+02 1.005e+02 8.253e+01 6.454e+01 5.068e+01 3.859e+01 2.651e+01 1.444e+01 2.518e+00 2.012e-02 3.518e-03 2.053e-03 6.789e-04 -6.56e-04 -1.86e-03 -2.93e-03 -3.87e-03 -4.66e-03 -5.30e-03 -6.55e-02 -6.93e-02 -7.19e-02 -7.38e-02 -7.53e-02 -7.65e-02 -7.76e-02 -7.85e-02 -7.93e-02 -8.00e-02 -8.06e-02 -8.13e-02 -8.84e-02 -1.26e+00 -2.16e+01 -4.53e+01 -6.89e+01 -9.26e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.19e+02
2.686e+02 2.428e+02 2.170e+02 1.912e+02 1.655e+02 1.397e+02 1.139e+02 8.814e+01 6.237e+01 4.389e+01 2.662e+01 9.362e+00 4.663e-02 1.070e-02 7.068e-03 4.233e-03 1.410e-03 -1.38e-03 -3.99e-03 -6.39e-03 -8.59e-03 -1.06e-02 -1.23e-02 -1.38e-02 -1.70e-01 -1.82e-01 -1.91e-01 -1.97e-01 -2.03e-01 -2.07e-01 -2.10e-01 -2.13e-01 -2.15e-01 -2.17e-01 -2.19e-01 -2.21e-01 -2.22e-01 -2.24e-01 -2.27e-01 -2.38e-01 -7.90e+00 -4.20e+01 -7.60e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.42e+02
MOTOROLA
DSP56367
F-15
IBIS Model
|voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.12e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.43e+01 -4.52e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -1.22e-02 -1.18e+00 -1.17e-02 -7.00e-01 -5.18e-04 -6.62e-03 -1.56e-03 -5.00e-01 -2.43e-06 -6.64e-05 -1.80e-05 -3.00e-01 -2.33e-09 -6.35e-07 -1.54e-08 -1.00e-01 -2.10e-11 -6.31e-09 -2.99e-11 0.000e+00 -1.70e-11 -1.95e-09 -1.91e-11 | [POWER_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 2.686e+02 1.905e+02 2.686e+02 -3.10e+00 2.428e+02 1.725e+02 2.428e+02 -2.90e+00 2.170e+02 1.545e+02 2.170e+02 -2.70e+00 1.912e+02 1.365e+02 1.912e+02 -2.50e+00 1.655e+02 1.185e+02 1.655e+02 -2.30e+00 1.397e+02 1.005e+02 1.397e+02 -2.10e+00 1.139e+02 8.253e+01 1.139e+02 -1.90e+00 8.814e+01 6.454e+01 8.814e+01 -1.70e+00 6.236e+01 5.068e+01 6.237e+01 -1.50e+00 4.389e+01 3.859e+01 4.389e+01 -1.30e+00 2.662e+01 2.651e+01 2.662e+01 -1.10e+00 9.358e+00 1.444e+01 9.359e+00 -9.00e-01 3.399e-02 2.517e+00 3.554e-02 -7.00e-01 3.426e-04 1.577e-02 9.211e-04 -5.00e-01 2.840e-06 7.857e-05 1.655e-05 -3.00e-01 3.401e-09 6.836e-07 1.946e-08 -1.00e-01 6.162e-11 7.379e-09 7.622e-11 0.000e+00 5.758e-11 2.438e-09 6.240e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.680/0.164 1.360/0.329 1.900/0.124 | | dV/dt_f 1.690/0.219 1.310/0.442 1.880/0.155 |
F-16
DSP56367
MOTOROLA
IBIS Model
| [Model] icbc_o Model_type 3-state Polarity Non-Inverting C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.18e+02 -3.10e+00 -4.69e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.16e+02 -2.70e+00 -3.67e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.14e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.63e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.25e+01 -1.10e+02 -1.50e+00 -7.83e+01 -6.88e+01 -7.58e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.67e+00 -9.00e-01 -2.51e-02 -1.18e+00 -2.65e-02 -7.00e-01 -1.30e-02 -1.16e-02 -1.58e-02 -5.00e-01 -9.33e-03 -4.67e-03 -1.10e-02 -3.00e-01 -5.75e-03 -2.81e-03 -6.76e-03 -1.00e-01 -1.97e-03 -9.48e-04 -2.32e-03 1.000e-01 1.945e-03 9.285e-04 2.307e-03 3.000e-01 5.507e-03 2.640e-03 6.599e-03 5.000e-01 8.649e-03 4.168e-03 1.048e-02 7.000e-01 1.136e-02 5.504e-03 1.393e-02 9.000e-01 1.364e-02 6.636e-03 1.693e-02 1.100e+00 1.547e-02 7.551e-03 1.950e-02 1.300e+00 1.688e-02 8.240e-03 2.162e-02 1.500e+00 9.632e-02 4.783e-02 2.331e-02 1.700e+00 1.012e-01 4.994e-02 1.302e-01 1.900e+00 1.039e-01 5.118e-02 1.369e-01 2.100e+00 1.053e-01 5.184e-02 1.412e-01 2.300e+00 1.060e-01 5.223e-02 1.436e-01 2.500e+00 1.065e-01 5.251e-02 1.449e-01 2.700e+00 1.069e-01 5.274e-02 1.458e-01 2.900e+00 1.073e-01 5.293e-02 1.464e-01 3.100e+00 1.076e-01 5.309e-02 1.470e-01 3.300e+00 1.078e-01 5.324e-02 1.475e-01 3.500e+00 1.081e-01 5.344e-02 1.479e-01 3.700e+00 1.083e-01 6.705e-02 1.483e-01 3.900e+00 1.086e-01 2.529e+00 1.487e-01 4.100e+00 1.103e-01 1.438e+01 1.491e-01 4.300e+00 1.437e+00 2.638e+01 1.503e-01 4.500e+00 1.800e+01 3.839e+01 1.810e-01 4.700e+00 3.519e+01 5.041e+01 9.452e+00 4.900e+00 5.241e+01 6.419e+01 2.664e+01
MOTOROLA
DSP56367
F-17
IBIS Model
5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00 1.500e+00 1.700e+00 1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00
7.505e+01 1.007e+02 1.264e+02 1.522e+02 1.779e+02 2.036e+02 2.293e+02 2.550e+02 2.678e+02
8.210e+01 1.000e+02 1.179e+02 1.359e+02 1.538e+02 1.717e+02 1.896e+02 2.075e+02 2.165e+02
4.384e+01 6.224e+01 8.794e+01 1.136e+02 1.394e+02 1.651e+02 1.908e+02 2.165e+02 2.293e+02
I(typ) 2.677e+02 2.420e+02 2.163e+02 1.906e+02 1.649e+02 1.392e+02 1.135e+02 8.778e+01 6.208e+01 4.368e+01 2.649e+01 9.302e+00 3.838e-02 8.115e-03 5.634e-03 3.370e-03 1.118e-03 -1.09e-03 -3.12e-03 -4.96e-03 -6.60e-03 -8.04e-03 -9.26e-03 -1.03e-02 -9.03e-02 -9.49e-02 -9.84e-02 -1.01e-01 -1.03e-01 -1.05e-01 -1.06e-01 -1.07e-01 -1.08e-01 -1.09e-01 -1.10e-01 -1.11e-01 -1.11e-01 -1.14e-01 -4.76e-01 -2.73e+01
I(min) 1.896e+02 1.716e+02 1.537e+02 1.358e+02 1.179e+02 9.996e+01 8.205e+01 6.413e+01 5.035e+01 3.834e+01 2.633e+01 1.433e+01 2.477e+00 1.789e-02 3.503e-03 2.053e-03 6.789e-04 -6.56e-04 -1.86e-03 -2.93e-03 -3.87e-03 -4.66e-03 -5.30e-03 -4.75e-02 -5.02e-02 -5.21e-02 -5.34e-02 -5.45e-02 -5.54e-02 -5.62e-02 -5.68e-02 -5.74e-02 -5.79e-02 -5.84e-02 -5.89e-02 -6.49e-02 -1.23e+00 -2.16e+01 -4.52e+01 -6.89e+01
I(max)
2.677e+02 2.420e+02 2.163e+02 1.906e+02 1.649e+02 1.392e+02 1.135e+02 8.778e+01 6.208e+01 4.368e+01 2.649e+01 9.303e+00 4.183e-02 1.045e-02 7.064e-03 4.233e-03 1.410e-03 -1.38e-03 -3.99e-03 -6.39e-03 -8.59e-03 -1.06e-02 -1.23e-02 -1.41e-02 -1.23e-01 -1.31e-01 -1.38e-01 -1.43e-01 -1.47e-01 -1.50e-01 -1.52e-01 -1.54e-01 -1.56e-01 -1.57e-01 -1.59e-01 -1.60e-01 -1.61e-01 -1.62e-01 -1.64e-01 -1.73e-01
F-18
DSP56367
MOTOROLA
IBIS Model
4.700e+00 -6.14e+01 4.900e+00 -9.54e+01 5.100e+00 -1.38e+02 5.300e+00 -1.89e+02 5.500e+00 -2.40e+02 5.700e+00 -2.91e+02 5.900e+00 -3.42e+02 6.100e+00 -3.93e+02 6.300e+00 -4.44e+02 6.500e+00 -4.95e+02 6.600e+00 -5.20e+02 | [GND_clamp] |voltage I(typ) | -3.30e+00 -5.20e+02 -3.10e+00 -4.69e+02 -2.90e+00 -4.18e+02 -2.70e+00 -3.67e+02 -2.50e+00 -3.16e+02 -2.30e+00 -2.65e+02 -2.10e+00 -2.14e+02 -1.90e+00 -1.63e+02 -1.70e+00 -1.13e+02 -1.50e+00 -7.83e+01 -1.30e+00 -4.42e+01 -1.10e+00 -1.02e+01 -9.00e-01 -1.03e-02 -7.00e-01 -3.74e-04 -5.00e-01 -1.72e-06 -3.00e-01 -1.67e-09 -1.00e-01 -2.03e-11 0.000e+00 -1.69e-11 | [POWER_clamp] |voltage I(typ) | -3.30e+00 2.677e+02 -3.10e+00 2.420e+02 -2.90e+00 2.163e+02 -2.70e+00 1.906e+02 -2.50e+00 1.649e+02 -2.30e+00 1.392e+02 -2.10e+00 1.135e+02 -1.90e+00 8.778e+01 -1.70e+00 6.208e+01 -1.50e+00 4.368e+01 -1.30e+00 2.649e+01 -1.10e+00 9.300e+00 -9.00e-01 2.962e-02 -7.00e-01 2.501e-04 -5.00e-01 2.066e-06 -3.00e-01 2.487e-09
-9.25e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.59e+02 -2.94e+02 -3.30e+02 -3.65e+02 -4.01e+02 -4.18e+02
-7.82e+00 -4.19e+01 -7.59e+01 -1.11e+02 -1.61e+02 -2.12e+02 -2.63e+02 -3.14e+02 -3.65e+02 -4.16e+02 -4.41e+02
I(min) -3.65e+02 -3.30e+02 -2.94e+02 -2.59e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.25e+01 -6.88e+01 -4.51e+01 -2.15e+01 -1.17e+00 -5.73e-03 -5.06e-05 -4.65e-07 -4.80e-09 -1.61e-09
I(max)
-5.18e+02 -4.67e+02 -4.16e+02 -3.65e+02 -3.14e+02 -2.63e+02 -2.11e+02 -1.60e+02 -1.10e+02 -7.58e+01 -4.17e+01 -7.66e+00 -9.27e-03 -1.14e-03 -1.28e-05 -1.10e-08 -2.71e-11 -1.89e-11
I(min) 1.896e+02 1.716e+02 1.537e+02 1.358e+02 1.179e+02 9.996e+01 8.205e+01 6.413e+01 5.035e+01 3.834e+01 2.633e+01 1.433e+01 2.475e+00 1.354e-02 6.280e-05 5.128e-07
I(max)
2.677e+02 2.420e+02 2.163e+02 1.906e+02 1.649e+02 1.392e+02 1.135e+02 8.778e+01 6.208e+01 4.368e+01 2.649e+01 9.301e+00 3.075e-02 6.708e-04 1.204e-05 1.417e-08
MOTOROLA
DSP56367
F-19
IBIS Model
-1.00e-01 5.672e-11 5.639e-09 6.832e-11 0.000e+00 5.334e-11 1.992e-09 5.783e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.570/0.200 1.210/0.411 1.810/0.149 | | dV/dt_f 1.590/0.304 1.170/0.673 1.800/0.205 | | [Model] ipbw_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02 -3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02 -2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02 -1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.16e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.64e+00 -9.00e-01 -7.17e-03 -1.16e+00 -4.87e-03 -7.00e-01 -1.14e-04 -4.39e-03 -3.03e-04 -5.00e-01 -4.86e-07 -2.55e-05 -2.73e-06 -3.00e-01 -5.19e-10 -1.91e-07 -2.57e-09 -1.00e-01 -1.91e-11 -2.47e-09 -2.19e-11 0.000e+00 -1.68e-11 -1.17e-09 -1.84e-11 | [POWER_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02
F-20
DSP56367
MOTOROLA
IBIS Model
-2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.634e+01 2.613e+01 2.634e+01 -1.10e+00 9.237e+00 1.421e+01 9.237e+00 -9.00e-01 2.454e-02 2.430e+00 2.488e-02 -7.00e-01 8.741e-05 1.104e-02 2.050e-04 -5.00e-01 6.316e-07 4.079e-05 2.961e-06 -3.00e-01 8.479e-10 2.484e-07 3.721e-09 -1.00e-01 4.420e-11 3.001e-09 4.943e-11 0.000e+00 4.215e-11 1.346e-09 4.543e-11 | | [Model] ipbw_io Model_type I/O Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [Pulldown] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.20e+02 -3.65e+02 -5.17e+02 -3.10e+00 -4.69e+02 -3.29e+02 -4.66e+02 -2.90e+00 -4.18e+02 -2.94e+02 -4.15e+02 -2.70e+00 -3.67e+02 -2.58e+02 -3.64e+02 -2.50e+00 -3.16e+02 -2.23e+02 -3.13e+02 -2.30e+00 -2.65e+02 -1.88e+02 -2.62e+02 -2.10e+00 -2.14e+02 -1.52e+02 -2.11e+02 -1.90e+00 -1.63e+02 -1.17e+02 -1.60e+02 -1.70e+00 -1.13e+02 -9.24e+01 -1.10e+02 -1.50e+00 -7.82e+01 -6.87e+01 -7.57e+01 -1.30e+00 -4.42e+01 -4.51e+01 -4.17e+01 -1.10e+00 -1.02e+01 -2.15e+01 -7.66e+00 -9.00e-01 -3.69e-02 -1.17e+00 -3.79e-02 -7.00e-01 -2.52e-02 -1.67e-02 -2.81e-02 -5.00e-01 -1.83e-02 -9.77e-03 -2.04e-02 -3.00e-01 -1.11e-02 -5.89e-03 -1.24e-02 -1.00e-01 -3.77e-03 -1.98e-03 -4.20e-03 1.000e-01 3.729e-03 1.940e-03 4.177e-03 3.000e-01 1.076e-02 5.578e-03 1.216e-02 5.000e-01 1.723e-02 8.907e-03 1.965e-02 7.000e-01 2.311e-02 1.191e-02 2.663e-02 9.000e-01 2.836e-02 1.455e-02 3.305e-02 1.100e+00 3.292e-02 1.680e-02 3.887e-02 1.300e+00 3.675e-02 1.862e-02 4.404e-02 1.500e+00 3.979e-02 1.997e-02 4.850e-02 1.700e+00 4.205e-02 2.085e-02 5.223e-02
MOTOROLA
DSP56367
F-21
IBIS Model
1.900e+00 2.100e+00 2.300e+00 2.500e+00 2.700e+00 2.900e+00 3.100e+00 3.300e+00 3.500e+00 3.700e+00 3.900e+00 4.100e+00 4.300e+00 4.500e+00 4.700e+00 4.900e+00 5.100e+00 5.300e+00 5.500e+00 5.700e+00 5.900e+00 6.100e+00 6.300e+00 6.500e+00 6.600e+00 | [Pullup] |voltage | -3.30e+00 -3.10e+00 -2.90e+00 -2.70e+00 -2.50e+00 -2.30e+00 -2.10e+00 -1.90e+00 -1.70e+00 -1.50e+00 -1.30e+00 -1.10e+00 -9.00e-01 -7.00e-01 -5.00e-01 -3.00e-01 -1.00e-01 1.000e-01 3.000e-01 5.000e-01 7.000e-01 9.000e-01 1.100e+00 1.300e+00
4.347e-02 4.413e-02 4.445e-02 4.465e-02 4.479e-02 4.492e-02 4.502e-02 4.511e-02 4.519e-02 4.526e-02 4.536e-02 4.614e-02 1.344e+00 1.783e+01 3.495e+01 5.208e+01 7.463e+01 1.002e+02 1.259e+02 1.515e+02 1.771e+02 2.027e+02 2.283e+02 2.539e+02 2.667e+02
2.136e-02 2.162e-02 2.176e-02 2.186e-02 2.194e-02 2.200e-02 2.206e-02 2.211e-02 2.219e-02 3.324e-02 2.452e+00 1.423e+01 2.615e+01 3.808e+01 5.001e+01 6.371e+01 8.154e+01 9.937e+01 1.172e+02 1.350e+02 1.529e+02 1.707e+02 1.885e+02 2.064e+02 2.153e+02
5.518e-02 5.728e-02 5.843e-02 5.899e-02 5.931e-02 5.953e-02 5.971e-02 5.986e-02 5.999e-02 6.010e-02 6.021e-02 6.032e-02 6.065e-02 8.548e-02 9.298e+00 2.640e+01 4.352e+01 6.184e+01 8.745e+01 1.131e+02 1.387e+02 1.643e+02 1.899e+02 2.155e+02 2.283e+02
I(typ) 2.667e+02 2.411e+02 2.155e+02 1.898e+02 1.642e+02 1.386e+02 1.130e+02 8.739e+01 6.178e+01 4.346e+01 2.635e+01 9.243e+00 5.536e-02 2.847e-02 2.025e-02 1.208e-02 3.994e-03 -3.88e-03 -1.11e-02 -1.76e-02 -2.35e-02 -2.86e-02 -3.30e-02 -3.65e-02
I(min) 1.885e+02 1.707e+02 1.528e+02 1.350e+02 1.172e+02 9.935e+01 8.152e+01 6.369e+01 4.999e+01 3.806e+01 2.613e+01 1.421e+01 2.435e+00 2.689e-02 1.265e-02 7.503e-03 2.474e-03 -2.38e-03 -6.76e-03 -1.06e-02 -1.40e-02 -1.69e-02 -1.93e-02 -2.10e-02
I(max)
2.667e+02 2.411e+02 2.155e+02 1.898e+02 1.642e+02 1.386e+02 1.130e+02 8.739e+01 6.178e+01 4.346e+01 2.635e+01 9.245e+00 6.260e-02 3.437e-02 2.451e-02 1.467e-02 4.868e-03 -4.76e-03 -1.37e-02 -2.20e-02 -2.95e-02 -3.63e-02 -4.23e-02 -4.75e-02
F-22
DSP56367
MOTOROLA
IBIS Model
1.500e+00 -3.92e-02 1.700e+00 -4.12e-02 1.900e+00 -4.26e-02 2.100e+00 -4.36e-02 2.300e+00 -4.43e-02 2.500e+00 -4.49e-02 2.700e+00 -4.54e-02 2.900e+00 -4.58e-02 3.100e+00 -4.61e-02 3.300e+00 -4.65e-02 3.500e+00 -4.68e-02 3.700e+00 -4.70e-02 3.900e+00 -4.73e-02 4.100e+00 -4.81e-02 4.300e+00 -4.00e-01 4.500e+00 -2.72e+01 4.700e+00 -6.12e+01 4.900e+00 -9.52e+01 5.100e+00 -1.37e+02 5.300e+00 -1.88e+02 5.500e+00 -2.39e+02 5.700e+00 -2.90e+02 5.900e+00 -3.41e+02 6.100e+00 -3.92e+02 6.300e+00 -4.43e+02 6.500e+00 -4.94e+02 6.600e+00 -5.20e+02 | [GND_clamp] |voltage I(typ) | -3.30e+00 -5.20e+02 -3.10e+00 -4.69e+02 -2.90e+00 -4.18e+02 -2.70e+00 -3.67e+02 -2.50e+00 -3.16e+02 -2.30e+00 -2.65e+02 -2.10e+00 -2.14e+02 -1.90e+00 -1.63e+02 -1.70e+00 -1.13e+02 -1.50e+00 -7.82e+01 -1.30e+00 -4.42e+01 -1.10e+00 -1.02e+01 -9.00e-01 -7.17e-03 -7.00e-01 -1.14e-04 -5.00e-01 -4.86e-07 -3.00e-01 -5.19e-10 -1.00e-01 -1.91e-11 0.000e+00 -1.68e-11 | [POWER_clamp] |voltage I(typ) |
-2.22e-02 -2.29e-02 -2.35e-02 -2.38e-02 -2.42e-02 -2.44e-02 -2.47e-02 -2.49e-02 -2.50e-02 -2.52e-02 -2.54e-02 -2.99e-02 -1.19e+00 -2.15e+01 -4.51e+01 -6.87e+01 -9.24e+01 -1.17e+02 -1.52e+02 -1.88e+02 -2.23e+02 -2.58e+02 -2.94e+02 -3.29e+02 -3.65e+02 -4.00e+02 -4.18e+02
-5.17e-02 -5.51e-02 -5.77e-02 -5.97e-02 -6.11e-02 -6.22e-02 -6.31e-02 -6.38e-02 -6.44e-02 -6.49e-02 -6.54e-02 -6.58e-02 -6.62e-02 -6.66e-02 -6.72e-02 -7.21e-02 -7.70e+00 -4.17e+01 -7.57e+01 -1.10e+02 -1.60e+02 -2.11e+02 -2.62e+02 -3.13e+02 -3.64e+02 -4.15e+02 -4.41e+02
I(min) -3.65e+02 -3.29e+02 -2.94e+02 -2.58e+02 -2.23e+02 -1.88e+02 -1.52e+02 -1.17e+02 -9.24e+01 -6.87e+01 -4.51e+01 -2.15e+01 -1.16e+00 -4.39e-03 -2.55e-05 -1.91e-07 -2.47e-09 -1.17e-09
I(max)
-5.17e+02 -4.66e+02 -4.15e+02 -3.64e+02 -3.13e+02 -2.62e+02 -2.11e+02 -1.60e+02 -1.10e+02 -7.57e+01 -4.16e+01 -7.64e+00 -4.87e-03 -3.03e-04 -2.73e-06 -2.57e-09 -2.19e-11 -1.84e-11
I(min)
I(max)
MOTOROLA
DSP56367
F-23
IBIS Model
-3.30e+00 2.667e+02 1.885e+02 2.667e+02 -3.10e+00 2.411e+02 1.707e+02 2.411e+02 -2.90e+00 2.155e+02 1.528e+02 2.155e+02 -2.70e+00 1.898e+02 1.350e+02 1.898e+02 -2.50e+00 1.642e+02 1.172e+02 1.642e+02 -2.30e+00 1.386e+02 9.935e+01 1.386e+02 -2.10e+00 1.130e+02 8.152e+01 1.130e+02 -1.90e+00 8.739e+01 6.369e+01 8.739e+01 -1.70e+00 6.178e+01 4.999e+01 6.178e+01 -1.50e+00 4.346e+01 3.806e+01 4.346e+01 -1.30e+00 2.634e+01 2.613e+01 2.634e+01 -1.10e+00 9.237e+00 1.421e+01 9.237e+00 -9.00e-01 2.454e-02 2.430e+00 2.488e-02 -7.00e-01 8.741e-05 1.104e-02 2.050e-04 -5.00e-01 6.316e-07 4.079e-05 2.961e-06 -3.00e-01 8.479e-10 2.484e-07 3.721e-09 -1.00e-01 4.420e-11 3.001e-09 4.943e-11 0.000e+00 4.215e-11 1.346e-09 4.543e-11 | [Ramp] R_load = 50.00 |voltage I(typ) I(min) I(max) | | dV/dt_r 1.140/0.494 0.699/0.978 1.400/0.354 | | dV/dt_f 1.150/0.505 0.642/0.956 1.350/0.350 | | [Model] iexlh_i Model_type Input Polarity Non-Inverting Vinl= 0.8000v Vinh= 2.000v C_comp 5.00pF 5.00pF 5.00pF | | [Voltage Range] 3.3v 3v 3.6v [GND_clamp] |voltage I(typ) I(min) I(max) | -3.30e+00 -5.21e+02 -3.66e+02 -5.18e+02 -3.10e+00 -4.70e+02 -3.30e+02 -4.67e+02 -2.90e+00 -4.19e+02 -2.95e+02 -4.16e+02 -2.70e+00 -3.68e+02 -2.59e+02 -3.65e+02 -2.50e+00 -3.17e+02 -2.24e+02 -3.14e+02 -2.30e+00 -2.66e+02 -1.89e+02 -2.63e+02 -2.10e+00 -2.15e+02 -1.53e+02 -2.12e+02 -1.90e+00 -1.64e+02 -1.18e+02 -1.61e+02 -1.70e+00 -1.14e+02 -9.34e+01 -1.11e+02 -1.50e+00 -7.93e+01 -6.98e+01 -7.68e+01 -1.30e+00 -4.53e+01 -4.62e+01 -4.28e+01
F-24
DSP56367
MOTOROLA
IBIS Model
-1.10e+00 -1.13e+01 -9.00e-01 -7.94e-03 -7.00e-01 -1.62e-06 -5.00e-01 -3.45e-10 -3.00e-01 -1.29e-11 -1.00e-01 -1.10e-11 0.000e+00 -1.01e-11 | [POWER_clamp] |voltage I(typ) | -3.30e+00 2.653e+02 -3.10e+00 2.398e+02 -2.90e+00 2.143e+02 -2.70e+00 1.888e+02 -2.50e+00 1.633e+02 -2.30e+00 1.378e+02 -2.10e+00 1.123e+02 -1.90e+00 8.682e+01 -1.70e+00 6.133e+01 -1.50e+00 4.313e+01 -1.30e+00 2.614e+01 -1.10e+00 9.145e+00 -9.00e-01 1.797e-02 -7.00e-01 3.667e-06 -5.00e-01 7.730e-10 -3.00e-01 2.293e-11 -1.00e-01 2.096e-11 0.000e+00 2.004e-11 | [End]
-2.26e+01 -1.87e+00 -5.11e-03 -1.40e-05 -3.90e-08 -8.67e-10 -7.13e-10
-8.78e+00 -3.77e-03 -7.69e-07 -1.72e-10 -1.38e-11 -1.19e-11 -1.10e-11
I(min) 1.870e+02 1.693e+02 1.516e+02 1.339e+02 1.162e+02 9.847e+01 8.076e+01 6.305e+01 4.947e+01 3.766e+01 2.585e+01 1.404e+01 2.364e+00 7.589e-03 2.072e-05 5.767e-08 1.163e-09 9.618e-10
I(max)
2.653e+02 2.398e+02 2.143e+02 1.888e+02 1.633e+02 1.378e+02 1.123e+02 8.682e+01 6.133e+01 4.313e+01 2.614e+01 9.145e+00 1.797e-02 3.667e-06 7.748e-10 2.476e-11 2.278e-11 2.186e-11
MOTOROLA
DSP56367
F-25
IBIS Model
F-26
DSP56367
MOTOROLA
Index
Numerics
5 V tolerance, 2-1, 2-1 registers, 1-6 data bus, 2-1, 2-1 Data Output bit (DO), 13-11 DAX, 2-1, 2-1, 2-20 Block Transferred Interrupt Handling, 12-13 Initiating A Transmit Session, 12-12 Transmit Register Empty Interrupt Handling, 12-13 DAX Audio Data register Empty (XADE) status flag, 12-9 DAX Audio Data Registers (XADRA/XADRB), 12-5 DAX Audio Data Shift Register (XADSR), 12-6, 12-6 DAX biphase encoder, 12-10 DAX Block transfer (XBLK) flag, 12-9 DAX Channel A Channel status (XCA) bit, 12-7 DAX Channel A User data (XUA) bit, 12-6 DAX Channel A Validity (XVA) bit, 12-6 DAX Channel B Channel Status (XCB) bit, 12-7 DAX Channel B User Data (XUB) bit, 12-7 DAX Channel B Validity (XVB) bit, 12-7 DAX Clock input Select bits, 12-8 DAX clock multiplexer, 12-11 DAX clock selection, 12-8 DAX Control Register (XCTR), 12-7 DAX internal architecture, 12-5 DAX Interrupt Enable (XIEN) bit, 12-8, 12-8, 12-8 DAX Non-Audio Data Buffer (XNADBUF), 12-7 DAX Operation During Stop, 12-15 DAX Parity Generator (PRTYG), 12-10 DAX preamble generator, 12-10 DAX Preamble sequence, 12-11, 12-15 DAX Programming Considerations, 12-12 DAX programming model, 12-4 DAX Status Register (XSTR), 12-9 DAX Transmit Underrun error (XAUR) status flag, 12-9 dc electrical characteristics, 3-3 design considerations electrical, 4-3, 4-3 PLL, 4-5, 4-5 power consumption, 4-4 thermal, 4-1, 4-1 DI, 13-11 Digital Audio Transmitter, 2-1, 2-1, 2-20 Digital Audio Transmitter (DAX), 1-14, 12-1 DIR, 13-10 Divide Factor (DF), 1-9 DMA, 1-9 triggered by timer, 13-24
A
ac electrical characteristics, 3-4 adder modulo, 1-7 offset, 1-7 reverse-carry, 1-7 address bus, 2-1, 2-1 Address Generation Unit, 1-6 addressing modes, 1-7 AES/EBU, 1-14, 12-1 AGU, 1-6
B
barrel shifter, 1-5 benchmark test algorithm, E-1, F-1 Boundary Scan (JTAG Port) timing diagram, 3-65 bus external address, 2-6 external data, 2-6 bus control, 2-1, 2-1 buses internal, 1-8
C
case outline drawing, 14-10 Central Processing Unit (CPU), 1-i CLKGEN, 1-9 Clock, 2-5 clock, 2-1, 2-1 external, 3-6 operation, 3-7 Clock divider, 10-14 Clock Generator (CLKGEN), 1-9 clocks internal, 3-6 CP-340, 1-14, 12-1 CPHA and CPOL (HCKR Clock Phase and Polarity Controls), 9-10
D
data ALU, 1-5
MOTOROLA
Index-1
Index
DO bit, 13-11 DO loop, 1-8 DRAM, 1-11 out of page wait states selection guide, 3-25 write access, 3-33 out of page and refresh timings 11 wait states, 3-28 15 wait states, 3-29 4 wait states, 3-25 Page mode read accesses, 3-24 wait states selection guide, 3-19 write accesses, 3-23 Page mode timings 3 wait states, 3-20 4 wait states, 3-21 refresh access, 3-34 DSP56300 core, 1-2 DSP56300 Family Manual, 1-i, 1-3 DSP56362 specifications, 3-1 GPIO (ESSI0, Port C), 7-2, 7-2 GPIO (ESSI1, Port D), 7-2 GPIO (HI08, Port B), 7-1 GPIO (Timer), 7-2 GPIO timing, 3-63 Ground, 2-4 ground, 2-1, 2-1
H
HA1, HA3-HA6 (HSAR I2C Slave Address), 9-9 hardware stack, 1-8 HBER (HCSR Bus Error), 9-18 HBIE (HCSR Bus Error Interrupt Enable), 9-16 HBUSY (HCSR Host Busy), 9-18 HCKR (SHI Clock Control Register), 9-9 HCSR Receive Interrupt Enable Bits, 9-16 SHI Control/Status Register, 9-13 HDI08, 2-1, 2-1, 2-10, 2-12, 2-12, 2-12 HDI08 timing, 3-36 HDM0-HDM5 (HCKR Divider Modulus Select), 9-11 HEN (HCSR SHI Enable), 9-13 HFIFO (HCSR FIFO Enable Control), 9-14 HFM0-HFM1 (HCKR Filter Mode), 9-12 HI08, 1-12 (GPIO), 7-1 HI2C (HCSR Serial Host Interface I2C/SPI Selection), 9-13 HIDLE (HCSR Idle), 9-15 HM0-HM1 (HCSR Serial Host Interface Mode), 9-13 HMST (HCSR Master Mode), 9-14 Host Receive Data FIFO (HRX), 9-8 Receive Data FIFO--DSP Side, 9-8 Transmit Data Register (HTX), 9-8 Transmit Data Register--DSP Side, 9-8 Host Interface, 1-12, 2-1, 2-1, 2-10, 2-12, 2-12, 2-12 Host Interface timing, 3-36 HREQ Function In SHI Slave Modes, 9-15 HRFF (HCSR Host Receive FIFO Full), 9-18 HRIE0-HRIE1 (HCSR Receive Interrupt Enable), 916 HRNE (HCSR Host Receive FIFO Not Empty), 9-18 HROE (HCSR Host Receive Overrun Error), 9-18 HRQE0-HRQE1 (HCSR Host Request Enable), 9-15 HTDE (HCSR Host Transmit Data Empty), 9-17 HTIE (HCSR Transmit Interrupt Enable), 9-16 HTUE (HCSR Host Transmit Underrun Error), 9-17
E
electrical design considerations, 4-3, 4-3 Enhanced Serial Audio Interface, 2-15, 2-15, 2-19, 219 Enhanced Synchronous Audio Interface, 2-1, 2-1 ESAI, 2-1, 2-1, 2-15, 2-15, 2-19, 2-19 receiver timing, 3-59, 3-59, 3-60, 3-60 timings, 3-55 transmitter timing, 3-58 ESAI block diagram, 10-1 ESSI0 (GPIO), 7-2, 7-2 ESSI1 (GPIO), 7-2 EXTAL jitter, 4-5 external address bus, 2-6 external bus control, 2-6, 2-7, 2-7 external clock operation, 3-6 external data bus, 2-6 external interrupt timing (negative edge-triggered), 313 external level-sensitive fast interrupt timing, 3-12 external memory access (DMA Source) timing, 3-14 External Memory Expansion Port, 2-6, 3-15
F
functional signal groups, 2-1
G
Global Data Bus, 1-8 GPIO, 1-12, 2-21
I
I2C, 1-14, 9-1, 9-19 Bit Transfer, 9-19 Bus Protocol For Host Read Cycle, 9-22
Index-2
MOTOROLA
Index
Bus Protocol For Host Write Cycle, 9-21 Data Transfer Formats, 9-21 Master Mode, 9-27 Protocol for Host Write Cycle, 9-21 Receive Data In Master Mode, 9-28 Receive Data In Slave Mode, 9-25 Slave Mode, 9-24 Start and Stop Events, 9-20 Transmit Data In Master Mode, 9-28, 9-28 Transmit Data In Slave Mode, 9-26, 9-26 I2C Bus Acknowledgment, 9-20 I2C Mode, 9-1 IEC958, 1-14, 12-1 Inter Integrated Circuit Bus, 1-14, 9-1 internal buses, 1-8 internal clocks, 3-6 Internal Exception Priorities SHI, 9-7 interrupt, 1-8 interrupt and mode control, 2-1, 2-1, 2-8, 2-8, 2-9 interrupt control, 2-8, 2-8, 2-9 interrupt timing, 3-8 external level-sensitive fast, 3-12 external negative edge-triggered, 3-13 Interrupt Vectors SHI, 9-7 INV, 13-9 mode control, 2-8, 2-8, 2-9 Mode select timing, 3-8 modulo adder, 1-7 multiplexed bus timings read, 3-42 write, 3-43 multiplier-accumulator (MAC), 1-5, 1-6
N
non-multiplexed bus timings read, 3-40 write, 3-41
O
offset adder, 1-7 OMR register, 1-8 OnCE module, 1-10, 2-21 On-Chip Emulation (OnCE) module, 1-10 on-chip memory, 1-10 Operating Mode Register (OMR), 1-8 operating mode select timing, 3-13 ordering drawings, 14-10
P
PAB, 1-9 package TQFP description, 14-1, 14-5 PAG, 1-7 PC register, 1-8 PC0-PC20 bits, 13-6 PCE, 13-11 PCU, 1-7 PDB, 1-8 PDC, 1-7 Peripheral I/O Expansion Bus, 1-8 Phase Lock Loop, 3-8 PIC, 1-7 PL0-PL20 bits, 13-5 PL21-PL22 bits, 13-5 PLL, 1-9, 2-1, 2-1, 2-5, 3-8 Characteristics, 3-8 performance issues, 4-5 PLL design considerations, 4-5, 4-5 PLL performance issues, 4-5 Port A, 2-1, 2-1, 2-6 Port B, 2-1, 2-1, 2-11, 2-11, 2-12, 2-12, 7-1 Port C, 2-1, 2-1, 2-15, 2-15, 2-19, 7-2, 7-2 Port D, 2-20, 7-2 Power, 2-3 power, 2-1, 2-1 power consumption benchmark test, E-1, F-1 power consumption design considerations, 4-4
J
Jitter, 4-5 JTAG, 1-10, 1-10, 2-21 JTAG Port timing, 3-64, 3-65 JTAG/OnCE port, 2-1, 2-1
L
LA register, 1-8 LC register, 1-8 Loop Address register (LA), 1-8 Loop Counter register (LC), 1-8
M
MAC, 1-6 Manual Conventions, 1-iii, 1-iii maximum ratings, 3-1, 3-2 mechanical drawings, 14-10 memory expansion, 1-11 external expansion port, 1-11 off-chip, 1-11 on-chip, 1-10, 1-10 Mfax system, 14-10
MOTOROLA
Index-3
Index
Prescaler Counter, 13-5 Prescaler Counter Value bits (PC0-PC20), 13-6 Prescaler Load Value bits (PL0-PL20), 13-5 Prescaler Source bits (PL21-PL22), 13-5 Program Address Bus (PAB), 1-9 Program Address Generator (PAG), 1-7 Program Control Unit (PCU), 1-7 Program Counter register (PC), 1-8 Program Data Bus (PDB), 1-8 Program Decode Controller (PDC), 1-7 Program Interrupt Controller (PIC), 1-7 Program Memory Expansion Bus, 1-8 Programming Model SHI--DSP Side, 9-6 SHI--Host Side, 9-5 SHI Enable, 9-13 Host Receive Data FIFO--DSP Side, 9-8 Host Transmit Data Register--DSP Side, 9-8 HREQ Function In SHI Slave Modes, 9-15 HSAR I2C Slave Address, 9-9 Slave Address Register, 9-9 I/O Shift Register, 9-8 Input/Output Shift Register--Host Side, 9-7 Internal Architecture, 9-2, 9-2 Internal Interrupt Priorities, 9-7 Interrupt Vectors, 9-7 Introduction, 9-1 Operation During Stop, 9-29 Programming Considerations, 9-22 Programming Model, 9-4 Programming Model--DSP Side, 9-6 Programming Model--Host Side, 9-5 Slave Address Register--DSP Side, 9-9 SHI Noise Reduction Filter Mode, 9-12 signal groupings, 2-1 signals, 2-1 Size register (SZ), 1-8 SP, 1-8 SPI, 1-14, 9-1 HCSR Bus Error, 9-18 Host Busy, 9-18 Host Receive FIFO Full, 9-18 Host Receive FIFO Not Empty, 9-18 Host Receive Overrun Error, 9-18 Host Transmit Data Empty, 9-17 Host Transmit Underrun Error, 9-17 Receive Interrupt Enable, 9-16, 9-16 Master Mode, 9-23 Slave Mode, 9-22 SPI Data-To-Clock Timing, 9-10 SPI Data-To-Clock Timing Diagram, 9-10 SPI Mode, 9-1 SR register, 1-8 SRAM interfacing, 1-11 read access, 3-17 read and write accesses, 3-15 write access, 3-18 SS, 1-8 Stack Counter register (SC), 1-8 Stack Pointer (SP), 1-8 Status Register (SR), 1-8 Stop state recovery from, 3-13, 3-14 Stop timing, 3-8 supply voltage, 3-2
R
recovery from Stop state using IRQA, 3-13, 3-14 reserved bits in TCSR register bits 3, 10, 14, 16-19, 22, 23, 13-12 in TPCR, 13-6 in TPLR, 13-6 RESET, 2-9 Reset timing, 3-8, 3-11 reverse-carry adder, 1-7
S
SC register, 1-8 Serial Host Interface, 2-1, 2-1, 2-13 Serial Host Interface (SHI), 1-14, 9-1 Serial Host Interface--See Section 5 Serial Peripheral Interface Bus, 1-14, 9-1 SHI, 1-14, 2-1, 2-1, 2-13, 9-1 Block Diagram, 9-3 Clock Control Register--DSP Side, 9-9 Clock Generator, 9-4, 9-4, 9-4 Control/Status Register--DSP Side, 9-13 Data Size, 9-13 Exception Priorities, 9-7 HCKR Clock Phase and Polarity Controls, 9-10 Divider Modulus Select, 9-11 Prescaler Rate Select, 9-11 HCKR Filter Mode, 9-12 HCSR Bus Error Interrupt Enable, 9-16 FIFO Enable Control, 9-14 Host Request Enable, 9-15 Idle, 9-15 Master Mode, 9-14 Serial Host Interface I2C/SPI Selection, 9-13 Serial Host Interface Mode, 9-13
Index-4
MOTOROLA
Index
System Stack (SS), 1-8 SZ register, 1-8 Serial Host Interface (SHI) SPI Protocol Timing, 345 Serial Host Interface (SHI) Timing, 3-45 timing interrupt, 3-8 mode select, 3-8 Reset, 3-8 Stop, 3-8 TLR, 13-12 TOF, 13-11 TOIE, 13-7 TPCR register, 13-6 bits 0-20--Prescaler Counter Value bits (PC0PC20), 13-6 bit 21-23--reserved bits, 13-6 reserved bits--bits 21-23, 13-6 TPLR register, 13-5 bits 0-20--Prescaler Load Value bits (PL0PL20), 13-5 bits 21-22--Prescaler Source bits (PL0-PL20), 13-5 bit 23--reserved bit, 13-6 reserved bit--bit 23, 13-6 TQFP pin list by number, 14-5 pin-out drawing (top), 14-1 TQFP package drawing, 14-10 Transmitter High Frequency Clock Divider, 10-14 TRM, 13-10
T
TAP, 1-10 TC0-TC3 bits, 13-7 TCF, 13-12 TCIE bit, 13-7 TCPR, 13-13 TCR, 13-13 TCSR register, 13-7 bit 0--Timer Enable bit (TE), 13-7 bit 2--Timer Compare Interrupt Enable bit (TCIE), 13-7 bits 4-7--Timer Control bits (TC0-TC3), 13-7 bit 13--Data Output bit (DO), 13-11 reserved bits--bits 3, 10, 14, 16-19, 22, 23, 13-12 TE bit, 13-7 Test Access Port (TAP), 1-10 Test Access Port timing diagram, 3-65 Test Clock (TCLK) input timing diagram, 3-64 thermal characteristics, 3-3 thermal design considerations, 4-1, 4-1 Timer, 2-1, 2-1, 2-21 event input restrictions, 3-62 timing, 3-62 timer special cases, 13-24 Timer (GPIO), 7-2 Timer Compare Interrupt Enable bit (TCIE), 13-7 Timer Control bits (TC0-TC3), 13-7 Timer Control/Status Register (TCSR), 13-7 Timer Enable bit (TE), 13-7 timer mode mode 0--GPIO, 13-14 mode 1--timer pulse, 13-15 mode 2--timer toggle, 13-16 mode 3--timer event counter, 13-17 mode 4--measurement input width, 13-18 mode 5--measurement input period, 13-19 mode 6--measurement capture, 13-20 mode 7--pulse width modulation, 13-21 mode 8--reserved, 13-22 mode 9--watchdog pulse, 13-22, 13-23 modes 11-15--reserved, 13-24 Timer module architecture, 13-1 Timer Prescaler Count Register (TPCR), 13-6 Timer Prescaler Load Register (TPLR), 13-5 Timing Digital Audio Transmitter (DAX), 3-61 Enhanced Serial Audio Interface (ESAI), 3-57 General Purpose I/O (GPIO) Timing, 3-55 OnCETM (On Chip Emulator) Timing, 3-55
V
VBA register, 1-8 Vector Base Address register (VBA), 1-8
X
X Memory Address Bus (XAB), 1-9 X Memory Data Bus (XDB), 1-8 X Memory Expansion Bus, 1-8 XAB, 1-9 XDB, 1-8
Y
Y Memory Address Bus (YAB), 1-9 Y Memory Data Bus (YDB), 1-8 Y Memory Expansion Bus, 1-8 YAB, 1-9 YDB, 1-8
MOTOROLA
Index-5
Index
Index-6
MOTOROLA
How to reach us: USA/Europe/Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 (303) 675-2140 (800) 441-2447 Asia/Pacific: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-26629298
Technical Resource Center: 1 (800) 521-6274 Japan: Nippon Motorola Ltd. SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo, Japan 81-3-5487-8488 Internet: http://motorola.com/semiconductors
DSP helpline email: dsphelp@dsp.sps.motcom
DSP56367UM/D Revision 1.4 01/02

▲Up To Search▲

Price & Availability of DSP56367

	To Download DSP56367 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .